From b0e7f54dc77a943e2bd28d4f61c5d8e2afdb8f7a Mon Sep 17 00:00:00 2001 From: Catherine Moore Date: Sat, 4 Aug 2012 18:16:57 -0400 Subject: [PATCH] xlr.md (ir_xlr_alu_clz): New insn_reservation. 2012-08-04 Catherine Moore Sandra Loosemore gcc/ * config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation. (ir_xlr_alu): Remove clz. * config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY. Co-Authored-By: Sandra Loosemore From-SVN: r190146 --- gcc/ChangeLog | 7 +++++++ gcc/config/mips/mips-cpus.def | 2 +- gcc/config/mips/xlr.md | 7 ++++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c849368db0a4..b8f0a86a0f89 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2012-08-04 Catherine Moore + Sandra Loosemore + + * config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation. + (ir_xlr_alu): Remove clz. + * config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY. + 2012-08-04 Richard Earnshaw * arm.c (arm_gen_constant): Use SImode when preparing operands for diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 62b1a19062ee..e8dc5a7a036c 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -142,7 +142,7 @@ MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0) +MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY) /* MIPS64 Release 2 processors. */ diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md index 14204694d5d0..59f863323f26 100644 --- a/gcc/config/mips/xlr.md +++ b/gcc/config/mips/xlr.md @@ -28,10 +28,15 @@ (eq_attr "type" "slt")) "xlr_main_pipe") +(define_insn_reservation "ir_xlr_alu_clz" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "clz")) + "xlr_main_pipe") + ;; Integer arithmetic instructions. (define_insn_reservation "ir_xlr_alu" 1 (and (eq_attr "cpu" "xlr") - (eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) + (eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) "xlr_main_pipe") ;; Integer arithmetic instructions. -- 2.39.5