From b4d9909f9367b87dc2a70b9f4f3fa05dc622e23f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 13 Aug 2015 15:13:56 -0700 Subject: [PATCH] 4.1-stable patches added patches: arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch clk-keystone-add-support-for-post-divider-register-for-main-pll.patch --- ...dt-bindings-to-use-post-div-register.patch | 69 +++++++++++ ...r-post-divider-register-for-main-pll.patch | 109 ++++++++++++++++++ queue-4.1/series | 2 + 3 files changed, 180 insertions(+) create mode 100644 queue-4.1/arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch create mode 100644 queue-4.1/clk-keystone-add-support-for-post-divider-register-for-main-pll.patch diff --git a/queue-4.1/arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch b/queue-4.1/arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch new file mode 100644 index 00000000000..accd4e6ee6b --- /dev/null +++ b/queue-4.1/arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch @@ -0,0 +1,69 @@ +From c1bfa985ded82cacdfc6403e78f329c44e35534a Mon Sep 17 00:00:00 2001 +From: Murali Karicheri +Date: Fri, 29 May 2015 12:04:13 -0400 +Subject: ARM: dts: keystone: fix dt bindings to use post div register + for mainpll + +From: Murali Karicheri + +commit c1bfa985ded82cacdfc6403e78f329c44e35534a upstream. + +All of the keystone devices have a separate register to hold post +divider value for main pll clock. Currently the fixed-postdiv +value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to +use a value of 2 for this. Now that we have fixed this in the pll +clock driver change the dt bindings for the same. + +Signed-off-by: Murali Karicheri +Acked-by: Santosh Shilimkar +Signed-off-by: Olof Johansson +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/k2e-clocks.dtsi | 5 ++--- + arch/arm/boot/dts/k2hk-clocks.dtsi | 5 ++--- + arch/arm/boot/dts/k2l-clocks.dtsi | 5 ++--- + 3 files changed, 6 insertions(+), 9 deletions(-) + +--- a/arch/arm/boot/dts/k2e-clocks.dtsi ++++ b/arch/arm/boot/dts/k2e-clocks.dtsi +@@ -13,9 +13,8 @@ clocks { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>; +- reg-names = "control", "multiplier"; +- fixed-postdiv = <2>; ++ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; ++ reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { +--- a/arch/arm/boot/dts/k2hk-clocks.dtsi ++++ b/arch/arm/boot/dts/k2hk-clocks.dtsi +@@ -22,9 +22,8 @@ clocks { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>; +- reg-names = "control", "multiplier"; +- fixed-postdiv = <2>; ++ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; ++ reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { +--- a/arch/arm/boot/dts/k2l-clocks.dtsi ++++ b/arch/arm/boot/dts/k2l-clocks.dtsi +@@ -22,9 +22,8 @@ clocks { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>; +- reg-names = "control", "multiplier"; +- fixed-postdiv = <2>; ++ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; ++ reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { diff --git a/queue-4.1/clk-keystone-add-support-for-post-divider-register-for-main-pll.patch b/queue-4.1/clk-keystone-add-support-for-post-divider-register-for-main-pll.patch new file mode 100644 index 00000000000..e46c6a42eda --- /dev/null +++ b/queue-4.1/clk-keystone-add-support-for-post-divider-register-for-main-pll.patch @@ -0,0 +1,109 @@ +From 02fdfd708fd252a778709beb6c65d5e7360341ac Mon Sep 17 00:00:00 2001 +From: Murali Karicheri +Date: Fri, 29 May 2015 12:04:12 -0400 +Subject: clk: keystone: add support for post divider register for main pll + +From: Murali Karicheri + +commit 02fdfd708fd252a778709beb6c65d5e7360341ac upstream. + +Main PLL controller has post divider bits in a separate register in +pll controller. Use the value from this register instead of fixed +divider when available. + +Signed-off-by: Murali Karicheri +Signed-off-by: Michael Turquette +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/clock/keystone-pll.txt | 8 +++--- + drivers/clk/keystone/pll.c | 20 +++++++++++++-- + 2 files changed, 22 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/clock/keystone-pll.txt ++++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt +@@ -15,8 +15,8 @@ Required properties: + - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" + - clocks : parent clock phandle + - reg - pll control0 and pll multipler registers +-- reg-names : control and multiplier. The multiplier is applicable only for +- main pll clock ++- reg-names : control, multiplier and post-divider. The multiplier and ++ post-divider registers are applicable only for main pll clock + - fixed-postdiv : fixed post divider value. If absent, use clkod register bits + for postdiv + +@@ -25,8 +25,8 @@ Example: + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; +- reg = <0x02620350 4>, <0x02310110 4>; +- reg-names = "control", "multiplier"; ++ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; ++ reg-names = "control", "multiplier", "post-divider"; + fixed-postdiv = <2>; + }; + +--- a/drivers/clk/keystone/pll.c ++++ b/drivers/clk/keystone/pll.c +@@ -37,7 +37,8 @@ + * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL + * or PA PLL available on keystone2. These PLLs are controlled by + * this register. Main PLL is controlled by a PLL controller. +- * @pllm: PLL register map address ++ * @pllm: PLL register map address for multiplier bits ++ * @pllod: PLL register map address for post divider bits + * @pll_ctl0: PLL controller map address + * @pllm_lower_mask: multiplier lower mask + * @pllm_upper_mask: multiplier upper mask +@@ -53,6 +54,7 @@ struct clk_pll_data { + u32 phy_pllm; + u32 phy_pll_ctl0; + void __iomem *pllm; ++ void __iomem *pllod; + void __iomem *pll_ctl0; + u32 pllm_lower_mask; + u32 pllm_upper_mask; +@@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(s + /* read post divider from od bits*/ + postdiv = ((val & pll_data->clkod_mask) >> + pll_data->clkod_shift) + 1; +- else ++ else if (pll_data->pllod) { ++ postdiv = readl(pll_data->pllod); ++ postdiv = ((postdiv & pll_data->clkod_mask) >> ++ pll_data->clkod_shift) + 1; ++ } else + postdiv = pll_data->postdiv; + + rate /= (prediv + 1); +@@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(stru + /* assume the PLL has output divider register bits */ + pll_data->clkod_mask = CLKOD_MASK; + pll_data->clkod_shift = CLKOD_SHIFT; ++ ++ /* ++ * Check if there is an post-divider register. If not ++ * assume od bits are part of control register. ++ */ ++ i = of_property_match_string(node, "reg-names", ++ "post-divider"); ++ pll_data->pllod = of_iomap(node, i); + } + + i = of_property_match_string(node, "reg-names", "control"); + pll_data->pll_ctl0 = of_iomap(node, i); + if (!pll_data->pll_ctl0) { + pr_err("%s: ioremap failed\n", __func__); ++ iounmap(pll_data->pllod); + goto out; + } + +@@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(stru + pll_data->pllm = of_iomap(node, i); + if (!pll_data->pllm) { + iounmap(pll_data->pll_ctl0); ++ iounmap(pll_data->pllod); + goto out; + } + } diff --git a/queue-4.1/series b/queue-4.1/series index c5ee20f037e..838b7579f61 100644 --- a/queue-4.1/series +++ b/queue-4.1/series @@ -40,3 +40,5 @@ crypto-nx-fixing-nx-data-alignment-with-nx_sg-list.patch crypto-nx-fixing-sha-update-bug.patch crypto-nx-fix-reentrancy-bugs.patch sparc64-fix-userspace-fpu-register-corruptions.patch +clk-keystone-add-support-for-post-divider-register-for-main-pll.patch +arm-dts-keystone-fix-dt-bindings-to-use-post-div-register.patch -- 2.47.2