From b54b0c88aecb8cf7699b3c9af52d4e8fda271e8c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 12 Mar 2017 20:16:54 +0100 Subject: [PATCH] 4.10-stable patches added patches: drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch drm-ast-call-open_key-before-enable_mmio-in-post-code.patch drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch drm-ast-fix-test-for-vga-enabled.patch drm-ast-handle-configuration-without-p2a-bridge.patch drm-atomic-fix-an-error-code-in-mode_fixup.patch drm-cancel-drm_fb_helper_dirty_work-on-unload.patch drm-cancel-drm_fb_helper_resume_work-on-unload.patch drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch drm-radeon-handle-vfct-with-multiple-vbios-images.patch drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch --- ...es-to-dce11-possible-crtc-mask-setup.patch | 45 ++ ...adless-before-calling-compute_clocks.patch | 33 ++ ..._key-before-enable_mmio-in-post-code.patch | 34 ++ ...post-failure-without-bmc-fw-or-vbios.patch | 74 +++ .../drm-ast-fix-test-for-vga-enabled.patch | 42 ++ ...dle-configuration-without-p2a-bridge.patch | 411 ++++++++++++++++ ...omic-fix-an-error-code-in-mode_fixup.patch | 38 ++ ...l-drm_fb_helper_dirty_work-on-unload.patch | 41 ++ ...-drm_fb_helper_resume_work-on-unload.patch | 40 ++ ..._force_8bpc-quirk-for-rotel-rsx-1058.patch | 51 ++ ...e-access-to-stolen-memory-as-a-guest.patch | 42 ++ ...tve-do-not-set-the-regulator-voltage.patch | 57 +++ ...ndle-vfct-with-multiple-vbios-images.patch | 112 +++++ ...-bos-being-swapped-out-are-cacheable.patch | 51 ++ ...-around-drm-removal-of-control-nodes.patch | 73 +++ ...u-update-tile-table-for-oland-hainan.patch | 465 ++++++++++++++++++ queue-4.10/series | 16 + 17 files changed, 1625 insertions(+) create mode 100644 queue-4.10/drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch create mode 100644 queue-4.10/drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch create mode 100644 queue-4.10/drm-ast-call-open_key-before-enable_mmio-in-post-code.patch create mode 100644 queue-4.10/drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch create mode 100644 queue-4.10/drm-ast-fix-test-for-vga-enabled.patch create mode 100644 queue-4.10/drm-ast-handle-configuration-without-p2a-bridge.patch create mode 100644 queue-4.10/drm-atomic-fix-an-error-code-in-mode_fixup.patch create mode 100644 queue-4.10/drm-cancel-drm_fb_helper_dirty_work-on-unload.patch create mode 100644 queue-4.10/drm-cancel-drm_fb_helper_resume_work-on-unload.patch create mode 100644 queue-4.10/drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch create mode 100644 queue-4.10/drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch create mode 100644 queue-4.10/drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch create mode 100644 queue-4.10/drm-radeon-handle-vfct-with-multiple-vbios-images.patch create mode 100644 queue-4.10/drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch create mode 100644 queue-4.10/drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch create mode 100644 queue-4.10/revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch diff --git a/queue-4.10/drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch b/queue-4.10/drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch new file mode 100644 index 00000000000..0d734c6d9d5 --- /dev/null +++ b/queue-4.10/drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch @@ -0,0 +1,45 @@ +From 4ce3bd45b351633f2a0512c587f7fcba2ce044e8 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 10 Feb 2017 00:00:52 -0500 +Subject: drm/amdgpu: add more cases to DCE11 possible crtc mask setup +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 4ce3bd45b351633f2a0512c587f7fcba2ce044e8 upstream. + +Add cases for asics with 3 and 5 crtcs. Fixes an artificial +limitation on asics with 3 or 5 crtcs. + +Fixes: +https://bugs.freedesktop.org/show_bug.cgi?id=99744 + +Reviewed-by: Michel Dänzer +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -3737,9 +3737,15 @@ static void dce_v11_0_encoder_add(struct + default: + encoder->possible_crtcs = 0x3; + break; ++ case 3: ++ encoder->possible_crtcs = 0x7; ++ break; + case 4: + encoder->possible_crtcs = 0xf; + break; ++ case 5: ++ encoder->possible_crtcs = 0x1f; ++ break; + case 6: + encoder->possible_crtcs = 0x3f; + break; diff --git a/queue-4.10/drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch b/queue-4.10/drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch new file mode 100644 index 00000000000..05203c89a27 --- /dev/null +++ b/queue-4.10/drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch @@ -0,0 +1,33 @@ +From c10c8f7c27103bd7ac02d041d9d6e97296d48fc1 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 10 Feb 2017 18:09:32 -0500 +Subject: drm/amdgpu/pm: check for headless before calling compute_clocks + +From: Alex Deucher + +commit c10c8f7c27103bd7ac02d041d9d6e97296d48fc1 upstream. + +Don't update display bandwidth on headless asics. + +bug: +https://bugs.freedesktop.org/show_bug.cgi?id=99387 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +@@ -1252,7 +1252,8 @@ void amdgpu_pm_compute_clocks(struct amd + if (!adev->pm.dpm_enabled) + return; + +- amdgpu_display_bandwidth_update(adev); ++ if (adev->mode_info.num_crtc) ++ amdgpu_display_bandwidth_update(adev); + + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; diff --git a/queue-4.10/drm-ast-call-open_key-before-enable_mmio-in-post-code.patch b/queue-4.10/drm-ast-call-open_key-before-enable_mmio-in-post-code.patch new file mode 100644 index 00000000000..437de71baa6 --- /dev/null +++ b/queue-4.10/drm-ast-call-open_key-before-enable_mmio-in-post-code.patch @@ -0,0 +1,34 @@ +From 9bb92f51558f2ef5f56c257bdcea0588f31d857e Mon Sep 17 00:00:00 2001 +From: "Y.C. Chen" +Date: Wed, 22 Feb 2017 15:14:19 +1100 +Subject: drm/ast: Call open_key before enable_mmio in POST code + +From: Y.C. Chen + +commit 9bb92f51558f2ef5f56c257bdcea0588f31d857e upstream. + +open_key enables access the registers used by enable_mmio + +Signed-off-by: Y.C. Chen +Signed-off-by: Benjamin Herrenschmidt +Acked-by: Joel Stanley +Tested-by: Y.C. Chen +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/ast/ast_post.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/ast/ast_post.c ++++ b/drivers/gpu/drm/ast/ast_post.c +@@ -371,8 +371,8 @@ void ast_post_gpu(struct drm_device *dev + pci_write_config_dword(ast->dev->pdev, 0x04, reg); + + ast_enable_vga(dev); +- ast_enable_mmio(dev); + ast_open_key(ast); ++ ast_enable_mmio(dev); + ast_set_def_ext_reg(dev); + + if (ast->config_mode == ast_use_p2a) { diff --git a/queue-4.10/drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch b/queue-4.10/drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch new file mode 100644 index 00000000000..8f275a35f4d --- /dev/null +++ b/queue-4.10/drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch @@ -0,0 +1,74 @@ +From 3856081eede297b617560b85e948cfb00bb395ec Mon Sep 17 00:00:00 2001 +From: "Y.C. Chen" +Date: Thu, 23 Feb 2017 15:52:33 +0800 +Subject: drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS + +From: Y.C. Chen + +commit 3856081eede297b617560b85e948cfb00bb395ec upstream. + +The current POST code for the AST2300/2400 family doesn't work properly +if the chip hasn't been initialized previously by either the BMC own FW +or the VBIOS. This fixes it. + +Signed-off-by: Y.C. Chen +Signed-off-by: Benjamin Herrenschmidt +Tested-by: Y.C. Chen +Acked-by: Joel Stanley +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/ast/ast_post.c | 38 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 35 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/ast/ast_post.c ++++ b/drivers/gpu/drm/ast/ast_post.c +@@ -1631,12 +1631,44 @@ static void ast_init_dram_2300(struct dr + temp |= 0x73; + ast_write32(ast, 0x12008, temp); + ++ param.dram_freq = 396; + param.dram_type = AST_DDR3; ++ temp = ast_mindwm(ast, 0x1e6e2070); + if (temp & 0x01000000) + param.dram_type = AST_DDR2; +- param.dram_chipid = ast->dram_type; +- param.dram_freq = ast->mclk; +- param.vram_size = ast->vram_size; ++ switch (temp & 0x18000000) { ++ case 0: ++ param.dram_chipid = AST_DRAM_512Mx16; ++ break; ++ default: ++ case 0x08000000: ++ param.dram_chipid = AST_DRAM_1Gx16; ++ break; ++ case 0x10000000: ++ param.dram_chipid = AST_DRAM_2Gx16; ++ break; ++ case 0x18000000: ++ param.dram_chipid = AST_DRAM_4Gx16; ++ break; ++ } ++ switch (temp & 0x0c) { ++ default: ++ case 0x00: ++ param.vram_size = AST_VIDMEM_SIZE_8M; ++ break; ++ ++ case 0x04: ++ param.vram_size = AST_VIDMEM_SIZE_16M; ++ break; ++ ++ case 0x08: ++ param.vram_size = AST_VIDMEM_SIZE_32M; ++ break; ++ ++ case 0x0c: ++ param.vram_size = AST_VIDMEM_SIZE_64M; ++ break; ++ } + + if (param.dram_type == AST_DDR3) { + get_ddr3_info(ast, ¶m); diff --git a/queue-4.10/drm-ast-fix-test-for-vga-enabled.patch b/queue-4.10/drm-ast-fix-test-for-vga-enabled.patch new file mode 100644 index 00000000000..43df6ed4aa7 --- /dev/null +++ b/queue-4.10/drm-ast-fix-test-for-vga-enabled.patch @@ -0,0 +1,42 @@ +From 905f21a49d388de3e99438235f3301cabf0c0ef4 Mon Sep 17 00:00:00 2001 +From: "Y.C. Chen" +Date: Wed, 22 Feb 2017 15:10:50 +1100 +Subject: drm/ast: Fix test for VGA enabled + +From: Y.C. Chen + +commit 905f21a49d388de3e99438235f3301cabf0c0ef4 upstream. + +The test to see if VGA was already enabled is doing an unnecessary +second test from a register that may or may not have been initialized +to a valid value. Remove it. + +Signed-off-by: Y.C. Chen +Signed-off-by: Benjamin Herrenschmidt +Acked-by: Joel Stanley +Tested-by: Y.C. Chen +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/ast/ast_post.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/ast/ast_post.c ++++ b/drivers/gpu/drm/ast/ast_post.c +@@ -58,13 +58,9 @@ bool ast_is_vga_enabled(struct drm_devic + /* TODO 1180 */ + } else { + ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); +- if (ch) { +- ast_open_key(ast); +- ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff); +- return ch & 0x04; +- } ++ return !!(ch & 0x01); + } +- return 0; ++ return false; + } + + static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; diff --git a/queue-4.10/drm-ast-handle-configuration-without-p2a-bridge.patch b/queue-4.10/drm-ast-handle-configuration-without-p2a-bridge.patch new file mode 100644 index 00000000000..adcb8d0cee6 --- /dev/null +++ b/queue-4.10/drm-ast-handle-configuration-without-p2a-bridge.patch @@ -0,0 +1,411 @@ +From 71f677a91046599ece96ebab21df956ce909c456 Mon Sep 17 00:00:00 2001 +From: Russell Currey +Date: Fri, 17 Feb 2017 14:33:01 +1100 +Subject: drm/ast: Handle configuration without P2A bridge + +From: Russell Currey + +commit 71f677a91046599ece96ebab21df956ce909c456 upstream. + +The ast driver configures a window to enable access into BMC +memory space in order to read some configuration registers. + +If this window is disabled, which it can be from the BMC side, +the ast driver can't function. + +Closing this window is a necessity for security if a machine's +host side and BMC side are controlled by different parties; +i.e. a cloud provider offering machines "bare metal". + +A recent patch went in to try to check if that window is open +but it does so by trying to access the registers in question +and testing if the result is 0xffffffff. + +This method will trigger a PCIe error when the window is closed +which on some systems will be fatal (it will trigger an EEH +for example on POWER which will take out the device). + +This patch improves this in two ways: + + - First, if the firmware has put properties in the device-tree +containing the relevant configuration information, we use these. + + - Otherwise, a bit in one of the SCU scratch registers (which +are readable via the VGA register space and writeable by the BMC) +will indicate if the BMC has closed the window. This bit has been +defined by Y.C Chen from Aspeed. + +If the window is closed and the configuration isn't available from +the device-tree, some sane defaults are used. Those defaults are +hopefully sufficient for standard video modes used on a server. + +Signed-off-by: Russell Currey +Acked-by: Joel Stanley +Signed-off-by: Benjamin Herrenschmidt +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/ast/ast_drv.h | 6 + drivers/gpu/drm/ast/ast_main.c | 264 +++++++++++++++++++++++++---------------- + drivers/gpu/drm/ast/ast_post.c | 7 - + 3 files changed, 168 insertions(+), 109 deletions(-) + +--- a/drivers/gpu/drm/ast/ast_drv.h ++++ b/drivers/gpu/drm/ast/ast_drv.h +@@ -113,7 +113,11 @@ struct ast_private { + struct ttm_bo_kmap_obj cache_kmap; + int next_cursor; + bool support_wide_screen; +- bool DisableP2A; ++ enum { ++ ast_use_p2a, ++ ast_use_dt, ++ ast_use_defaults ++ } config_mode; + + enum ast_tx_chip tx_chip_type; + u8 dp501_maxclk; +--- a/drivers/gpu/drm/ast/ast_main.c ++++ b/drivers/gpu/drm/ast/ast_main.c +@@ -62,13 +62,84 @@ uint8_t ast_get_index_reg_mask(struct as + return ret; + } + ++static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) ++{ ++ struct device_node *np = dev->pdev->dev.of_node; ++ struct ast_private *ast = dev->dev_private; ++ uint32_t data, jregd0, jregd1; ++ ++ /* Defaults */ ++ ast->config_mode = ast_use_defaults; ++ *scu_rev = 0xffffffff; ++ ++ /* Check if we have device-tree properties */ ++ if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", ++ scu_rev)) { ++ /* We do, disable P2A access */ ++ ast->config_mode = ast_use_dt; ++ DRM_INFO("Using device-tree for configuration\n"); ++ return; ++ } ++ ++ /* Not all families have a P2A bridge */ ++ if (dev->pdev->device != PCI_CHIP_AST2000) ++ return; ++ ++ /* ++ * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge ++ * is disabled. We force using P2A if VGA only mode bit ++ * is set D[7] ++ */ ++ jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); ++ jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); ++ if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { ++ /* Double check it's actually working */ ++ data = ast_read32(ast, 0xf004); ++ if (data != 0xFFFFFFFF) { ++ /* P2A works, grab silicon revision */ ++ ast->config_mode = ast_use_p2a; ++ ++ DRM_INFO("Using P2A bridge for configuration\n"); ++ ++ /* Read SCU7c (silicon revision register) */ ++ ast_write32(ast, 0xf004, 0x1e6e0000); ++ ast_write32(ast, 0xf000, 0x1); ++ *scu_rev = ast_read32(ast, 0x1207c); ++ return; ++ } ++ } ++ ++ /* We have a P2A bridge but it's disabled */ ++ DRM_INFO("P2A bridge disabled, using default configuration\n"); ++} + + static int ast_detect_chip(struct drm_device *dev, bool *need_post) + { + struct ast_private *ast = dev->dev_private; +- uint32_t data, jreg; ++ uint32_t jreg, scu_rev; ++ ++ /* ++ * If VGA isn't enabled, we need to enable now or subsequent ++ * access to the scratch registers will fail. We also inform ++ * our caller that it needs to POST the chip ++ * (Assumption: VGA not enabled -> need to POST) ++ */ ++ if (!ast_is_vga_enabled(dev)) { ++ ast_enable_vga(dev); ++ DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); ++ *need_post = true; ++ } else ++ *need_post = false; ++ ++ ++ /* Enable extended register access */ ++ ast_enable_mmio(dev); + ast_open_key(ast); + ++ /* Find out whether P2A works or whether to use device-tree */ ++ ast_detect_config_mode(dev, &scu_rev); ++ ++ /* Identify chipset */ + if (dev->pdev->device == PCI_CHIP_AST1180) { + ast->chip = AST1100; + DRM_INFO("AST 1180 detected\n"); +@@ -80,12 +151,7 @@ static int ast_detect_chip(struct drm_de + ast->chip = AST2300; + DRM_INFO("AST 2300 detected\n"); + } else if (dev->pdev->revision >= 0x10) { +- uint32_t data; +- ast_write32(ast, 0xf004, 0x1e6e0000); +- ast_write32(ast, 0xf000, 0x1); +- +- data = ast_read32(ast, 0x1207c); +- switch (data & 0x0300) { ++ switch (scu_rev & 0x0300) { + case 0x0200: + ast->chip = AST1100; + DRM_INFO("AST 1100 detected\n"); +@@ -110,26 +176,6 @@ static int ast_detect_chip(struct drm_de + } + } + +- /* +- * If VGA isn't enabled, we need to enable now or subsequent +- * access to the scratch registers will fail. We also inform +- * our caller that it needs to POST the chip +- * (Assumption: VGA not enabled -> need to POST) +- */ +- if (!ast_is_vga_enabled(dev)) { +- ast_enable_vga(dev); +- ast_enable_mmio(dev); +- DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); +- *need_post = true; +- } else +- *need_post = false; +- +- /* Check P2A Access */ +- ast->DisableP2A = true; +- data = ast_read32(ast, 0xf004); +- if (data != 0xFFFFFFFF) +- ast->DisableP2A = false; +- + /* Check if we support wide screen */ + switch (ast->chip) { + case AST1180: +@@ -146,17 +192,12 @@ static int ast_detect_chip(struct drm_de + ast->support_wide_screen = true; + else { + ast->support_wide_screen = false; +- if (ast->DisableP2A == false) { +- /* Read SCU7c (silicon revision register) */ +- ast_write32(ast, 0xf004, 0x1e6e0000); +- ast_write32(ast, 0xf000, 0x1); +- data = ast_read32(ast, 0x1207c); +- data &= 0x300; +- if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ +- ast->support_wide_screen = true; +- if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ +- ast->support_wide_screen = true; +- } ++ if (ast->chip == AST2300 && ++ (scu_rev & 0x300) == 0x0) /* ast1300 */ ++ ast->support_wide_screen = true; ++ if (ast->chip == AST2400 && ++ (scu_rev & 0x300) == 0x100) /* ast1400 */ ++ ast->support_wide_screen = true; + } + break; + } +@@ -220,85 +261,102 @@ static int ast_detect_chip(struct drm_de + + static int ast_get_dram_info(struct drm_device *dev) + { ++ struct device_node *np = dev->pdev->dev.of_node; + struct ast_private *ast = dev->dev_private; +- uint32_t data, data2; +- uint32_t denum, num, div, ref_pll; ++ uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; ++ uint32_t denum, num, div, ref_pll, dsel; + +- if (ast->DisableP2A) +- { ++ switch (ast->config_mode) { ++ case ast_use_dt: ++ /* ++ * If some properties are missing, use reasonable ++ * defaults for AST2400 ++ */ ++ if (of_property_read_u32(np, "aspeed,mcr-configuration", ++ &mcr_cfg)) ++ mcr_cfg = 0x00000577; ++ if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", ++ &mcr_scu_mpll)) ++ mcr_scu_mpll = 0x000050C0; ++ if (of_property_read_u32(np, "aspeed,mcr-scu-strap", ++ &mcr_scu_strap)) ++ mcr_scu_strap = 0; ++ break; ++ case ast_use_p2a: ++ ast_write32(ast, 0xf004, 0x1e6e0000); ++ ast_write32(ast, 0xf000, 0x1); ++ mcr_cfg = ast_read32(ast, 0x10004); ++ mcr_scu_mpll = ast_read32(ast, 0x10120); ++ mcr_scu_strap = ast_read32(ast, 0x10170); ++ break; ++ case ast_use_defaults: ++ default: + ast->dram_bus_width = 16; + ast->dram_type = AST_DRAM_1Gx16; + ast->mclk = 396; ++ return 0; + } +- else +- { +- ast_write32(ast, 0xf004, 0x1e6e0000); +- ast_write32(ast, 0xf000, 0x1); +- data = ast_read32(ast, 0x10004); + +- if (data & 0x40) +- ast->dram_bus_width = 16; +- else +- ast->dram_bus_width = 32; +- +- if (ast->chip == AST2300 || ast->chip == AST2400) { +- switch (data & 0x03) { +- case 0: +- ast->dram_type = AST_DRAM_512Mx16; +- break; +- default: +- case 1: +- ast->dram_type = AST_DRAM_1Gx16; +- break; +- case 2: +- ast->dram_type = AST_DRAM_2Gx16; +- break; +- case 3: +- ast->dram_type = AST_DRAM_4Gx16; +- break; +- } +- } else { +- switch (data & 0x0c) { +- case 0: +- case 4: +- ast->dram_type = AST_DRAM_512Mx16; +- break; +- case 8: +- if (data & 0x40) +- ast->dram_type = AST_DRAM_1Gx16; +- else +- ast->dram_type = AST_DRAM_512Mx32; +- break; +- case 0xc: +- ast->dram_type = AST_DRAM_1Gx32; +- break; +- } +- } ++ if (mcr_cfg & 0x40) ++ ast->dram_bus_width = 16; ++ else ++ ast->dram_bus_width = 32; + +- data = ast_read32(ast, 0x10120); +- data2 = ast_read32(ast, 0x10170); +- if (data2 & 0x2000) +- ref_pll = 14318; +- else +- ref_pll = 12000; +- +- denum = data & 0x1f; +- num = (data & 0x3fe0) >> 5; +- data = (data & 0xc000) >> 14; +- switch (data) { +- case 3: +- div = 0x4; ++ if (ast->chip == AST2300 || ast->chip == AST2400) { ++ switch (mcr_cfg & 0x03) { ++ case 0: ++ ast->dram_type = AST_DRAM_512Mx16; + break; +- case 2: ++ default: + case 1: +- div = 0x2; ++ ast->dram_type = AST_DRAM_1Gx16; + break; +- default: +- div = 0x1; ++ case 2: ++ ast->dram_type = AST_DRAM_2Gx16; ++ break; ++ case 3: ++ ast->dram_type = AST_DRAM_4Gx16; ++ break; ++ } ++ } else { ++ switch (mcr_cfg & 0x0c) { ++ case 0: ++ case 4: ++ ast->dram_type = AST_DRAM_512Mx16; ++ break; ++ case 8: ++ if (mcr_cfg & 0x40) ++ ast->dram_type = AST_DRAM_1Gx16; ++ else ++ ast->dram_type = AST_DRAM_512Mx32; ++ break; ++ case 0xc: ++ ast->dram_type = AST_DRAM_1Gx32; + break; + } +- ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); + } ++ ++ if (mcr_scu_strap & 0x2000) ++ ref_pll = 14318; ++ else ++ ref_pll = 12000; ++ ++ denum = mcr_scu_mpll & 0x1f; ++ num = (mcr_scu_mpll & 0x3fe0) >> 5; ++ dsel = (mcr_scu_mpll & 0xc000) >> 14; ++ switch (dsel) { ++ case 3: ++ div = 0x4; ++ break; ++ case 2: ++ case 1: ++ div = 0x2; ++ break; ++ default: ++ div = 0x1; ++ break; ++ } ++ ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); + return 0; + } + +--- a/drivers/gpu/drm/ast/ast_post.c ++++ b/drivers/gpu/drm/ast/ast_post.c +@@ -379,17 +379,14 @@ void ast_post_gpu(struct drm_device *dev + ast_open_key(ast); + ast_set_def_ext_reg(dev); + +- if (ast->DisableP2A == false) +- { ++ if (ast->config_mode == ast_use_p2a) { + if (ast->chip == AST2300 || ast->chip == AST2400) + ast_init_dram_2300(dev); + else + ast_init_dram_reg(dev); + + ast_init_3rdtx(dev); +- } +- else +- { ++ } else { + if (ast->tx_chip_type != AST_TX_NONE) + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ + } diff --git a/queue-4.10/drm-atomic-fix-an-error-code-in-mode_fixup.patch b/queue-4.10/drm-atomic-fix-an-error-code-in-mode_fixup.patch new file mode 100644 index 00000000000..bb3c9906933 --- /dev/null +++ b/queue-4.10/drm-atomic-fix-an-error-code-in-mode_fixup.patch @@ -0,0 +1,38 @@ +From f9ad86e42d0303eeb8e0d41bb208153022ebd9d2 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Wed, 8 Feb 2017 02:46:01 +0300 +Subject: drm/atomic: fix an error code in mode_fixup() + +From: Dan Carpenter + +commit f9ad86e42d0303eeb8e0d41bb208153022ebd9d2 upstream. + +Having "ret" be a bool type works for everything except +ret = funcs->atomic_check(). The other functions all return zero on +error but ->atomic_check() returns negative error codes. We want to +propagate the error code but instead we return 1. + +I found this bug with static analysis and I don't know if it affects +run time. + +Fixes: 4cd4df8080a3 ("drm/atomic: Add ->atomic_check() to encoder helpers") +Signed-off-by: Dan Carpenter +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/20170207234601.GA23981@mwanda +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_atomic_helper.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_atomic_helper.c ++++ b/drivers/gpu/drm/drm_atomic_helper.c +@@ -362,7 +362,7 @@ mode_fixup(struct drm_atomic_state *stat + struct drm_connector *connector; + struct drm_connector_state *conn_state; + int i; +- bool ret; ++ int ret; + + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (!crtc_state->mode_changed && diff --git a/queue-4.10/drm-cancel-drm_fb_helper_dirty_work-on-unload.patch b/queue-4.10/drm-cancel-drm_fb_helper_dirty_work-on-unload.patch new file mode 100644 index 00000000000..1db6db5ea94 --- /dev/null +++ b/queue-4.10/drm-cancel-drm_fb_helper_dirty_work-on-unload.patch @@ -0,0 +1,41 @@ +From f21b9a92ca7c29382909eaab9facc2cf46f2cc0b Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 7 Feb 2017 12:49:55 +0000 +Subject: drm: Cancel drm_fb_helper_dirty_work on unload +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit f21b9a92ca7c29382909eaab9facc2cf46f2cc0b upstream. + +We can not allow the worker to run after its fbdev, or even the module, +has been removed. + +Fixes: eaa434defaca ("drm/fb-helper: Add fb_deferred_io support") +Signed-off-by: Chris Wilson +Cc: Noralf Trønnes +Cc: Daniel Vetter +Cc: Jani Nikula +Cc: Sean Paul +Cc: dri-devel@lists.freedesktop.org +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/20170207124956.14954-1-chris@chris-wilson.co.uk +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_fb_helper.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/drm_fb_helper.c ++++ b/drivers/gpu/drm/drm_fb_helper.c +@@ -856,6 +856,8 @@ void drm_fb_helper_fini(struct drm_fb_he + if (!drm_fbdev_emulation) + return; + ++ cancel_work_sync(&fb_helper->dirty_work); ++ + mutex_lock(&kernel_fb_helper_lock); + if (!list_empty(&fb_helper->kernel_fb_list)) { + list_del(&fb_helper->kernel_fb_list); diff --git a/queue-4.10/drm-cancel-drm_fb_helper_resume_work-on-unload.patch b/queue-4.10/drm-cancel-drm_fb_helper_resume_work-on-unload.patch new file mode 100644 index 00000000000..52361b7863e --- /dev/null +++ b/queue-4.10/drm-cancel-drm_fb_helper_resume_work-on-unload.patch @@ -0,0 +1,40 @@ +From 24f76b2c87ed68f79f9f0705b11ccbefaaa0d390 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 7 Feb 2017 12:49:56 +0000 +Subject: drm: Cancel drm_fb_helper_resume_work on unload +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 24f76b2c87ed68f79f9f0705b11ccbefaaa0d390 upstream. + +We can not allow the worker to run after its fbdev, or even the module, +has been removed. + +Fixes: cfe63423d9be ("drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked()") +Signed-off-by: Chris Wilson +Cc: Noralf Trønnes +Cc: Daniel Vetter +Cc: Jani Nikula +Cc: Sean Paul +Cc: dri-devel@lists.freedesktop.org +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/20170207124956.14954-2-chris@chris-wilson.co.uk +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_fb_helper.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/drm_fb_helper.c ++++ b/drivers/gpu/drm/drm_fb_helper.c +@@ -856,6 +856,7 @@ void drm_fb_helper_fini(struct drm_fb_he + if (!drm_fbdev_emulation) + return; + ++ cancel_work_sync(&fb_helper->resume_work); + cancel_work_sync(&fb_helper->dirty_work); + + mutex_lock(&kernel_fb_helper_lock); diff --git a/queue-4.10/drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch b/queue-4.10/drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch new file mode 100644 index 00000000000..e7dabec664e --- /dev/null +++ b/queue-4.10/drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch @@ -0,0 +1,51 @@ +From 36fc579761b50784b63dafd0f2e796b659e0f5ee Mon Sep 17 00:00:00 2001 +From: Tomeu Vizoso +Date: Mon, 20 Feb 2017 16:25:45 +0100 +Subject: drm/edid: Add EDID_QUIRK_FORCE_8BPC quirk for Rotel RSX-1058 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Tomeu Vizoso + +commit 36fc579761b50784b63dafd0f2e796b659e0f5ee upstream. + +Rotel RSX-1058 is a receiver with 4 HDMI inputs and a HDMI output, all +1.1. + +When a sink that supports deep color is connected to the output, the +receiver will send EDIDs that advertise this capability, even if it +isn't possible with HDMI versions earlier than 1.3. + +Currently the kernel is assuming that deep color is possible and the +sink displays an error. + +This quirk will make sure that deep color isn't used with this +particular receiver. + +Fixes: 7a0baa623446 ("Revert "drm/i915: Disable 12bpc hdmi for now"") +Signed-off-by: Tomeu Vizoso +Link: http://patchwork.freedesktop.org/patch/msgid/20170220152545.13153-1-tomeu.vizoso@collabora.com +Cc: Matt Horan +Tested-by: Matt Horan +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99869 +Reviewed-by: Ville Syrjälä +Signed-off-by: Ville Syrjälä +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_edid.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -145,6 +145,9 @@ static struct edid_quirk { + + /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ + { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, ++ ++ /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ ++ { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, + }; + + /* diff --git a/queue-4.10/drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch b/queue-4.10/drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch new file mode 100644 index 00000000000..045046479d6 --- /dev/null +++ b/queue-4.10/drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch @@ -0,0 +1,42 @@ +From ddd09373628adcbdc3f7b9098d22328834f8d772 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Wed, 9 Nov 2016 10:39:05 +0000 +Subject: drm/i915/gvt: Disable access to stolen memory as a guest + +From: Chris Wilson + +commit ddd09373628adcbdc3f7b9098d22328834f8d772 upstream. + +Explicitly disable stolen memory when running as a guest in a virtual +machine, since the memory is not mediated between clients and reserved +entirely for the host. The actual size should be reported as zero, but +like every other quirk we want to tell the user what is happening. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99028 +Signed-off-by: Chris Wilson +Cc: Zhenyu Wang +Cc: Joonas Lahtinen +Link: http://patchwork.freedesktop.org/patch/msgid/20161109103905.17860-1-chris@chris-wilson.co.uk +Reviewed-by: Zhenyu Wang +(cherry picked from commit 04a68a35ce6d7b54749989f943993020f48fed62) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_gem_stolen.c ++++ b/drivers/gpu/drm/i915/i915_gem_stolen.c +@@ -414,6 +414,11 @@ int i915_gem_init_stolen(struct drm_i915 + + mutex_init(&dev_priv->mm.stolen_lock); + ++ if (intel_vgpu_active(dev_priv)) { ++ DRM_INFO("iGVT-g active, disabling use of stolen memory\n"); ++ return 0; ++ } ++ + #ifdef CONFIG_INTEL_IOMMU + if (intel_iommu_gfx_mapped && INTEL_GEN(dev_priv) < 8) { + DRM_INFO("DMAR active, disabling use of stolen memory\n"); diff --git a/queue-4.10/drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch b/queue-4.10/drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch new file mode 100644 index 00000000000..a55595053d4 --- /dev/null +++ b/queue-4.10/drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch @@ -0,0 +1,57 @@ +From fc12bccda8b6f5c38139eceec9e369ed78091b2b Mon Sep 17 00:00:00 2001 +From: Fabio Estevam +Date: Wed, 8 Feb 2017 10:47:49 -0200 +Subject: drm/imx: imx-tve: Do not set the regulator voltage + +From: Fabio Estevam + +commit fc12bccda8b6f5c38139eceec9e369ed78091b2b upstream. + +Commit deb65870b5d9d ("drm/imx: imx-tve: check the value returned by +regulator_set_voltage()") exposes the following probe issue: + +63ff0000.tve supply dac not found, using dummy regulator +imx-drm display-subsystem: failed to bind 63ff0000.tve (ops imx_tve_ops): -22 + +When the 'dac-supply' is not passed in the device tree a dummy regulator is +used and setting its voltage is not allowed. + +To fix this issue, do not set the dac-supply voltage inside the driver +and let its voltage be specified in the device tree. + +Print a warning if the the 'dac-supply' voltage has a value different +from 2.75V. + +Fixes: deb65870b5d9d ("drm/imx: imx-tve: check the value returned by regulator_set_voltage()") +Suggested-by: Lucas Stach +Signed-off-by: Fabio Estevam +Signed-off-by: Philipp Zabel +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/imx/imx-tve.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/imx/imx-tve.c ++++ b/drivers/gpu/drm/imx/imx-tve.c +@@ -98,6 +98,8 @@ + /* TVE_TST_MODE_REG */ + #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) + ++#define IMX_TVE_DAC_VOLTAGE 2750000 ++ + enum { + TVE_MODE_TVOUT, + TVE_MODE_VGA, +@@ -621,9 +623,8 @@ static int imx_tve_bind(struct device *d + + tve->dac_reg = devm_regulator_get(dev, "dac"); + if (!IS_ERR(tve->dac_reg)) { +- ret = regulator_set_voltage(tve->dac_reg, 2750000, 2750000); +- if (ret) +- return ret; ++ if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE) ++ dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE); + ret = regulator_enable(tve->dac_reg); + if (ret) + return ret; diff --git a/queue-4.10/drm-radeon-handle-vfct-with-multiple-vbios-images.patch b/queue-4.10/drm-radeon-handle-vfct-with-multiple-vbios-images.patch new file mode 100644 index 00000000000..d5e7a8b952a --- /dev/null +++ b/queue-4.10/drm-radeon-handle-vfct-with-multiple-vbios-images.patch @@ -0,0 +1,112 @@ +From a882f5de402ded769af74fbf276132f9c175049c Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 25 Jan 2017 15:33:44 -0500 +Subject: drm/radeon: handle vfct with multiple vbios images + +From: Alex Deucher + +commit a882f5de402ded769af74fbf276132f9c175049c upstream. + +The vfct table can contain multiple vbios images if the +platform contains multiple GPUs. Noticed by netkas on +phoronix forums. This patch fixes those platforms. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_bios.c | 68 +++++++++++++++++++---------------- + 1 file changed, 37 insertions(+), 31 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_bios.c ++++ b/drivers/gpu/drm/radeon/radeon_bios.c +@@ -596,52 +596,58 @@ static bool radeon_read_disabled_bios(st + #ifdef CONFIG_ACPI + static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) + { +- bool ret = false; + struct acpi_table_header *hdr; + acpi_size tbl_size; + UEFI_ACPI_VFCT *vfct; +- GOP_VBIOS_CONTENT *vbios; +- VFCT_IMAGE_HEADER *vhdr; ++ unsigned offset; + + if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) + return false; + tbl_size = hdr->length; + if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { + DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); +- goto out_unmap; ++ return false; + } + + vfct = (UEFI_ACPI_VFCT *)hdr; +- if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { +- DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); +- goto out_unmap; +- } ++ offset = vfct->VBIOSImageOffset; + +- vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); +- vhdr = &vbios->VbiosHeader; +- DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", +- vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, +- vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); +- +- if (vhdr->PCIBus != rdev->pdev->bus->number || +- vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || +- vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || +- vhdr->VendorID != rdev->pdev->vendor || +- vhdr->DeviceID != rdev->pdev->device) { +- DRM_INFO("ACPI VFCT table is not for this card\n"); +- goto out_unmap; ++ while (offset < tbl_size) { ++ GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); ++ VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; ++ ++ offset += sizeof(VFCT_IMAGE_HEADER); ++ if (offset > tbl_size) { ++ DRM_ERROR("ACPI VFCT image header truncated\n"); ++ return false; ++ } ++ ++ offset += vhdr->ImageLength; ++ if (offset > tbl_size) { ++ DRM_ERROR("ACPI VFCT image truncated\n"); ++ return false; ++ } ++ ++ if (vhdr->ImageLength && ++ vhdr->PCIBus == rdev->pdev->bus->number && ++ vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && ++ vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && ++ vhdr->VendorID == rdev->pdev->vendor && ++ vhdr->DeviceID == rdev->pdev->device) { ++ rdev->bios = kmemdup(&vbios->VbiosContent, ++ vhdr->ImageLength, ++ GFP_KERNEL); ++ ++ if (!rdev->bios) { ++ kfree(rdev->bios); ++ return false; ++ } ++ return true; ++ } + } + +- if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { +- DRM_ERROR("ACPI VFCT image truncated\n"); +- goto out_unmap; +- } +- +- rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); +- ret = !!rdev->bios; +- +-out_unmap: +- return ret; ++ DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); ++ return false; + } + #else + static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) diff --git a/queue-4.10/drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch b/queue-4.10/drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch new file mode 100644 index 00000000000..780001f9e6b --- /dev/null +++ b/queue-4.10/drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch @@ -0,0 +1,51 @@ +From 239ac65fa5ffab71adf66e642750f940e7241d99 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Wed, 25 Jan 2017 17:21:31 +0900 +Subject: drm/ttm: Make sure BOs being swapped out are cacheable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 239ac65fa5ffab71adf66e642750f940e7241d99 upstream. + +The current caching state may not be tt_cached, even though the +placement contains TTM_PL_FLAG_CACHED, because placement can contain +multiple caching flags. Trying to swap out such a BO would trip up the + + BUG_ON(ttm->caching_state != tt_cached); + +in ttm_tt_swapout. + +Signed-off-by: Michel Dänzer +Reviewed-by: Thomas Hellstrom +Reviewed-by: Christian König . +Reviewed-by: Sinclair Yeh +Signed-off-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/ttm/ttm_bo.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/ttm/ttm_bo.c ++++ b/drivers/gpu/drm/ttm/ttm_bo.c +@@ -1670,7 +1670,6 @@ static int ttm_bo_swapout(struct ttm_mem + struct ttm_buffer_object *bo; + int ret = -EBUSY; + int put_count; +- uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM); + + spin_lock(&glob->lru_lock); + list_for_each_entry(bo, &glob->swap_lru, swap) { +@@ -1701,7 +1700,8 @@ static int ttm_bo_swapout(struct ttm_mem + * Move to system cached + */ + +- if ((bo->mem.placement & swap_placement) != swap_placement) { ++ if (bo->mem.mem_type != TTM_PL_SYSTEM || ++ bo->ttm->caching_state != tt_cached) { + struct ttm_mem_reg evict_mem; + + evict_mem = bo->mem; diff --git a/queue-4.10/drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch b/queue-4.10/drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch new file mode 100644 index 00000000000..30cf11517af --- /dev/null +++ b/queue-4.10/drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch @@ -0,0 +1,73 @@ +From 31788ca803a0c89078f9e604e64286fbd9077926 Mon Sep 17 00:00:00 2001 +From: Thomas Hellstrom +Date: Tue, 21 Feb 2017 17:42:27 +0700 +Subject: drm/vmwgfx: Work around drm removal of control nodes + +From: Thomas Hellstrom + +commit 31788ca803a0c89078f9e604e64286fbd9077926 upstream. + +vmware tools has a daemon that gets layout information from the GUI and +forwards it to DRM so that the modesetting code can set preferred connector +locations and modes. This daemon was using control nodes but since control +nodes were just removed, make it possible for the daemon to use render- or +primary nodes instead. This is a bit ugly but will allow drm to proceed with +removal of the mostly unused control-node code and allow vmware to proceed +with fixing up automatic layout settings for gnome-shell/wayland. + +We bump minor to inform user-space about the api change. + +Signed-off-by: Thomas Hellstrom +Reviewed-by: Sinclair Yeh +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/20170221104227.2854-1-thellstrom@vmware.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 11 ++++++++++- + drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 4 ++-- + 2 files changed, 12 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +@@ -199,9 +199,14 @@ static const struct drm_ioctl_desc vmw_i + VMW_IOCTL_DEF(VMW_PRESENT_READBACK, + vmw_present_readback_ioctl, + DRM_MASTER | DRM_AUTH), ++ /* ++ * The permissions of the below ioctl are overridden in ++ * vmw_generic_ioctl(). We require either ++ * DRM_MASTER or capable(CAP_SYS_ADMIN). ++ */ + VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, + vmw_kms_update_layout_ioctl, +- DRM_MASTER | DRM_CONTROL_ALLOW), ++ DRM_RENDER_ALLOW), + VMW_IOCTL_DEF(VMW_CREATE_SHADER, + vmw_shader_define_ioctl, + DRM_AUTH | DRM_RENDER_ALLOW), +@@ -1125,6 +1130,10 @@ static long vmw_generic_ioctl(struct fil + + return (long) vmw_execbuf_ioctl(dev, arg, file_priv, + _IOC_SIZE(cmd)); ++ } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { ++ if (!drm_is_current_master(file_priv) && ++ !capable(CAP_SYS_ADMIN)) ++ return -EACCES; + } + + if (unlikely(ioctl->cmd != cmd)) +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +@@ -41,9 +41,9 @@ + #include + #include "vmwgfx_fence.h" + +-#define VMWGFX_DRIVER_DATE "20160210" ++#define VMWGFX_DRIVER_DATE "20170221" + #define VMWGFX_DRIVER_MAJOR 2 +-#define VMWGFX_DRIVER_MINOR 11 ++#define VMWGFX_DRIVER_MINOR 12 + #define VMWGFX_DRIVER_PATCHLEVEL 0 + #define VMWGFX_FILE_PAGE_OFFSET 0x00100000 + #define VMWGFX_FIFO_STATIC_SIZE (1024*1024) diff --git a/queue-4.10/revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch b/queue-4.10/revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch new file mode 100644 index 00000000000..40513126ec8 --- /dev/null +++ b/queue-4.10/revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch @@ -0,0 +1,465 @@ +From jdelvare@suse.de Sun Mar 12 19:44:04 2017 +From: Jean Delvare +Date: Thu, 2 Mar 2017 18:21:35 +0100 +Subject: Revert "drm/amdgpu: update tile table for oland/hainan" +To: stable@vger.kernel.org +Cc: Flora Cui , Junwei Zhang , Alex Deucher +Message-ID: <20170302182135.3afe11e1@endymion> + +From: Jean Delvare + +Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for +oland/hainan") as it is causing ugly visual artifacts on at least +Oland. This is only an optimization so we can live without it. + +This fixes kernel bug #194761: +amdgpu driver breaks on Oland (SI) +https://bugzilla.kernel.org/show_bug.cgi?id=194761 + +Signed-off-by: Jean Delvare +Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") +Cc: Flora Cui +Cc: Junwei Zhang +Cc: Alex Deucher +Acked-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- +Note: This is for stable v4.10 branch only. v4.11 and later have a +different fix, but it's much larger and more intrusive so not suitable +for a stable branch. + + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 330 ++++++++++++++-------------------- + 1 file changed, 139 insertions(+), 191 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 1: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 2: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 3: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK) | +- TILE_SPLIT(split_equal_to_row_size)); ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 4: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_1D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2)); ++ gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | ++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 5: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(split_equal_to_row_size) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 6: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(split_equal_to_row_size) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 7: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(split_equal_to_row_size) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 8: +- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); ++ gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | ++ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | ++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 9: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | +- ARRAY_MODE(ARRAY_1D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2)); ++ gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | ++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 10: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 11: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 12: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 13: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_1D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2)); ++ gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | ++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 14: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 15: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 16: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 17: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK) | +- TILE_SPLIT(split_equal_to_row_size)); +- break; +- case 18: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_1D_TILED_THICK) | +- PIPE_CONFIG(ADDR_SURF_P2)); +- break; +- case 19: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P4_8x16) | ++ TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | +- TILE_SPLIT(split_equal_to_row_size)); +- break; +- case 20: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THICK) | +- PIPE_CONFIG(ADDR_SURF_P2) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | +- NUM_BANKS(ADDR_SURF_16_BANK) | +- TILE_SPLIT(split_equal_to_row_size)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 21: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 22: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ NUM_BANKS(ADDR_SURF_16_BANK) | ++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); + break; + case 23: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 24: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | ++ NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_8_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); + break; + case 25: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | ++ gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ++ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); +- break; +- case 26: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); +- break; +- case 27: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); +- break; +- case 28: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); +- break; +- case 29: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | +- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | +- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); +- break; +- case 30: +- gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | +- ARRAY_MODE(ARRAY_2D_TILED_THIN1) | +- PIPE_CONFIG(ADDR_SURF_P2) | +- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | ++ NUM_BANKS(ADDR_SURF_8_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | +- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | +- NUM_BANKS(ADDR_SURF_4_BANK)); ++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); + break; + default: +- continue; ++ gb_tile_moden = 0; ++ break; + } + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); diff --git a/queue-4.10/series b/queue-4.10/series index a189eb00ef3..4275a87955c 100644 --- a/queue-4.10/series +++ b/queue-4.10/series @@ -44,3 +44,19 @@ mac80211-flush-delayed-work-when-entering-suspend.patch mac80211-don-t-reorder-frames-with-sn-smaller-than-ssn.patch mac80211-don-t-handle-filtered-frames-within-a-ba-session.patch mac80211-use-driver-indicated-transmitter-sta-only-for-data-frames.patch +drm-amdgpu-add-more-cases-to-dce11-possible-crtc-mask-setup.patch +drm-amdgpu-pm-check-for-headless-before-calling-compute_clocks.patch +revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch +drm-ast-handle-configuration-without-p2a-bridge.patch +drm-ast-fix-test-for-vga-enabled.patch +drm-ast-call-open_key-before-enable_mmio-in-post-code.patch +drm-ast-fix-ast2400-post-failure-without-bmc-fw-or-vbios.patch +drm-radeon-handle-vfct-with-multiple-vbios-images.patch +drm-edid-add-edid_quirk_force_8bpc-quirk-for-rotel-rsx-1058.patch +drm-ttm-make-sure-bos-being-swapped-out-are-cacheable.patch +drm-vmwgfx-work-around-drm-removal-of-control-nodes.patch +drm-imx-imx-tve-do-not-set-the-regulator-voltage.patch +drm-atomic-fix-an-error-code-in-mode_fixup.patch +drm-i915-gvt-disable-access-to-stolen-memory-as-a-guest.patch +drm-cancel-drm_fb_helper_dirty_work-on-unload.patch +drm-cancel-drm_fb_helper_resume_work-on-unload.patch -- 2.47.3