From b8ba13856360d1cae00269a0ffe291cf573bb575 Mon Sep 17 00:00:00 2001 From: Sergey Belyashov Date: Tue, 3 Mar 2020 16:31:42 +0000 Subject: [PATCH] The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit. PR 25627 opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX instructions. gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of instruction LD IY,(HL). * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction. --- gas/ChangeLog | 10 ++++++++++ gas/config/tc-z80.c | 4 ++-- gas/testsuite/gas/z80/ez80_adl_all.d | 10 ++++++++++ gas/testsuite/gas/z80/ez80_adl_all.s | 12 +++++++++++- gas/testsuite/gas/z80/ez80_z80_all.d | 10 ++++++++++ gas/testsuite/gas/z80/ez80_z80_all.s | 12 +++++++++++- opcodes/ChangeLog | 6 ++++++ opcodes/z80-dis.c | 4 ++-- 8 files changed, 62 insertions(+), 6 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 835383c1259..9360e8d8774 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2020-03-03 Sergey Belyashov + + PR 25627 + * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of + instruction LD IY,(HL). + * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. + * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. + * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. + * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction. + 2020-03-03 H.J. Lu PR gas/25622 diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c index 312a0fc034d..713176f76bd 100644 --- a/gas/config/tc-z80.c +++ b/gas/config/tc-z80.c @@ -2601,8 +2601,8 @@ emit_ld_rr_m (expressionS *dst, expressionS *src) case REG_BC: opcode = 0x07; break; case REG_DE: opcode = 0x17; break; case REG_HL: opcode = 0x27; break; - case REG_IX: opcode = (!prefix || prefix == 0xDD) ? 0x37 : 0x31; break; - case REG_IY: opcode = prefix ? ((prefix == 0xDD) ? 0x31 : 0x37) : 0x36; break; + case REG_IX: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x37 : 0x31; break; + case REG_IY: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x31 : 0x37; break; default: ill_op (); } diff --git a/gas/testsuite/gas/z80/ez80_adl_all.d b/gas/testsuite/gas/z80/ez80_adl_all.d index 45793ac8037..1ed35d2849d 100644 --- a/gas/testsuite/gas/z80/ez80_adl_all.d +++ b/gas/testsuite/gas/z80/ez80_adl_all.d @@ -959,3 +959,13 @@ Disassembly of section .text: \s+7c1:\s+ab\s+xor a,e \s+7c2:\s+ac\s+xor a,h \s+7c3:\s+ad\s+xor a,l +\s+7c4:\s+ed 07\s+ld bc,\(hl\) +\s+7c6:\s+ed 17\s+ld de,\(hl\) +\s+7c8:\s+ed 27\s+ld hl,\(hl\) +\s+7ca:\s+ed 37\s+ld ix,\(hl\) +\s+7cc:\s+ed 31\s+ld iy,\(hl\) +\s+7ce:\s+ed 0f\s+ld \(hl\),bc +\s+7d0:\s+ed 1f\s+ld \(hl\),de +\s+7d2:\s+ed 2f\s+ld \(hl\),hl +\s+7d4:\s+ed 3f\s+ld \(hl\),ix +\s+7d6:\s+ed 3e\s+ld \(hl\),iy diff --git a/gas/testsuite/gas/z80/ez80_adl_all.s b/gas/testsuite/gas/z80/ez80_adl_all.s index 2a895b1ab89..041c10c94c3 100644 --- a/gas/testsuite/gas/z80/ez80_adl_all.s +++ b/gas/testsuite/gas/z80/ez80_adl_all.s @@ -480,7 +480,7 @@ ex (sp),hl ex (sp),ix ex (sp),iy - ex af,af' + ex af,af' ;' ex de,hl exx halt @@ -998,3 +998,13 @@ xor e xor h xor l + ld bc,(hl) + ld de,(hl) + ld hl,(hl) + ld ix,(hl) + ld iy,(hl) + ld (hl),bc + ld (hl),de + ld (hl),hl + ld (hl),ix + ld (hl),iy diff --git a/gas/testsuite/gas/z80/ez80_z80_all.d b/gas/testsuite/gas/z80/ez80_z80_all.d index ce69d251357..1f9a6f147fc 100644 --- a/gas/testsuite/gas/z80/ez80_z80_all.d +++ b/gas/testsuite/gas/z80/ez80_z80_all.d @@ -955,3 +955,13 @@ Disassembly of section .text: \s+793:\s+ab\s+xor a,e \s+794:\s+ac\s+xor a,h \s+795:\s+ad\s+xor a,l +\s+796:\s+ed 07\s+ld bc,\(hl\) +\s+798:\s+ed 17\s+ld de,\(hl\) +\s+79a:\s+ed 27\s+ld hl,\(hl\) +\s+79c:\s+ed 37\s+ld ix,\(hl\) +\s+79e:\s+ed 31\s+ld iy,\(hl\) +\s+7a0:\s+ed 0f\s+ld \(hl\),bc +\s+7a2:\s+ed 1f\s+ld \(hl\),de +\s+7a4:\s+ed 2f\s+ld \(hl\),hl +\s+7a6:\s+ed 3f\s+ld \(hl\),ix +\s+7a8:\s+ed 3e\s+ld \(hl\),iy diff --git a/gas/testsuite/gas/z80/ez80_z80_all.s b/gas/testsuite/gas/z80/ez80_z80_all.s index 76992c7634c..d2c6cdbeee4 100644 --- a/gas/testsuite/gas/z80/ez80_z80_all.s +++ b/gas/testsuite/gas/z80/ez80_z80_all.s @@ -474,7 +474,7 @@ ex (sp),hl ex (sp),ix ex (sp),iy - ex af,af' + ex af,af' ;' ex de,hl exx halt @@ -992,3 +992,13 @@ xor e xor h xor l + ld bc,(hl) + ld de,(hl) + ld hl,(hl) + ld ix,(hl) + ld iy,(hl) + ld (hl),bc + ld (hl),de + ld (hl),hl + ld (hl),ix + ld (hl),iy diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 03146c25db3..f471cd07f29 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2020-03-03 Sergey Belyashov + + PR 25627 + * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX + instructions. + 2020-03-03 H.J. Lu PR gas/25622 diff --git a/opcodes/z80-dis.c b/opcodes/z80-dis.c index 4762a626a8f..d66bd75657b 100644 --- a/opcodes/z80-dis.c +++ b/opcodes/z80-dis.c @@ -436,6 +436,7 @@ struct tab_elt opc_ed[] = { { 0x30, 0xFF, prt, "mul d,e", INSS_Z80N }, { 0x31, 0xFF, prt, "add hl,a", INSS_Z80N }, + { 0x31, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 }, { 0x30, 0xFE, dump, "xx", INSS_ALL }, /* do not move this line */ { 0x00, 0xC7, prt_r_n, "in0 %s,(0x%%02x)", INSS_Z180|INSS_EZ80 }, { 0x01, 0xC7, prt_r_n, "out0 (0x%%02x),%s", INSS_Z180|INSS_EZ80 }, @@ -446,6 +447,7 @@ struct tab_elt opc_ed[] = { 0x04, 0xC7, prt_r, "tst %s", INSS_Z180}, { 0x04, 0xC7, prt_r, "tst a,%s", INSS_EZ80 }, { 0x07, 0xFF, prt, "ld bc,(hl)", INSS_EZ80 }, + { 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 }, { 0x0F, 0xCF, prt_rr, "ld (hl),", INSS_EZ80 }, { 0x17, 0xFF, prt, "ld de,(hl)", INSS_EZ80 }, { 0x23, 0xFF, prt, "swapnib", INSS_Z80N }, @@ -462,10 +464,8 @@ struct tab_elt opc_ed[] = { 0x34, 0xFF, prt_nn, "add hl,0x%04x", INSS_Z80N }, { 0x35, 0xFF, prt_nn, "add de,0x%04x", INSS_Z80N }, { 0x36, 0xFF, prt_nn, "add bc,0x%04x", INSS_Z80N }, - { 0x36, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 }, { 0x37, 0xFF, prt, "ld ix,(hl)", INSS_EZ80 }, { 0x3E, 0xFF, prt, "ld (hl),iy", INSS_EZ80 }, - { 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 }, { 0x70, 0xFF, prt, "in f,(c)", INSS_Z80 | INSS_R800 | INSS_Z80N }, { 0x70, 0xFF, dump, "xx", INSS_ALL }, { 0x40, 0xC7, prt_r, "in %s,(bc)", INSS_EZ80 }, -- 2.39.5