From bf7929f6bc2c2e4c4d46a7cd32c69d866f29fb53 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 15 Oct 2024 13:20:36 +0200 Subject: [PATCH] drop clk imx6ul patches that broke the build --- ...ul-add-ethernet-refclock-mux-support.patch | 134 ------------------ ...lock-parent-for-imx6ul_clk_enetx_ref.patch | 47 ------ ...-imx6ul-fix-enet1-gate-configuration.patch | 88 ------------ ...mx6ul-fix-failed-to-get-parent-error.patch | 50 ------- ...n-early-uart-clocks-during-kernel-in.patch | 38 ----- queue-5.10/series | 5 - ...ul-add-ethernet-refclock-mux-support.patch | 134 ------------------ ...lock-parent-for-imx6ul_clk_enetx_ref.patch | 47 ------ ...-imx6ul-fix-enet1-gate-configuration.patch | 88 ------------ ...mx6ul-fix-failed-to-get-parent-error.patch | 50 ------- ...n-early-uart-clocks-during-kernel-in.patch | 38 ----- queue-5.15/series | 5 - ...ul-add-ethernet-refclock-mux-support.patch | 134 ------------------ ...lock-parent-for-imx6ul_clk_enetx_ref.patch | 47 ------ ...-imx6ul-fix-enet1-gate-configuration.patch | 88 ------------ ...mx6ul-fix-failed-to-get-parent-error.patch | 50 ------- ...n-early-uart-clocks-during-kernel-in.patch | 38 ----- queue-5.4/series | 5 - ...ul-add-ethernet-refclock-mux-support.patch | 134 ------------------ ...lock-parent-for-imx6ul_clk_enetx_ref.patch | 47 ------ ...-imx6ul-fix-enet1-gate-configuration.patch | 88 ------------ ...mx6ul-fix-failed-to-get-parent-error.patch | 50 ------- ...n-early-uart-clocks-during-kernel-in.patch | 38 ----- queue-6.1/series | 5 - 24 files changed, 1448 deletions(-) delete mode 100644 queue-5.10/clk-imx6ul-add-ethernet-refclock-mux-support.patch delete mode 100644 queue-5.10/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch delete mode 100644 queue-5.10/clk-imx6ul-fix-enet1-gate-configuration.patch delete mode 100644 queue-5.10/clk-imx6ul-fix-failed-to-get-parent-error.patch delete mode 100644 queue-5.10/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch delete mode 100644 queue-5.15/clk-imx6ul-add-ethernet-refclock-mux-support.patch delete mode 100644 queue-5.15/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch delete mode 100644 queue-5.15/clk-imx6ul-fix-enet1-gate-configuration.patch delete mode 100644 queue-5.15/clk-imx6ul-fix-failed-to-get-parent-error.patch delete mode 100644 queue-5.15/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch delete mode 100644 queue-5.4/clk-imx6ul-add-ethernet-refclock-mux-support.patch delete mode 100644 queue-5.4/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch delete mode 100644 queue-5.4/clk-imx6ul-fix-enet1-gate-configuration.patch delete mode 100644 queue-5.4/clk-imx6ul-fix-failed-to-get-parent-error.patch delete mode 100644 queue-5.4/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch delete mode 100644 queue-6.1/clk-imx6ul-add-ethernet-refclock-mux-support.patch delete mode 100644 queue-6.1/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch delete mode 100644 queue-6.1/clk-imx6ul-fix-enet1-gate-configuration.patch delete mode 100644 queue-6.1/clk-imx6ul-fix-failed-to-get-parent-error.patch delete mode 100644 queue-6.1/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch diff --git a/queue-5.10/clk-imx6ul-add-ethernet-refclock-mux-support.patch b/queue-5.10/clk-imx6ul-add-ethernet-refclock-mux-support.patch deleted file mode 100644 index 7be20de79d0..00000000000 --- a/queue-5.10/clk-imx6ul-add-ethernet-refclock-mux-support.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 69ec30417f9fdb1d78fac3407b59c9afa0ee6b6e Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:39 +0100 -Subject: clk: imx6ul: add ethernet refclock mux support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ] - -Add ethernet refclock mux support and set it to internal clock by -default. This configuration will not affect existing boards. - -clock tree before this patch: -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -after this patch: -fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... - `--<> enet1_ref_pad |- pll6_enet -fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... - `--<> enet2_ref_pad - -Signed-off-by: Oleksij Rempel -Acked-by: Lee Jones -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 26 +++++++++++++++++++++ - include/dt-bindings/clock/imx6ul-clock.h | 6 ++++- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +++-- - 3 files changed, 35 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 1205a1ee339dd..da9f2ca825644 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -94,6 +95,17 @@ static const struct clk_div_table video_div_table[] = { - { } - }; - -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET1_CLK_SEL }; -+static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET1_CLK_SEL; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET2_CLK_SEL }; -+static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET2_CLK_SEL; -+ - static u32 share_count_asrc; - static u32 share_count_audio; - static u32 share_count_sai1; -@@ -467,6 +479,17 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - /* mask handshake of mmdc */ - imx_mmdc_mask_handshake(base, 0); - -+ hws[IMX6UL_CLK_ENET1_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet1_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux("enet1_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), -+ enet1_ref_sels_table, enet1_ref_sels_table_mask); -+ hws[IMX6UL_CLK_ENET2_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet2_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux("enet2_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), -+ enet2_ref_sels_table, enet2_ref_sels_table_mask); -+ - imx_check_clk_hws(hws, IMX6UL_CLK_END); - - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); -@@ -511,6 +534,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk); - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); -+ -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index b44920f1edb0d..66239ebc0e233 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -257,7 +257,11 @@ - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 - #define IMX6UL_CLK_ENET1_REF_125M 250 -+#define IMX6UL_CLK_ENET1_REF_SEL 251 -+#define IMX6UL_CLK_ENET1_REF_PAD 252 -+#define IMX6UL_CLK_ENET2_REF_SEL 253 -+#define IMX6UL_CLK_ENET2_REF_PAD 254 - --#define IMX6UL_CLK_END 251 -+#define IMX6UL_CLK_END 255 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -index d4b5e527a7a3b..09c6b3184bb04 100644 ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -451,8 +451,10 @@ - #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) - - /* For imx6ul iomux gpr register field define */ --#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) --#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) -+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) -+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) -+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) -+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) - #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) - #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) - #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) --- -2.43.0 - diff --git a/queue-5.10/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch b/queue-5.10/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch deleted file mode 100644 index f5ada57cf02..00000000000 --- a/queue-5.10/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 37169e02cdc21e222cacc01847d79a12e4bb031f Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Sep 2024 09:05:53 +0000 -Subject: clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL - -From: Michel Alex - -[ Upstream commit 32c055ef563c3a4a73a477839f591b1b170bde8e ] - -Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add -ethernet refclock mux support") sets the internal clock as default -ethernet clock. - -Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, -the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct -parent and shall be used instead. -Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M -is the correct parent. - -Cc: stable@vger.kernel.org -Signed-off-by: Alex Michel -Reviewed-by: Oleksij Rempel -Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM -Signed-off-by: Abel Vesa -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index bdf98ef60ba0f..7beda28ed2f09 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -535,8 +535,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); - -- clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -- clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk); - - imx_register_uart_clocks(); - } --- -2.43.0 - diff --git a/queue-5.10/clk-imx6ul-fix-enet1-gate-configuration.patch b/queue-5.10/clk-imx6ul-fix-enet1-gate-configuration.patch deleted file mode 100644 index effefdd3872..00000000000 --- a/queue-5.10/clk-imx6ul-fix-enet1-gate-configuration.patch +++ /dev/null @@ -1,88 +0,0 @@ -From cf9dd99c7b32156c3f6e97d494d60bfa1722c6cc Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:38 +0100 -Subject: clk: imx6ul: fix enet1 gate configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 5f82bfced6118450cb9ea3f12316568f6fac10ab ] - -According to the "i.MX 6UltraLite Applications Processor Reference Manual, -Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root -of PLL6. It is controlling ENET1 separately. - -So, instead of this picture (implementation before this patch): -fec1 <- enet_ref (divider) <---------------------------, - |- pll6_enet (gate) -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -we should have this one (after this patch): -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -With this fix, the RMII reference clock will be turned off, after -setting network interface down on each separate interface -(ip l s dev eth0 down). Which was not working before, on system with both -FECs enabled. - -Signed-off-by: Oleksij Rempel -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 7 ++++--- - include/dt-bindings/clock/imx6ul-clock.h | 3 ++- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 206e4c43f68f8..1205a1ee339dd 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); - hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); - hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); -- hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); -+ hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1); - hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); - - /* -@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - -- hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, -+ hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, - base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, - base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - -- hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); -+ hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13); -+ hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); - hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); - hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); - -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index 79094338e6f1e..b44920f1edb0d 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -256,7 +256,8 @@ - #define IMX6UL_CLK_GPIO4 247 - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 -+#define IMX6UL_CLK_ENET1_REF_125M 250 - --#define IMX6UL_CLK_END 250 -+#define IMX6UL_CLK_END 251 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ --- -2.43.0 - diff --git a/queue-5.10/clk-imx6ul-fix-failed-to-get-parent-error.patch b/queue-5.10/clk-imx6ul-fix-failed-to-get-parent-error.patch deleted file mode 100644 index f6be7ee0001..00000000000 --- a/queue-5.10/clk-imx6ul-fix-failed-to-get-parent-error.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f420f47e56c67587d9bc8f94267327b6fb214c1d Mon Sep 17 00:00:00 2001 -From: Oleksij Rempel -Date: Fri, 10 Mar 2023 17:45:23 +0100 -Subject: clk: imx6ul: fix "failed to get parent" error - -From: Oleksij Rempel - -commit f420f47e56c67587d9bc8f94267327b6fb214c1d upstream. - -On some configuration we may get following error: -[ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) - -This happens if selector is configured to not supported value. To avoid -this warnings add dummy parents for not supported values. - -Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") -Signed-off-by: Oleksij Rempel -Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de -Tested-by: Stefan Wahren -Reported-by: Stefan Wahren -Reviewed-by: Peng Fan -Signed-off-by: Stephen Boyd -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/imx/clk-imx6ul.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -95,14 +95,16 @@ static const struct clk_div_table video_ - { } - }; - --static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", "dummy", "dummy"}; - static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -- IMX6UL_GPR1_ENET1_CLK_SEL }; -+ IMX6UL_GPR1_ENET1_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET1_TX_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL }; - static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | - IMX6UL_GPR1_ENET1_CLK_SEL; --static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", "dummy", "dummy"}; - static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -- IMX6UL_GPR1_ENET2_CLK_SEL }; -+ IMX6UL_GPR1_ENET2_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET2_TX_CLK_DIR | IMX6UL_GPR1_ENET2_CLK_SEL }; - static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | - IMX6UL_GPR1_ENET2_CLK_SEL; - diff --git a/queue-5.10/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch b/queue-5.10/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch deleted file mode 100644 index a41a6977acd..00000000000 --- a/queue-5.10/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 2195dbfd3dc056e2a9df152876de7c5d0b3aaf34 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 21 Apr 2023 13:55:17 +0200 -Subject: clk: imx6ul: retain early UART clocks during kernel init - -From: Alexander Stein - -[ Upstream commit 912d7af473f163ccdeb02aaabc3534177936b86c ] - -Make sure to keep UART clocks enabled during kernel init if -earlyprintk or earlycon are active. - -Signed-off-by: Alexander Stein -Reviewed-by: Peng Fan -Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com -Signed-off-by: Abel Vesa -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index da9f2ca825644..bdf98ef60ba0f 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -537,6 +537,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); - clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ -+ imx_register_uart_clocks(); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); --- -2.43.0 - diff --git a/queue-5.10/series b/queue-5.10/series index f3efbe90386..cfb95228599 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -426,10 +426,6 @@ uprobes-fix-kernel-info-leak-via-uprobes-vma.patch drm-rockchip-define-gamma-registers-for-rk3399.patch drm-rockchip-support-gamma-control-on-rk3399.patch drm-rockchip-vop-clear-dma-stop-bit-on-rk3066.patch -clk-imx6ul-fix-enet1-gate-configuration.patch -clk-imx6ul-add-ethernet-refclock-mux-support.patch -clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch -clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch clk-qcom-dispcc-sm8250-use-clk_set_rate_parent-for-b.patch r8169-fix-spelling-mistake-tx_underun-tx_underrun.patch r8169-add-tally-counter-fields-added-with-rtl8125.patch @@ -437,7 +433,6 @@ acpi-battery-simplify-battery-hook-locking.patch acpi-battery-fix-possible-crash-when-unregistering-a.patch ext4-fix-inode-tree-inconsistency-caused-by-enomem.patch vhost-scsi-null-ptr-dereference-in-vhost_scsi_get_req.patch -clk-imx6ul-fix-failed-to-get-parent-error.patch unicode-don-t-special-case-ignorable-code-points.patch net-ethernet-cortina-drop-tso-support.patch tracing-remove-precision-vsnprintf-check-from-print-.patch diff --git a/queue-5.15/clk-imx6ul-add-ethernet-refclock-mux-support.patch b/queue-5.15/clk-imx6ul-add-ethernet-refclock-mux-support.patch deleted file mode 100644 index e52d2e2be22..00000000000 --- a/queue-5.15/clk-imx6ul-add-ethernet-refclock-mux-support.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 35af8da03ae285e8e65144e22ff7e19639aa31b4 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:39 +0100 -Subject: clk: imx6ul: add ethernet refclock mux support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ] - -Add ethernet refclock mux support and set it to internal clock by -default. This configuration will not affect existing boards. - -clock tree before this patch: -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -after this patch: -fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... - `--<> enet1_ref_pad |- pll6_enet -fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... - `--<> enet2_ref_pad - -Signed-off-by: Oleksij Rempel -Acked-by: Lee Jones -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 26 +++++++++++++++++++++ - include/dt-bindings/clock/imx6ul-clock.h | 6 ++++- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +++-- - 3 files changed, 35 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 1205a1ee339dd..da9f2ca825644 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -94,6 +95,17 @@ static const struct clk_div_table video_div_table[] = { - { } - }; - -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET1_CLK_SEL }; -+static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET1_CLK_SEL; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET2_CLK_SEL }; -+static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET2_CLK_SEL; -+ - static u32 share_count_asrc; - static u32 share_count_audio; - static u32 share_count_sai1; -@@ -467,6 +479,17 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - /* mask handshake of mmdc */ - imx_mmdc_mask_handshake(base, 0); - -+ hws[IMX6UL_CLK_ENET1_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet1_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux("enet1_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), -+ enet1_ref_sels_table, enet1_ref_sels_table_mask); -+ hws[IMX6UL_CLK_ENET2_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet2_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux("enet2_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), -+ enet2_ref_sels_table, enet2_ref_sels_table_mask); -+ - imx_check_clk_hws(hws, IMX6UL_CLK_END); - - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); -@@ -511,6 +534,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk); - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); -+ -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index b44920f1edb0d..66239ebc0e233 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -257,7 +257,11 @@ - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 - #define IMX6UL_CLK_ENET1_REF_125M 250 -+#define IMX6UL_CLK_ENET1_REF_SEL 251 -+#define IMX6UL_CLK_ENET1_REF_PAD 252 -+#define IMX6UL_CLK_ENET2_REF_SEL 253 -+#define IMX6UL_CLK_ENET2_REF_PAD 254 - --#define IMX6UL_CLK_END 251 -+#define IMX6UL_CLK_END 255 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -index d4b5e527a7a3b..09c6b3184bb04 100644 ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -451,8 +451,10 @@ - #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) - - /* For imx6ul iomux gpr register field define */ --#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) --#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) -+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) -+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) -+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) -+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) - #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) - #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) - #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) --- -2.43.0 - diff --git a/queue-5.15/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch b/queue-5.15/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch deleted file mode 100644 index 0e346f26ad2..00000000000 --- a/queue-5.15/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 7ca1a28556796205fcdcb1e2f340090358a0a963 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Sep 2024 09:05:53 +0000 -Subject: clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL - -From: Michel Alex - -[ Upstream commit 32c055ef563c3a4a73a477839f591b1b170bde8e ] - -Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add -ethernet refclock mux support") sets the internal clock as default -ethernet clock. - -Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, -the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct -parent and shall be used instead. -Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M -is the correct parent. - -Cc: stable@vger.kernel.org -Signed-off-by: Alex Michel -Reviewed-by: Oleksij Rempel -Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM -Signed-off-by: Abel Vesa -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index bdf98ef60ba0f..7beda28ed2f09 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -535,8 +535,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); - -- clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -- clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk); - - imx_register_uart_clocks(); - } --- -2.43.0 - diff --git a/queue-5.15/clk-imx6ul-fix-enet1-gate-configuration.patch b/queue-5.15/clk-imx6ul-fix-enet1-gate-configuration.patch deleted file mode 100644 index 2f4b1bd2b68..00000000000 --- a/queue-5.15/clk-imx6ul-fix-enet1-gate-configuration.patch +++ /dev/null @@ -1,88 +0,0 @@ -From cee8d48e428abb41b5e7efa8c5ed9af5788e5031 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:38 +0100 -Subject: clk: imx6ul: fix enet1 gate configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 5f82bfced6118450cb9ea3f12316568f6fac10ab ] - -According to the "i.MX 6UltraLite Applications Processor Reference Manual, -Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root -of PLL6. It is controlling ENET1 separately. - -So, instead of this picture (implementation before this patch): -fec1 <- enet_ref (divider) <---------------------------, - |- pll6_enet (gate) -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -we should have this one (after this patch): -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -With this fix, the RMII reference clock will be turned off, after -setting network interface down on each separate interface -(ip l s dev eth0 down). Which was not working before, on system with both -FECs enabled. - -Signed-off-by: Oleksij Rempel -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 7 ++++--- - include/dt-bindings/clock/imx6ul-clock.h | 3 ++- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 206e4c43f68f8..1205a1ee339dd 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); - hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); - hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); -- hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); -+ hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1); - hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); - - /* -@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - -- hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, -+ hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, - base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, - base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - -- hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); -+ hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13); -+ hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); - hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); - hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); - -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index 79094338e6f1e..b44920f1edb0d 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -256,7 +256,8 @@ - #define IMX6UL_CLK_GPIO4 247 - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 -+#define IMX6UL_CLK_ENET1_REF_125M 250 - --#define IMX6UL_CLK_END 250 -+#define IMX6UL_CLK_END 251 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ --- -2.43.0 - diff --git a/queue-5.15/clk-imx6ul-fix-failed-to-get-parent-error.patch b/queue-5.15/clk-imx6ul-fix-failed-to-get-parent-error.patch deleted file mode 100644 index f6be7ee0001..00000000000 --- a/queue-5.15/clk-imx6ul-fix-failed-to-get-parent-error.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f420f47e56c67587d9bc8f94267327b6fb214c1d Mon Sep 17 00:00:00 2001 -From: Oleksij Rempel -Date: Fri, 10 Mar 2023 17:45:23 +0100 -Subject: clk: imx6ul: fix "failed to get parent" error - -From: Oleksij Rempel - -commit f420f47e56c67587d9bc8f94267327b6fb214c1d upstream. - -On some configuration we may get following error: -[ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) - -This happens if selector is configured to not supported value. To avoid -this warnings add dummy parents for not supported values. - -Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") -Signed-off-by: Oleksij Rempel -Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de -Tested-by: Stefan Wahren -Reported-by: Stefan Wahren -Reviewed-by: Peng Fan -Signed-off-by: Stephen Boyd -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/imx/clk-imx6ul.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -95,14 +95,16 @@ static const struct clk_div_table video_ - { } - }; - --static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", "dummy", "dummy"}; - static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -- IMX6UL_GPR1_ENET1_CLK_SEL }; -+ IMX6UL_GPR1_ENET1_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET1_TX_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL }; - static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | - IMX6UL_GPR1_ENET1_CLK_SEL; --static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", "dummy", "dummy"}; - static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -- IMX6UL_GPR1_ENET2_CLK_SEL }; -+ IMX6UL_GPR1_ENET2_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET2_TX_CLK_DIR | IMX6UL_GPR1_ENET2_CLK_SEL }; - static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | - IMX6UL_GPR1_ENET2_CLK_SEL; - diff --git a/queue-5.15/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch b/queue-5.15/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch deleted file mode 100644 index 767501650d1..00000000000 --- a/queue-5.15/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 483f17cbf43e3465b2426fc9364a5d99327aaa01 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 21 Apr 2023 13:55:17 +0200 -Subject: clk: imx6ul: retain early UART clocks during kernel init - -From: Alexander Stein - -[ Upstream commit 912d7af473f163ccdeb02aaabc3534177936b86c ] - -Make sure to keep UART clocks enabled during kernel init if -earlyprintk or earlycon are active. - -Signed-off-by: Alexander Stein -Reviewed-by: Peng Fan -Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com -Signed-off-by: Abel Vesa -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index da9f2ca825644..bdf98ef60ba0f 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -537,6 +537,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); - clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ -+ imx_register_uart_clocks(); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); --- -2.43.0 - diff --git a/queue-5.15/series b/queue-5.15/series index 87e150d4994..a51d237346d 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -567,10 +567,6 @@ lib-buildid-harden-build-id-parsing-logic.patch drm-rockchip-define-gamma-registers-for-rk3399.patch drm-rockchip-support-gamma-control-on-rk3399.patch drm-rockchip-vop-clear-dma-stop-bit-on-rk3066.patch -clk-imx6ul-fix-enet1-gate-configuration.patch -clk-imx6ul-add-ethernet-refclock-mux-support.patch -clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch -clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch media-i2c-imx335-enable-regulator-supplies.patch media-imx335-fix-reset-gpio-handling.patch dt-bindings-clock-qcom-add-missing-ufs-qref-clocks.patch @@ -585,7 +581,6 @@ ext4-fix-inode-tree-inconsistency-caused-by-enomem.patch 9p-add-missing-locking-around-taking-dentry-fid-list.patch vhost-scsi-null-ptr-dereference-in-vhost_scsi_get_req.patch perf-report-fix-segfault-when-sym-sort-key-is-not-used.patch -clk-imx6ul-fix-failed-to-get-parent-error.patch alsa-usb-audio-fix-possible-null-pointer-dereference-in-snd_usb_pcm_has_fixed_rate.patch unicode-don-t-special-case-ignorable-code-points.patch net-ethernet-cortina-drop-tso-support.patch diff --git a/queue-5.4/clk-imx6ul-add-ethernet-refclock-mux-support.patch b/queue-5.4/clk-imx6ul-add-ethernet-refclock-mux-support.patch deleted file mode 100644 index 08b2ecf48e4..00000000000 --- a/queue-5.4/clk-imx6ul-add-ethernet-refclock-mux-support.patch +++ /dev/null @@ -1,134 +0,0 @@ -From f0dd30eeb8614d9986db933a46344c0cf5474d58 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:39 +0100 -Subject: clk: imx6ul: add ethernet refclock mux support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ] - -Add ethernet refclock mux support and set it to internal clock by -default. This configuration will not affect existing boards. - -clock tree before this patch: -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -after this patch: -fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... - `--<> enet1_ref_pad |- pll6_enet -fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... - `--<> enet2_ref_pad - -Signed-off-by: Oleksij Rempel -Acked-by: Lee Jones -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 26 +++++++++++++++++++++ - include/dt-bindings/clock/imx6ul-clock.h | 6 ++++- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +++-- - 3 files changed, 35 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 7a8dc0dc9d153..ae120b51544ea 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -94,6 +95,17 @@ static const struct clk_div_table video_div_table[] = { - { } - }; - -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET1_CLK_SEL }; -+static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET1_CLK_SEL; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET2_CLK_SEL }; -+static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET2_CLK_SEL; -+ - static u32 share_count_asrc; - static u32 share_count_audio; - static u32 share_count_sai1; -@@ -467,6 +479,17 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - /* mask handshake of mmdc */ - imx_mmdc_mask_handshake(base, 0); - -+ hws[IMX6UL_CLK_ENET1_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet1_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux("enet1_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), -+ enet1_ref_sels_table, enet1_ref_sels_table_mask); -+ hws[IMX6UL_CLK_ENET2_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet2_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux("enet2_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), -+ enet2_ref_sels_table, enet2_ref_sels_table_mask); -+ - imx_check_clk_hws(hws, IMX6UL_CLK_END); - - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); -@@ -511,6 +534,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk); - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); -+ -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index b44920f1edb0d..66239ebc0e233 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -257,7 +257,11 @@ - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 - #define IMX6UL_CLK_ENET1_REF_125M 250 -+#define IMX6UL_CLK_ENET1_REF_SEL 251 -+#define IMX6UL_CLK_ENET1_REF_PAD 252 -+#define IMX6UL_CLK_ENET2_REF_SEL 253 -+#define IMX6UL_CLK_ENET2_REF_PAD 254 - --#define IMX6UL_CLK_END 251 -+#define IMX6UL_CLK_END 255 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -index d4b5e527a7a3b..09c6b3184bb04 100644 ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -451,8 +451,10 @@ - #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) - - /* For imx6ul iomux gpr register field define */ --#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) --#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) -+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) -+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) -+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) -+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) - #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) - #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) - #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) --- -2.43.0 - diff --git a/queue-5.4/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch b/queue-5.4/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch deleted file mode 100644 index e145c9c433a..00000000000 --- a/queue-5.4/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 1c0b91af1e0a7ea541d7a3b523122f76f2bb51b9 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Sep 2024 09:05:53 +0000 -Subject: clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL - -From: Michel Alex - -[ Upstream commit 32c055ef563c3a4a73a477839f591b1b170bde8e ] - -Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add -ethernet refclock mux support") sets the internal clock as default -ethernet clock. - -Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, -the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct -parent and shall be used instead. -Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M -is the correct parent. - -Cc: stable@vger.kernel.org -Signed-off-by: Alex Michel -Reviewed-by: Oleksij Rempel -Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM -Signed-off-by: Abel Vesa -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 3895242235059..2ea0f00e3f796 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -535,8 +535,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); - -- clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -- clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk); - - imx_register_uart_clocks(); - } --- -2.43.0 - diff --git a/queue-5.4/clk-imx6ul-fix-enet1-gate-configuration.patch b/queue-5.4/clk-imx6ul-fix-enet1-gate-configuration.patch deleted file mode 100644 index 5cfa0177346..00000000000 --- a/queue-5.4/clk-imx6ul-fix-enet1-gate-configuration.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 19b552a1bb494a802044dd82d38ad865b66913fb Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:38 +0100 -Subject: clk: imx6ul: fix enet1 gate configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 5f82bfced6118450cb9ea3f12316568f6fac10ab ] - -According to the "i.MX 6UltraLite Applications Processor Reference Manual, -Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root -of PLL6. It is controlling ENET1 separately. - -So, instead of this picture (implementation before this patch): -fec1 <- enet_ref (divider) <---------------------------, - |- pll6_enet (gate) -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -we should have this one (after this patch): -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -With this fix, the RMII reference clock will be turned off, after -setting network interface down on each separate interface -(ip l s dev eth0 down). Which was not working before, on system with both -FECs enabled. - -Signed-off-by: Oleksij Rempel -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 7 ++++--- - include/dt-bindings/clock/imx6ul-clock.h | 3 ++- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index f3ac5a524f4ed..7a8dc0dc9d153 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); - hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); - hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); -- hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); -+ hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1); - hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); - - /* -@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - -- hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, -+ hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, - base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, - base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - -- hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); -+ hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13); -+ hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); - hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); - hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); - -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index 79094338e6f1e..b44920f1edb0d 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -256,7 +256,8 @@ - #define IMX6UL_CLK_GPIO4 247 - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 -+#define IMX6UL_CLK_ENET1_REF_125M 250 - --#define IMX6UL_CLK_END 250 -+#define IMX6UL_CLK_END 251 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ --- -2.43.0 - diff --git a/queue-5.4/clk-imx6ul-fix-failed-to-get-parent-error.patch b/queue-5.4/clk-imx6ul-fix-failed-to-get-parent-error.patch deleted file mode 100644 index f6be7ee0001..00000000000 --- a/queue-5.4/clk-imx6ul-fix-failed-to-get-parent-error.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f420f47e56c67587d9bc8f94267327b6fb214c1d Mon Sep 17 00:00:00 2001 -From: Oleksij Rempel -Date: Fri, 10 Mar 2023 17:45:23 +0100 -Subject: clk: imx6ul: fix "failed to get parent" error - -From: Oleksij Rempel - -commit f420f47e56c67587d9bc8f94267327b6fb214c1d upstream. - -On some configuration we may get following error: -[ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) - -This happens if selector is configured to not supported value. To avoid -this warnings add dummy parents for not supported values. - -Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") -Signed-off-by: Oleksij Rempel -Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de -Tested-by: Stefan Wahren -Reported-by: Stefan Wahren -Reviewed-by: Peng Fan -Signed-off-by: Stephen Boyd -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/imx/clk-imx6ul.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -95,14 +95,16 @@ static const struct clk_div_table video_ - { } - }; - --static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", "dummy", "dummy"}; - static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -- IMX6UL_GPR1_ENET1_CLK_SEL }; -+ IMX6UL_GPR1_ENET1_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET1_TX_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL }; - static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | - IMX6UL_GPR1_ENET1_CLK_SEL; --static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", "dummy", "dummy"}; - static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -- IMX6UL_GPR1_ENET2_CLK_SEL }; -+ IMX6UL_GPR1_ENET2_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET2_TX_CLK_DIR | IMX6UL_GPR1_ENET2_CLK_SEL }; - static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | - IMX6UL_GPR1_ENET2_CLK_SEL; - diff --git a/queue-5.4/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch b/queue-5.4/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch deleted file mode 100644 index 6f6c7571c6d..00000000000 --- a/queue-5.4/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch +++ /dev/null @@ -1,38 +0,0 @@ -From efe531035551263c92945a6f09e8638042556261 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 21 Apr 2023 13:55:17 +0200 -Subject: clk: imx6ul: retain early UART clocks during kernel init - -From: Alexander Stein - -[ Upstream commit 912d7af473f163ccdeb02aaabc3534177936b86c ] - -Make sure to keep UART clocks enabled during kernel init if -earlyprintk or earlycon are active. - -Signed-off-by: Alexander Stein -Reviewed-by: Peng Fan -Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com -Signed-off-by: Abel Vesa -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index ae120b51544ea..3895242235059 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -537,6 +537,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); - clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ -+ imx_register_uart_clocks(); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); --- -2.43.0 - diff --git a/queue-5.4/series b/queue-5.4/series index ffed111a588..890d4862d06 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -286,10 +286,6 @@ arm64-errata-expand-speculative-ssbs-workaround-once.patch uprobes-fix-kernel-info-leak-via-uprobes-vma.patch nfsd-use-ktime_get_seconds-for-timestamps.patch nfsd-fix-delegation_blocked-to-block-correctly-for-a.patch -clk-imx6ul-fix-enet1-gate-configuration.patch -clk-imx6ul-add-ethernet-refclock-mux-support.patch -clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch -clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch clk-qcom-rpmh-simplify-clk_rpmh_bcm_send_cmd.patch clk-qcom-clk-rpmh-fix-overflow-in-bcm-vote.patch r8169-fix-spelling-mistake-tx_underun-tx_underrun.patch @@ -297,7 +293,6 @@ r8169-add-tally-counter-fields-added-with-rtl8125.patch acpi-battery-simplify-battery-hook-locking.patch acpi-battery-fix-possible-crash-when-unregistering-a.patch ext4-fix-inode-tree-inconsistency-caused-by-enomem.patch -clk-imx6ul-fix-failed-to-get-parent-error.patch unicode-don-t-special-case-ignorable-code-points.patch net-ethernet-cortina-drop-tso-support.patch tracing-remove-precision-vsnprintf-check-from-print-.patch diff --git a/queue-6.1/clk-imx6ul-add-ethernet-refclock-mux-support.patch b/queue-6.1/clk-imx6ul-add-ethernet-refclock-mux-support.patch deleted file mode 100644 index fbd0d4bdf8f..00000000000 --- a/queue-6.1/clk-imx6ul-add-ethernet-refclock-mux-support.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 0ad5a55ed36d39ce5f35ed3deadfdf440a3445bb Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:39 +0100 -Subject: clk: imx6ul: add ethernet refclock mux support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ] - -Add ethernet refclock mux support and set it to internal clock by -default. This configuration will not affect existing boards. - -clock tree before this patch: -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -after this patch: -fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... - `--<> enet1_ref_pad |- pll6_enet -fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... - `--<> enet2_ref_pad - -Signed-off-by: Oleksij Rempel -Acked-by: Lee Jones -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 26 +++++++++++++++++++++ - include/dt-bindings/clock/imx6ul-clock.h | 6 ++++- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +++-- - 3 files changed, 35 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 777c4d2b87b3f..3e802befa2d4d 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -94,6 +95,17 @@ static const struct clk_div_table video_div_table[] = { - { } - }; - -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET1_CLK_SEL }; -+static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET1_CLK_SEL; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -+ IMX6UL_GPR1_ENET2_CLK_SEL }; -+static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | -+ IMX6UL_GPR1_ENET2_CLK_SEL; -+ - static u32 share_count_asrc; - static u32 share_count_audio; - static u32 share_count_sai1; -@@ -472,6 +484,17 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - /* mask handshake of mmdc */ - imx_mmdc_mask_handshake(base, 0); - -+ hws[IMX6UL_CLK_ENET1_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet1_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux("enet1_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), -+ enet1_ref_sels_table, enet1_ref_sels_table_mask); -+ hws[IMX6UL_CLK_ENET2_REF_PAD] = imx_obtain_fixed_of_clock(ccm_node, "enet2_ref_pad", 0); -+ -+ hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux("enet2_ref_sel", "fsl,imx6ul-iomuxc-gpr", -+ IOMUXC_GPR1, enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), -+ enet2_ref_sels_table, enet2_ref_sels_table_mask); -+ - imx_check_clk_hws(hws, IMX6UL_CLK_END); - - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); -@@ -516,6 +539,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk); - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); -+ -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index b44920f1edb0d..66239ebc0e233 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -257,7 +257,11 @@ - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 - #define IMX6UL_CLK_ENET1_REF_125M 250 -+#define IMX6UL_CLK_ENET1_REF_SEL 251 -+#define IMX6UL_CLK_ENET1_REF_PAD 252 -+#define IMX6UL_CLK_ENET2_REF_SEL 253 -+#define IMX6UL_CLK_ENET2_REF_PAD 254 - --#define IMX6UL_CLK_END 251 -+#define IMX6UL_CLK_END 255 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -index d4b5e527a7a3b..09c6b3184bb04 100644 ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -451,8 +451,10 @@ - #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) - - /* For imx6ul iomux gpr register field define */ --#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) --#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) -+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) -+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) -+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) -+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) - #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) - #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) - #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) --- -2.43.0 - diff --git a/queue-6.1/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch b/queue-6.1/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch deleted file mode 100644 index f685cc8d05e..00000000000 --- a/queue-6.1/clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2658da8276610b018cf43d1315317d5d440900aa Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Sep 2024 09:05:53 +0000 -Subject: clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL - -From: Michel Alex - -[ Upstream commit 32c055ef563c3a4a73a477839f591b1b170bde8e ] - -Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add -ethernet refclock mux support") sets the internal clock as default -ethernet clock. - -Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, -the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct -parent and shall be used instead. -Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M -is the correct parent. - -Cc: stable@vger.kernel.org -Signed-off-by: Alex Michel -Reviewed-by: Oleksij Rempel -Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM -Signed-off-by: Abel Vesa -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index ef6c94b732684..c4266d732f7c1 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -540,8 +540,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk); - -- clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); -- clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk); -+ clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk); - - imx_register_uart_clocks(); - } --- -2.43.0 - diff --git a/queue-6.1/clk-imx6ul-fix-enet1-gate-configuration.patch b/queue-6.1/clk-imx6ul-fix-enet1-gate-configuration.patch deleted file mode 100644 index 450c532fb6b..00000000000 --- a/queue-6.1/clk-imx6ul-fix-enet1-gate-configuration.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f35990348b9d51cb91121e2cb2220d0eb804e010 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 31 Jan 2023 09:46:38 +0100 -Subject: clk: imx6ul: fix enet1 gate configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Oleksij Rempel - -[ Upstream commit 5f82bfced6118450cb9ea3f12316568f6fac10ab ] - -According to the "i.MX 6UltraLite Applications Processor Reference Manual, -Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root -of PLL6. It is controlling ENET1 separately. - -So, instead of this picture (implementation before this patch): -fec1 <- enet_ref (divider) <---------------------------, - |- pll6_enet (gate) -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -we should have this one (after this patch): -fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, - |- pll6_enet -fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ - -With this fix, the RMII reference clock will be turned off, after -setting network interface down on each separate interface -(ip l s dev eth0 down). Which was not working before, on system with both -FECs enabled. - -Signed-off-by: Oleksij Rempel -Reviewed-by: Abel Vesa -Signed-off-by: Abel Vesa -Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 7 ++++--- - include/dt-bindings/clock/imx6ul-clock.h | 3 ++- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 520b100bff4bb..777c4d2b87b3f 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); - hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); - hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); -- hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); -+ hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1); - hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); - - /* -@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - -- hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, -+ hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, - base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, - base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - -- hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); -+ hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13); -+ hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); - hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); - hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); - -diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h -index 79094338e6f1e..b44920f1edb0d 100644 ---- a/include/dt-bindings/clock/imx6ul-clock.h -+++ b/include/dt-bindings/clock/imx6ul-clock.h -@@ -256,7 +256,8 @@ - #define IMX6UL_CLK_GPIO4 247 - #define IMX6UL_CLK_GPIO5 248 - #define IMX6UL_CLK_MMDC_P1_IPG 249 -+#define IMX6UL_CLK_ENET1_REF_125M 250 - --#define IMX6UL_CLK_END 250 -+#define IMX6UL_CLK_END 251 - - #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ --- -2.43.0 - diff --git a/queue-6.1/clk-imx6ul-fix-failed-to-get-parent-error.patch b/queue-6.1/clk-imx6ul-fix-failed-to-get-parent-error.patch deleted file mode 100644 index f6be7ee0001..00000000000 --- a/queue-6.1/clk-imx6ul-fix-failed-to-get-parent-error.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f420f47e56c67587d9bc8f94267327b6fb214c1d Mon Sep 17 00:00:00 2001 -From: Oleksij Rempel -Date: Fri, 10 Mar 2023 17:45:23 +0100 -Subject: clk: imx6ul: fix "failed to get parent" error - -From: Oleksij Rempel - -commit f420f47e56c67587d9bc8f94267327b6fb214c1d upstream. - -On some configuration we may get following error: -[ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) - -This happens if selector is configured to not supported value. To avoid -this warnings add dummy parents for not supported values. - -Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") -Signed-off-by: Oleksij Rempel -Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de -Tested-by: Stefan Wahren -Reported-by: Stefan Wahren -Reviewed-by: Peng Fan -Signed-off-by: Stephen Boyd -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/imx/clk-imx6ul.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -95,14 +95,16 @@ static const struct clk_div_table video_ - { } - }; - --static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", }; -+static const char * enet1_ref_sels[] = { "enet1_ref_125m", "enet1_ref_pad", "dummy", "dummy"}; - static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, -- IMX6UL_GPR1_ENET1_CLK_SEL }; -+ IMX6UL_GPR1_ENET1_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET1_TX_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL }; - static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | - IMX6UL_GPR1_ENET1_CLK_SEL; --static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", }; -+static const char * enet2_ref_sels[] = { "enet2_ref_125m", "enet2_ref_pad", "dummy", "dummy"}; - static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, -- IMX6UL_GPR1_ENET2_CLK_SEL }; -+ IMX6UL_GPR1_ENET2_CLK_SEL, 0, -+ IMX6UL_GPR1_ENET2_TX_CLK_DIR | IMX6UL_GPR1_ENET2_CLK_SEL }; - static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | - IMX6UL_GPR1_ENET2_CLK_SEL; - diff --git a/queue-6.1/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch b/queue-6.1/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch deleted file mode 100644 index 9b16887a37b..00000000000 --- a/queue-6.1/clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch +++ /dev/null @@ -1,38 +0,0 @@ -From cb9fb9964fe8b890c863dbdfb0c3b559977de75b Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 21 Apr 2023 13:55:17 +0200 -Subject: clk: imx6ul: retain early UART clocks during kernel init - -From: Alexander Stein - -[ Upstream commit 912d7af473f163ccdeb02aaabc3534177936b86c ] - -Make sure to keep UART clocks enabled during kernel init if -earlyprintk or earlycon are active. - -Signed-off-by: Alexander Stein -Reviewed-by: Peng Fan -Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com -Signed-off-by: Abel Vesa -Stable-dep-of: 32c055ef563c ("clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL") -Signed-off-by: Sasha Levin ---- - drivers/clk/imx/clk-imx6ul.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c -index 3e802befa2d4d..ef6c94b732684 100644 ---- a/drivers/clk/imx/clk-imx6ul.c -+++ b/drivers/clk/imx/clk-imx6ul.c -@@ -542,6 +542,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) - - clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); - clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk); -+ -+ imx_register_uart_clocks(); - } - - CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); --- -2.43.0 - diff --git a/queue-6.1/series b/queue-6.1/series index e6c7a8411a4..b1dbe63bcb3 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -633,10 +633,6 @@ lib-buildid-harden-build-id-parsing-logic.patch docs-zh_cn-update-the-translation-of-delay-accountin.patch delayacct-improve-the-average-delay-precision-of-get.patch sched-psi-fix-bogus-pressure-spikes-from-aggregation.patch -clk-imx6ul-fix-enet1-gate-configuration.patch -clk-imx6ul-add-ethernet-refclock-mux-support.patch -clk-imx6ul-retain-early-uart-clocks-during-kernel-in.patch -clk-imx6ul-fix-clock-parent-for-imx6ul_clk_enetx_ref.patch media-i2c-imx335-enable-regulator-supplies.patch media-imx335-fix-reset-gpio-handling.patch remoteproc-k3-r5-acquire-mailbox-handle-during-probe.patch @@ -659,7 +655,6 @@ erofs-fix-incorrect-symlink-detection-in-fast-symlink.patch vhost-scsi-null-ptr-dereference-in-vhost_scsi_get_req.patch perf-report-fix-segfault-when-sym-sort-key-is-not-used.patch fsdax-dax_unshare_iter-should-return-a-valid-length.patch -clk-imx6ul-fix-failed-to-get-parent-error.patch fsdax-unshare-zero-destination-if-srcmap-is-hole-or-unwritten.patch unicode-don-t-special-case-ignorable-code-points.patch net-ethernet-cortina-drop-tso-support.patch -- 2.47.3