From c1380adf2e8680a00dedaf1b25c19beadbbe5bbd Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Mon, 3 Jun 2024 18:04:33 +0800 Subject: [PATCH] clk: meson: s4: fix fixed_pll_dco clock The fixed_pll_dco output frequency is not accurate, add frac factor for fixed_pll_dco clk to fix it. Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller") Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/s4-pll.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index d2650d96400cf..707c107a52918 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = { .shift = 0, .width = 8, }, + .frac = { + .reg_off = ANACTRL_FIXPLL_CTRL1, + .shift = 0, + .width = 17, + }, .n = { .reg_off = ANACTRL_FIXPLL_CTRL0, .shift = 10, -- 2.39.5