From c4bcc90ee52bf594e67cebc41511989bbc5724f1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 7 Jul 2020 16:12:15 +0200 Subject: [PATCH] 5.4-stable patches added patches: dm-zoned-assign-max_io_len-correctly.patch efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch --- ...dm-zoned-assign-max_io_len-correctly.patch | 35 ++++++ ...ible-to-disable-efivar_ssdt-entirely.patch | 58 ++++++++++ queue-5.4/series | 3 + ...mory-bandwidth-counter-width-for-amd.patch | 106 ++++++++++++++++++ 4 files changed, 202 insertions(+) create mode 100644 queue-5.4/dm-zoned-assign-max_io_len-correctly.patch create mode 100644 queue-5.4/efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch create mode 100644 queue-5.4/x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch diff --git a/queue-5.4/dm-zoned-assign-max_io_len-correctly.patch b/queue-5.4/dm-zoned-assign-max_io_len-correctly.patch new file mode 100644 index 00000000000..9618bebdf9e --- /dev/null +++ b/queue-5.4/dm-zoned-assign-max_io_len-correctly.patch @@ -0,0 +1,35 @@ +From 7b2377486767503d47265e4d487a63c651f6b55d Mon Sep 17 00:00:00 2001 +From: Hou Tao +Date: Mon, 15 Jun 2020 11:33:23 +0800 +Subject: dm zoned: assign max_io_len correctly + +From: Hou Tao + +commit 7b2377486767503d47265e4d487a63c651f6b55d upstream. + +The unit of max_io_len is sector instead of byte (spotted through +code review), so fix it. + +Fixes: 3b1a94c88b79 ("dm zoned: drive-managed zoned block device target") +Cc: stable@vger.kernel.org +Signed-off-by: Hou Tao +Reviewed-by: Damien Le Moal +Signed-off-by: Mike Snitzer +Signed-off-by: Greg Kroah-Hartman + + +--- + drivers/md/dm-zoned-target.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/md/dm-zoned-target.c ++++ b/drivers/md/dm-zoned-target.c +@@ -790,7 +790,7 @@ static int dmz_ctr(struct dm_target *ti, + } + + /* Set target (no write same support) */ +- ti->max_io_len = dev->zone_nr_sectors << 9; ++ ti->max_io_len = dev->zone_nr_sectors; + ti->num_flush_bios = 1; + ti->num_discard_bios = 1; + ti->num_write_zeroes_bios = 1; diff --git a/queue-5.4/efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch b/queue-5.4/efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch new file mode 100644 index 00000000000..58265724d37 --- /dev/null +++ b/queue-5.4/efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch @@ -0,0 +1,58 @@ +From 435d1a471598752446a72ad1201b3c980526d869 Mon Sep 17 00:00:00 2001 +From: Peter Jones +Date: Mon, 15 Jun 2020 16:24:08 -0400 +Subject: efi: Make it possible to disable efivar_ssdt entirely + +From: Peter Jones + +commit 435d1a471598752446a72ad1201b3c980526d869 upstream. + +In most cases, such as CONFIG_ACPI_CUSTOM_DSDT and +CONFIG_ACPI_TABLE_UPGRADE, boot-time modifications to firmware tables +are tied to specific Kconfig options. Currently this is not the case +for modifying the ACPI SSDT via the efivar_ssdt kernel command line +option and associated EFI variable. + +This patch adds CONFIG_EFI_CUSTOM_SSDT_OVERLAYS, which defaults +disabled, in order to allow enabling or disabling that feature during +the build. + +Cc: +Signed-off-by: Peter Jones +Link: https://lore.kernel.org/r/20200615202408.2242614-1-pjones@redhat.com +Signed-off-by: Ard Biesheuvel +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/firmware/efi/Kconfig | 11 +++++++++++ + drivers/firmware/efi/efi.c | 2 +- + 2 files changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/firmware/efi/Kconfig ++++ b/drivers/firmware/efi/Kconfig +@@ -219,3 +219,14 @@ config EFI_EARLYCON + depends on SERIAL_EARLYCON && !ARM && !IA64 + select FONT_SUPPORT + select ARCH_USE_MEMREMAP_PROT ++ ++config EFI_CUSTOM_SSDT_OVERLAYS ++ bool "Load custom ACPI SSDT overlay from an EFI variable" ++ depends on EFI_VARS && ACPI ++ default ACPI_TABLE_UPGRADE ++ help ++ Allow loading of an ACPI SSDT overlay from an EFI variable specified ++ by a kernel command line option. ++ ++ See Documentation/admin-guide/acpi/ssdt-overlays.rst for more ++ information. +--- a/drivers/firmware/efi/efi.c ++++ b/drivers/firmware/efi/efi.c +@@ -217,7 +217,7 @@ static void generic_ops_unregister(void) + efivars_unregister(&generic_efivars); + } + +-#if IS_ENABLED(CONFIG_ACPI) ++#ifdef CONFIG_EFI_CUSTOM_SSDT_OVERLAYS + #define EFIVAR_SSDT_NAME_MAX 16 + static char efivar_ssdt[EFIVAR_SSDT_NAME_MAX] __initdata; + static int __init efivar_ssdt_setup(char *str) diff --git a/queue-5.4/series b/queue-5.4/series index c69cbd9ce73..f874f6dc6c8 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -60,3 +60,6 @@ dma-buf-move-dma_buf_release-from-fops-to-dentry_ops.patch irqchip-gic-atomically-update-affinity.patch mm-compaction-fully-assume-capture-is-not-null-in-compact_zone_order.patch mm-compaction-make-capture-control-handling-safe-wrt-interrupts.patch +x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch +dm-zoned-assign-max_io_len-correctly.patch +efi-make-it-possible-to-disable-efivar_ssdt-entirely.patch diff --git a/queue-5.4/x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch b/queue-5.4/x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch new file mode 100644 index 00000000000..80b77f61fae --- /dev/null +++ b/queue-5.4/x86-resctrl-fix-memory-bandwidth-counter-width-for-amd.patch @@ -0,0 +1,106 @@ +From 2c18bd525c47f882f033b0a813ecd09c93e1ecdf Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 Jun 2020 14:45:16 -0500 +Subject: x86/resctrl: Fix memory bandwidth counter width for AMD +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Babu Moger + +commit 2c18bd525c47f882f033b0a813ecd09c93e1ecdf upstream. + +Memory bandwidth is calculated reading the monitoring counter +at two intervals and calculating the delta. It is the software’s +responsibility to read the count often enough to avoid having +the count roll over _twice_ between reads. + +The current code hardcodes the bandwidth monitoring counter's width +to 24 bits for AMD. This is due to default base counter width which +is 24. Currently, AMD does not implement the CPUID 0xF.[ECX=1]:EAX +to adjust the counter width. But, the AMD hardware supports much +wider bandwidth counter with the default width of 44 bits. + +Kernel reads these monitoring counters every 1 second and adjusts the +counter value for overflow. With 24 bits and scale value of 64 for AMD, +it can only measure up to 1GB/s without overflowing. For the rates +above 1GB/s this will fail to measure the bandwidth. + +Fix the issue setting the default width to 44 bits by adjusting the +offset. + +AMD future products will implement CPUID 0xF.[ECX=1]:EAX. + + [ bp: Let the line stick out and drop {}-brackets around a single + statement. ] + +Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") +Signed-off-by: Babu Moger +Signed-off-by: Borislav Petkov +Link: https://lkml.kernel.org/r/159129975546.62538.5656031125604254041.stgit@naples-babu.amd.com +Signed-off-by: Greg Kroah-Hartman + + +--- + arch/x86/kernel/cpu/resctrl/core.c | 2 ++ + arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ + arch/x86/kernel/cpu/resctrl/monitor.c | 3 ++- + 3 files changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/resctrl/core.c ++++ b/arch/x86/kernel/cpu/resctrl/core.c +@@ -260,6 +260,7 @@ static bool __get_mem_config_intel(struc + r->num_closid = edx.split.cos_max + 1; + r->membw.max_delay = eax.split.max_delay + 1; + r->default_ctrl = MAX_MBA_BW; ++ r->membw.mbm_width = MBM_CNTR_WIDTH; + if (ecx & MBA_IS_LINEAR) { + r->membw.delay_linear = true; + r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay; +@@ -289,6 +290,7 @@ static bool __rdt_get_mem_config_amd(str + /* AMD does not use delay */ + r->membw.delay_linear = false; + ++ r->membw.mbm_width = MBM_CNTR_WIDTH_AMD; + r->membw.min_bw = 0; + r->membw.bw_gran = 1; + /* Max value is 2048, Data width should be 4 in decimal */ +--- a/arch/x86/kernel/cpu/resctrl/internal.h ++++ b/arch/x86/kernel/cpu/resctrl/internal.h +@@ -32,6 +32,7 @@ + #define CQM_LIMBOCHECK_INTERVAL 1000 + + #define MBM_CNTR_WIDTH 24 ++#define MBM_CNTR_WIDTH_AMD 44 + #define MBM_OVERFLOW_INTERVAL 1000 + #define MAX_MBA_BW 100u + #define MBA_IS_LINEAR 0x4 +@@ -368,6 +369,7 @@ struct rdt_cache { + * @min_bw: Minimum memory bandwidth percentage user can request + * @bw_gran: Granularity at which the memory bandwidth is allocated + * @delay_linear: True if memory B/W delay is in linear scale ++ * @mbm_width: memory B/W monitor counter width + * @mba_sc: True if MBA software controller(mba_sc) is enabled + * @mb_map: Mapping of memory B/W percentage to memory B/W delay + */ +@@ -376,6 +378,7 @@ struct rdt_membw { + u32 min_bw; + u32 bw_gran; + u32 delay_linear; ++ u32 mbm_width; + bool mba_sc; + u32 *mb_map; + }; +--- a/arch/x86/kernel/cpu/resctrl/monitor.c ++++ b/arch/x86/kernel/cpu/resctrl/monitor.c +@@ -216,8 +216,9 @@ void free_rmid(u32 rmid) + + static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr) + { +- u64 shift = 64 - MBM_CNTR_WIDTH, chunks; ++ u64 shift, chunks; + ++ shift = 64 - rdt_resources_all[RDT_RESOURCE_MBA].membw.mbm_width; + chunks = (cur_msr << shift) - (prev_msr << shift); + return chunks >>= shift; + } -- 2.47.3