From c512c9090f52e7666730db9117c6ec6ca11cf3b8 Mon Sep 17 00:00:00 2001 From: Alex Coplan Date: Thu, 19 Jun 2025 12:38:11 +0100 Subject: [PATCH] aarch64: Drop const_int from aarch64_maskload_else_operand The "else operand" to maskload should always be a const_vector, never a const_int. This was just an issue I noticed while looking through the code, I don't have a testcase which shows a concrete problem due to this. Testing of that change alone showed ICEs with load lanes vectorization and SVE. That turned out to be because the backend pattern was missing a mode for the else operand (causing the middle-end to choose a const_int during expansion), fixed thusly. That in turn exposed an issue with the unpredicated load lanes expander which was using the wrong mode for the else operand, so fixed that too. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (vec_load_lanes): Expand else operand in subvector mode, as per optab documentation. (vec_mask_load_lanes): Add missing mode for operand 3. * config/aarch64/predicates.md (aarch64_maskload_else_operand): Remove const_int. --- gcc/config/aarch64/aarch64-sve.md | 4 ++-- gcc/config/aarch64/predicates.md | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 450975dd088..4aecb3a6bf8 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1344,7 +1344,7 @@ "TARGET_SVE" { operands[2] = aarch64_ptrue_reg (mode); - operands[3] = CONST0_RTX (mode); + operands[3] = CONST0_RTX (mode); } ) @@ -1354,7 +1354,7 @@ (unspec:SVE_STRUCT [(match_operand: 2 "register_operand" "Upl") (match_operand:SVE_STRUCT 1 "memory_operand" "m") - (match_operand 3 "aarch64_maskload_else_operand")] + (match_operand: 3 "aarch64_maskload_else_operand")] UNSPEC_LDN))] "TARGET_SVE" "ld\t%0, %2/z, %1" diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index d8e9725a1b6..32056daf329 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -1076,5 +1076,5 @@ && !(INTVAL (op) & 0xf)"))) (define_predicate "aarch64_maskload_else_operand" - (and (match_code "const_int,const_vector") + (and (match_code "const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) -- 2.47.2