From c8b8f8a491b250b8b716c0460705f827ffaa2f6c Mon Sep 17 00:00:00 2001 From: Florian Krohm Date: Fri, 19 Sep 2025 15:15:39 +0000 Subject: [PATCH] s390: disasm-test: Fix a few opcode specs. Namely: eedtr, eextr, esdtr, esxtr, iedtr, iextr, rrdtr, rrxtr Wrong register class was used. binutils 2.44 let that slide by. 2.45 does not. --- none/tests/s390x/disasm-test/opcode.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c index e98a5e9e5..df8ca7e8c 100644 --- a/none/tests/s390x/disasm-test/opcode.c +++ b/none/tests/s390x/disasm-test/opcode.c @@ -1157,12 +1157,12 @@ static const char *opcodes[] = { "dxtr f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13}", "ddtra f1,f2,f3,m4", "dxtra f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4", - "eedtr f1,f2", - "eextr f1,f2:{0,1,4,5,8,9,12,13}", - "esdtr f1,f2", - "esxtr f1,f2:{0,1,4,5,8,9,12,13}", - "iedtr f1,f3,f2", - "iextr f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2", + "eedtr r1,f2", + "eextr r1,f2:{0,1,4,5,8,9,12,13}", + "esdtr r1,f2", + "esxtr r1,f2:{0,1,4,5,8,9,12,13}", + "iedtr f1,f3,r2", + "iextr f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},r2", "ltdtr f1,f2", "ltxtr f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}", // fidtr not implemented @@ -1177,8 +1177,8 @@ static const char *opcodes[] = { "mxtra f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4", "qadtr f1,f3,f2,m4", "qaxtr f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},m4", - "rrdtr f1,f3,f2,m4", - "rrxtr f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2,m4", + "rrdtr f1,f3,r2,m4", + "rrxtr f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},r2,m4", "sldt f1,f3,d12(x2,b2)", "slxt f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},d12(x2,b2)", "srdt f1,f3,d12(x2,b2)", -- 2.47.3