From c94ee67abd9d22d2f8cff93b3581d99695babe9f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Jun 2024 12:09:12 +0200 Subject: [PATCH] dt-bindings: soc: intel: lgm-syscon: Move to dedicated schema intel,lgm-syscon is not a simple syscon device - it has children - thus it should be fully documented in its own binding. Reviewed-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-3-3409903bb99b@linaro.org Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/syscon.yaml | 1 - .../bindings/soc/intel/intel,lgm-syscon.yaml | 57 +++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 0f8c26efa18a4..99838787d437d 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -57,7 +57,6 @@ properties: - hisilicon,pcie-sas-subctrl - hisilicon,peri-subctrl - hpe,gxp-sysreg - - intel,lgm-syscon - loongson,ls1b-syscon - loongson,ls1c-syscon - marvell,armada-3700-cpu-misc diff --git a/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml b/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml new file mode 100644 index 0000000000000..6951d55356d56 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain(LGM) Syscon + +maintainers: + - Chuanhua Lei + - Rahul Tanwar + +properties: + compatible: + items: + - const: intel,lgm-syscon + - const: syscon + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "^emmc-phy@[0-9a-f]+$": + $ref: /schemas/phy/intel,lgm-emmc-phy.yaml# + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + chiptop@e0200000 { + compatible = "intel,lgm-syscon", "syscon"; + reg = <0xe0200000 0x100>; + ranges = <0x0 0xe0200000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + emmc-phy@a8 { + compatible = "intel,lgm-emmc-phy"; + reg = <0x00a8 0x10>; + clocks = <&emmc>; + #phy-cells = <0>; + }; + }; -- 2.39.5