From d503425f034479bd7dc9bda456b1dcc7fe613966 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sat, 20 Jan 2024 19:19:12 -0500 Subject: [PATCH] Fixes for 6.7 Signed-off-by: Sasha Levin --- ...-fix-information-leak-in-sec_attest_.patch | 39 ++ ...r-extended-error-log-status-when-ras.patch | 48 ++ ...it-avoid-u32-multiplication-overflow.patch | 40 ++ ...x-the-fractional-clock-divider-flags.patch | 40 ++ ...-for-error-while-searching-for-backl.patch | 54 ++ ...add-clamp-in-scarlett2_mixer_ctl_put.patch | 39 ++ ...dd-missing-error-check-to-scarlett2_.patch | 44 ++ ...sing-error-check-to-scarlett2_.patch-10152 | 42 ++ ...add-missing-error-checks-to-_ctl_get.patch | 356 +++++++++++++ ...dd-missing-mutex-lock-around-get-met.patch | 54 ++ ...nci-always-select-config_cpu_arm926t.patch | 39 ++ ...q8064-correct-xoadc-register-address.patch | 40 ++ ...m8226-provide-dsi-phy-clocks-to-mmcc.patch | 42 ++ ...qcom-sdx65-correct-pcie-ep-phy-names.patch | 41 ++ ...ts-qcom-sdx65-correct-spmi-node-name.patch | 39 ++ ...n-t-mix-scmi-and-non-scmi-board-comp.patch | 86 ++++ ...con-hikey970-pmic-fix-regulator-cell.patch | 37 ++ ...s-imx8mm-reduce-gpu-to-nominal-speed.patch | 51 ++ ...ek-mt8183-correct-mdp3-dma-related-n.patch | 62 +++ ...ek-mt8186-fix-address-warning-for-ad.patch | 51 ++ ...ek-mt8186-fix-alias-prefix-for-ovl_2.patch | 38 ++ ...ek-mt8195-revise-vdosys-rdma-node-na.patch | 131 +++++ ...cer-aspire1-correct-audio-codec-defi.patch | 64 +++ ...pq6018-fix-clock-rates-for-gcc_usb0_.patch | 41 ++ ...s-qcom-qrb2210-rb1-use-usb-host-mode.patch | 45 ++ ...rb4210-rb2-don-t-force-usb-periphera.patch | 41 ++ ...rb5165-rb5-correct-led-panic-indicat.patch | 42 ++ ...a8775p-fix-usb-wakeup-interrupt-type.patch | 67 +++ ...a8775p-make-watchdog-bark-interrupt-.patch | 42 ++ ...c7180-make-watchdog-bark-interrupt-e.patch | 58 +++ ...rm64-dts-qcom-sc7280-fix-up-gpu-sids.patch | 44 ++ ...c7280-fix-usb_2-wakeup-interrupt-typ.patch | 43 ++ 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00000000000..cc66affc394 --- /dev/null +++ b/queue-6.7/accel-habanalabs-fix-information-leak-in-sec_attest_.patch @@ -0,0 +1,39 @@ +From b97c4f79a163658e7fb04d86df7eb311d2fd45f1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 21:00:59 +0800 +Subject: accel/habanalabs: fix information leak in sec_attest_info() + +From: Xingyuan Mo + +[ Upstream commit a9f07790a4b2250f0140e9a61c7f842fd9b618c7 ] + +This function may copy the pad0 field of struct hl_info_sec_attest to user +mode which has not been initialized, resulting in leakage of kernel heap +data to user mode. To prevent this, use kzalloc() to allocate and zero out +the buffer, which can also eliminate other uninitialized holes, if any. + +Fixes: 0c88760f8f5e ("habanalabs/gaudi2: add secured attestation info uapi") +Signed-off-by: Xingyuan Mo +Reviewed-by: Oded Gabbay +Signed-off-by: Oded Gabbay +Signed-off-by: Sasha Levin +--- + drivers/accel/habanalabs/common/habanalabs_ioctl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c +index 8ef36effb95b..a7cd625d82c0 100644 +--- a/drivers/accel/habanalabs/common/habanalabs_ioctl.c ++++ b/drivers/accel/habanalabs/common/habanalabs_ioctl.c +@@ -685,7 +685,7 @@ static int sec_attest_info(struct hl_fpriv *hpriv, struct hl_info_args *args) + if (!sec_attest_info) + return -ENOMEM; + +- info = kmalloc(sizeof(*info), GFP_KERNEL); ++ info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + rc = -ENOMEM; + goto free_sec_attest_info; +-- +2.43.0 + diff --git a/queue-6.7/acpi-extlog-clear-extended-error-log-status-when-ras.patch b/queue-6.7/acpi-extlog-clear-extended-error-log-status-when-ras.patch new file mode 100644 index 00000000000..03240fc720c --- /dev/null +++ b/queue-6.7/acpi-extlog-clear-extended-error-log-status-when-ras.patch @@ -0,0 +1,48 @@ +From dd0d2017f7d896115fa97ff8179feecee67a8374 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Dec 2023 13:22:39 -0800 +Subject: ACPI: extlog: Clear Extended Error Log status when RAS_CEC handled + the error + +From: Tony Luck + +[ Upstream commit 38c872a9e96f72f2947affc0526cc05659367d3d ] + +When both CONFIG_RAS_CEC and CONFIG_ACPI_EXTLOG are enabled, Linux does +not clear the status word of the BIOS supplied error record for corrected +errors. This may prevent logging of subsequent uncorrected errors. + +Fix by clearing the status. + +Fixes: 23ba710a0864 ("x86/mce: Fix all mce notifiers to update the mce->kflags bitmask") +Reported-by: Erwin Tsaur +Signed-off-by: Tony Luck +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_extlog.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_extlog.c b/drivers/acpi/acpi_extlog.c +index e120a96e1eae..71e8d4e7a36c 100644 +--- a/drivers/acpi/acpi_extlog.c ++++ b/drivers/acpi/acpi_extlog.c +@@ -145,9 +145,14 @@ static int extlog_print(struct notifier_block *nb, unsigned long val, + static u32 err_seq; + + estatus = extlog_elog_entry_check(cpu, bank); +- if (estatus == NULL || (mce->kflags & MCE_HANDLED_CEC)) ++ if (!estatus) + return NOTIFY_DONE; + ++ if (mce->kflags & MCE_HANDLED_CEC) { ++ estatus->block_status = 0; ++ return NOTIFY_DONE; ++ } ++ + memcpy(elog_buf, (void *)estatus, ELOG_ENTRY_LEN); + /* clear record status to enable BIOS to update it again */ + estatus->block_status = 0; +-- +2.43.0 + diff --git a/queue-6.7/acpi-lpit-avoid-u32-multiplication-overflow.patch b/queue-6.7/acpi-lpit-avoid-u32-multiplication-overflow.patch new file mode 100644 index 00000000000..9223215e34e --- /dev/null +++ b/queue-6.7/acpi-lpit-avoid-u32-multiplication-overflow.patch @@ -0,0 +1,40 @@ +From 3477c5f4e11d529e0c95a25f380ed503d4833282 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 21:08:59 +0300 +Subject: ACPI: LPIT: Avoid u32 multiplication overflow + +From: Nikita Kiryushin + +[ Upstream commit 56d2eeda87995245300836ee4dbd13b002311782 ] + +In lpit_update_residency() there is a possibility of overflow +in multiplication, if tsc_khz is large enough (> UINT_MAX/1000). + +Change multiplication to mul_u32_u32(). + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: eeb2d80d502a ("ACPI / LPIT: Add Low Power Idle Table (LPIT) support") +Signed-off-by: Nikita Kiryushin +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_lpit.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c +index c5598b6d5db8..794962c5c88e 100644 +--- a/drivers/acpi/acpi_lpit.c ++++ b/drivers/acpi/acpi_lpit.c +@@ -105,7 +105,7 @@ static void lpit_update_residency(struct lpit_residency_info *info, + return; + + info->frequency = lpit_native->counter_frequency ? +- lpit_native->counter_frequency : tsc_khz * 1000; ++ lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U); + if (!info->frequency) + info->frequency = 1; + +-- +2.43.0 + diff --git a/queue-6.7/acpi-lpss-fix-the-fractional-clock-divider-flags.patch b/queue-6.7/acpi-lpss-fix-the-fractional-clock-divider-flags.patch new file mode 100644 index 00000000000..37105424242 --- /dev/null +++ b/queue-6.7/acpi-lpss-fix-the-fractional-clock-divider-flags.patch @@ -0,0 +1,40 @@ +From 3b5f70b698926b82ef09911362d004ab68d79e4d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 13:14:29 +0200 +Subject: ACPI: LPSS: Fix the fractional clock divider flags + +From: Andy Shevchenko + +[ Upstream commit 3ebccf1d1ca74bbb78e6f8c38d1d172e468d91f8 ] + +The conversion to CLK_FRAC_DIVIDER_POWER_OF_TWO_PS uses wrong flags +in the parameters and hence miscalculates the values in the clock +divider. Fix this by applying the flag to the proper parameter. + +Fixes: 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag") +Reported-by: Alex Vinarskis +Signed-off-by: Andy Shevchenko +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_lpss.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c +index 875de44961bf..d48407472dfb 100644 +--- a/drivers/acpi/acpi_lpss.c ++++ b/drivers/acpi/acpi_lpss.c +@@ -461,8 +461,9 @@ static int register_device_clock(struct acpi_device *adev, + if (!clk_name) + return -ENOMEM; + clk = clk_register_fractional_divider(NULL, clk_name, parent, ++ 0, prv_base, 1, 15, 16, 15, + CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, +- prv_base, 1, 15, 16, 15, 0, NULL); ++ NULL); + parent = clk_name; + + clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); +-- +2.43.0 + diff --git a/queue-6.7/acpi-video-check-for-error-while-searching-for-backl.patch b/queue-6.7/acpi-video-check-for-error-while-searching-for-backl.patch new file mode 100644 index 00000000000..9951d57ef6f --- /dev/null +++ b/queue-6.7/acpi-video-check-for-error-while-searching-for-backl.patch @@ -0,0 +1,54 @@ +From 94e94c596b218470362258ebbd5d8cf5d62d85ac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 16:49:25 +0300 +Subject: ACPI: video: check for error while searching for backlight device + parent + +From: Nikita Kiryushin + +[ Upstream commit ccd45faf4973746c4f30ea41eec864e5cf191099 ] + +If acpi_get_parent() called in acpi_video_dev_register_backlight() +fails, for example, because acpi_ut_acquire_mutex() fails inside +acpi_get_parent), this can lead to incorrect (uninitialized) +acpi_parent handle being passed to acpi_get_pci_dev() for detecting +the parent pci device. + +Check acpi_get_parent() result and set parent device only in case of success. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 9661e92c10a9 ("acpi: tie ACPI backlight devices to PCI devices if possible") +Signed-off-by: Nikita Kiryushin +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_video.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c +index 6cee536c229a..375010e575d0 100644 +--- a/drivers/acpi/acpi_video.c ++++ b/drivers/acpi/acpi_video.c +@@ -1713,12 +1713,12 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device) + return; + count++; + +- acpi_get_parent(device->dev->handle, &acpi_parent); +- +- pdev = acpi_get_pci_dev(acpi_parent); +- if (pdev) { +- parent = &pdev->dev; +- pci_dev_put(pdev); ++ if (ACPI_SUCCESS(acpi_get_parent(device->dev->handle, &acpi_parent))) { ++ pdev = acpi_get_pci_dev(acpi_parent); ++ if (pdev) { ++ parent = &pdev->dev; ++ pci_dev_put(pdev); ++ } + } + + memset(&props, 0, sizeof(struct backlight_properties)); +-- +2.43.0 + diff --git a/queue-6.7/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch b/queue-6.7/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch new file mode 100644 index 00000000000..7b76f414088 --- /dev/null +++ b/queue-6.7/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch @@ -0,0 +1,39 @@ +From 3f937f6cd32e7ce89570f3255584ed81571ad0e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:52 +1030 +Subject: ALSA: scarlett2: Add clamp() in scarlett2_mixer_ctl_put() + +From: Geoffrey D. Bennett + +[ Upstream commit 04f8f053252b86c7583895c962d66747ecdc61b7 ] + +Ensure the value passed to scarlett2_mixer_ctl_put() is between 0 and +SCARLETT2_MIXER_MAX_VALUE so we don't attempt to access outside +scarlett2_mixer_values[]. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/3b19fb3da641b587749b85fe1daa1b4e696c0c1b.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett2.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c +index f4351900fbbd..cdaf0470e62b 100644 +--- a/sound/usb/mixer_scarlett2.c ++++ b/sound/usb/mixer_scarlett2.c +@@ -3663,7 +3663,8 @@ static int scarlett2_mixer_ctl_put(struct snd_kcontrol *kctl, + mutex_lock(&private->data_mutex); + + oval = private->mix[index]; +- val = ucontrol->value.integer.value[0]; ++ val = clamp(ucontrol->value.integer.value[0], ++ 0L, (long)SCARLETT2_MIXER_MAX_VALUE); + num_mixer_in = port_count[SCARLETT2_PORT_TYPE_MIX][SCARLETT2_PORT_OUT]; + mix_num = index / num_mixer_in; + +-- +2.43.0 + diff --git a/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch b/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch new file mode 100644 index 00000000000..c9286e067a1 --- /dev/null +++ b/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch @@ -0,0 +1,44 @@ +From ae6805724bc13633b3239b6507e90123258c4605 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:00 +1030 +Subject: ALSA: scarlett2: Add missing error check to scarlett2_config_save() + +From: Geoffrey D. Bennett + +[ Upstream commit 5f6ff6931a1c0065a55448108940371e1ac8075f ] + +scarlett2_config_save() was ignoring the return value from +scarlett2_usb(). As this function is not called from user-space we +can't return the error, so call usb_audio_err() instead. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/bf0a15332d852d7825fa6da87d2a0d9c0b702053.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett2.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c +index 33a3d1161885..35e45c337383 100644 +--- a/sound/usb/mixer_scarlett2.c ++++ b/sound/usb/mixer_scarlett2.c +@@ -1524,9 +1524,11 @@ static void scarlett2_config_save(struct usb_mixer_interface *mixer) + { + __le32 req = cpu_to_le32(SCARLETT2_USB_CONFIG_SAVE); + +- scarlett2_usb(mixer, SCARLETT2_USB_DATA_CMD, +- &req, sizeof(u32), +- NULL, 0); ++ int err = scarlett2_usb(mixer, SCARLETT2_USB_DATA_CMD, ++ &req, sizeof(u32), ++ NULL, 0); ++ if (err < 0) ++ usb_audio_err(mixer->chip, "config save failed: %d\n", err); + } + + /* Delayed work to save config */ +-- +2.43.0 + diff --git a/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-10152 b/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-10152 new file mode 100644 index 00000000000..3eedf580c21 --- /dev/null +++ b/queue-6.7/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-10152 @@ -0,0 +1,42 @@ +From ac1fb53a4d3bde92814e4b9431df9738874cc990 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:21 +1030 +Subject: ALSA: scarlett2: Add missing error check to + scarlett2_usb_set_config() + +From: Geoffrey D. Bennett + +[ Upstream commit ca459dfa7d4ed9098fcf13e410963be6ae9b6bf3 ] + +scarlett2_usb_set_config() calls scarlett2_usb_get() but was not +checking the result. Return the error if it fails rather than +continuing with an invalid value. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e15fae6c51a ("ALSA: usb-audio: scarlett2: Allow bit-level access to config") +Link: https://lore.kernel.org/r/def110c5c31dbdf0a7414d258838a0a31c0fab67.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett2.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c +index 35e45c337383..a6e72862d30f 100644 +--- a/sound/usb/mixer_scarlett2.c ++++ b/sound/usb/mixer_scarlett2.c +@@ -1577,7 +1577,10 @@ static int scarlett2_usb_set_config( + size = 1; + offset = config_item->offset; + +- scarlett2_usb_get(mixer, offset, &tmp, 1); ++ err = scarlett2_usb_get(mixer, offset, &tmp, 1); ++ if (err < 0) ++ return err; ++ + if (value) + tmp |= (1 << index); + else +-- +2.43.0 + diff --git a/queue-6.7/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch b/queue-6.7/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch new file mode 100644 index 00000000000..b8c7882a934 --- /dev/null +++ b/queue-6.7/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch @@ -0,0 +1,356 @@ +From 5d5d83257b0c504579bd4b8b7d10a7dabfced9d3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:37 +1030 +Subject: ALSA: scarlett2: Add missing error checks to *_ctl_get() + +From: Geoffrey D. Bennett + +[ Upstream commit 50603a67daef161c78c814580d57f7f0be57167e ] + +The *_ctl_get() functions which call scarlett2_update_*() were not +checking the return value. Fix to check the return value and pass to +the caller. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/32a5fdc83b05fa74e0fcdd672fbf71d75c5f0a6d.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett2.c | 182 +++++++++++++++++++++++++----------- + 1 file changed, 130 insertions(+), 52 deletions(-) + +diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c +index a6e72862d30f..f4351900fbbd 100644 +--- a/sound/usb/mixer_scarlett2.c ++++ b/sound/usb/mixer_scarlett2.c +@@ -2100,14 +2100,20 @@ static int scarlett2_sync_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->sync_updated) +- scarlett2_update_sync(mixer); ++ ++ if (private->sync_updated) { ++ err = scarlett2_update_sync(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->sync; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static const struct snd_kcontrol_new scarlett2_sync_ctl = { +@@ -2190,14 +2196,20 @@ static int scarlett2_master_volume_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->master_vol; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int line_out_remap(struct scarlett2_data *private, int index) +@@ -2223,14 +2235,20 @@ static int scarlett2_volume_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->vol[index]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_volume_ctl_put(struct snd_kcontrol *kctl, +@@ -2297,14 +2315,20 @@ static int scarlett2_mute_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->mute_switch[index]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_mute_ctl_put(struct snd_kcontrol *kctl, +@@ -2550,14 +2574,20 @@ static int scarlett2_level_enum_ctl_get(struct snd_kcontrol *kctl, + const struct scarlett2_device_info *info = private->info; + + int index = elem->control + info->level_input_first; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->level_switch[index]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_level_enum_ctl_put(struct snd_kcontrol *kctl, +@@ -2608,15 +2638,21 @@ static int scarlett2_pad_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = + private->pad_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_pad_ctl_put(struct snd_kcontrol *kctl, +@@ -2666,14 +2702,20 @@ static int scarlett2_air_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->air_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_air_ctl_put(struct snd_kcontrol *kctl, +@@ -2723,15 +2765,21 @@ static int scarlett2_phantom_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = + private->phantom_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_phantom_ctl_put(struct snd_kcontrol *kctl, +@@ -2903,14 +2951,20 @@ static int scarlett2_direct_monitor_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = elem->head.mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->direct_monitor_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_direct_monitor_ctl_put( +@@ -3010,14 +3064,20 @@ static int scarlett2_speaker_switch_enum_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->speaker_switching_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + /* when speaker switching gets enabled, switch the main/alt speakers +@@ -3165,14 +3225,20 @@ static int scarlett2_talkback_enum_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->talkback_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_talkback_enum_ctl_put( +@@ -3320,14 +3386,20 @@ static int scarlett2_dim_mute_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->dim_mute[elem->control]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_dim_mute_ctl_put(struct snd_kcontrol *kctl, +@@ -3698,14 +3770,20 @@ static int scarlett2_mux_src_enum_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->mux_updated) +- scarlett2_usb_get_mux(mixer); ++ ++ if (private->mux_updated) { ++ err = scarlett2_usb_get_mux(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->mux[index]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_mux_src_enum_ctl_put(struct snd_kcontrol *kctl, +-- +2.43.0 + diff --git a/queue-6.7/alsa-scarlett2-add-missing-mutex-lock-around-get-met.patch b/queue-6.7/alsa-scarlett2-add-missing-mutex-lock-around-get-met.patch new file mode 100644 index 00000000000..77e6b0dc7bd --- /dev/null +++ b/queue-6.7/alsa-scarlett2-add-missing-mutex-lock-around-get-met.patch @@ -0,0 +1,54 @@ +From 45460f8a8699b848522fbbeef21cc7512925671c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:08:09 +1030 +Subject: ALSA: scarlett2: Add missing mutex lock around get meter levels + +From: Geoffrey D. Bennett + +[ Upstream commit 993f7b42fa066b055e3a19b7f76ad8157c0927a0 ] + +As scarlett2_meter_ctl_get() uses meter_level_map[], the data_mutex +should be locked while accessing it. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 3473185f31df ("ALSA: scarlett2: Remap Level Meter values") +Link: https://lore.kernel.org/r/77e093c27402c83d0730681448fa4f57583349dd.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett2.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c +index cdaf0470e62b..3b7fcd0907e6 100644 +--- a/sound/usb/mixer_scarlett2.c ++++ b/sound/usb/mixer_scarlett2.c +@@ -3880,10 +3880,12 @@ static int scarlett2_meter_ctl_get(struct snd_kcontrol *kctl, + u16 meter_levels[SCARLETT2_MAX_METERS]; + int i, err; + ++ mutex_lock(&private->data_mutex); ++ + err = scarlett2_usb_get_meter_levels(elem->head.mixer, elem->channels, + meter_levels); + if (err < 0) +- return err; ++ goto unlock; + + /* copy & translate from meter_levels[] using meter_level_map[] */ + for (i = 0; i < elem->channels; i++) { +@@ -3898,7 +3900,10 @@ static int scarlett2_meter_ctl_get(struct snd_kcontrol *kctl, + ucontrol->value.integer.value[i] = value; + } + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ ++ return err; + } + + static const struct snd_kcontrol_new scarlett2_meter_ctl = { +-- +2.43.0 + diff --git a/queue-6.7/arm-davinci-always-select-config_cpu_arm926t.patch b/queue-6.7/arm-davinci-always-select-config_cpu_arm926t.patch new file mode 100644 index 00000000000..532e8413bfb --- /dev/null +++ b/queue-6.7/arm-davinci-always-select-config_cpu_arm926t.patch @@ -0,0 +1,39 @@ +From 819387346511868dae2ed9d6d6189fbcbfeca386 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Jan 2024 12:00:36 +0100 +Subject: ARM: davinci: always select CONFIG_CPU_ARM926T + +From: Arnd Bergmann + +[ Upstream commit 40974ee421b4d1fc74ac733d86899ce1b83d8f65 ] + +The select was lost by accident during the multiplatform conversion. +Any davinci-only + +arm-linux-gnueabi-ld: arch/arm/mach-davinci/sleep.o: in function `CACHE_FLUSH': +(.text+0x168): undefined reference to `arm926_flush_kern_cache_all' + +Fixes: f962396ce292 ("ARM: davinci: support multiplatform build for ARM v5") +Acked-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20240108110055.1531153-1-arnd@kernel.org +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/mach-davinci/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig +index 4316e1370627..59de137c6f53 100644 +--- a/arch/arm/mach-davinci/Kconfig ++++ b/arch/arm/mach-davinci/Kconfig +@@ -4,6 +4,7 @@ menuconfig ARCH_DAVINCI + bool "TI DaVinci" + depends on ARCH_MULTI_V5 + depends on CPU_LITTLE_ENDIAN ++ select CPU_ARM926T + select DAVINCI_TIMER + select ZONE_DMA + select PM_GENERIC_DOMAINS if PM +-- +2.43.0 + diff --git a/queue-6.7/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch b/queue-6.7/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch new file mode 100644 index 00000000000..0eac1e8a029 --- /dev/null +++ b/queue-6.7/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch @@ -0,0 +1,40 @@ +From 71f2eb9834dbd81cb2a0b651938202417c9ebe5f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Sep 2023 14:02:35 +0300 +Subject: ARM: dts: qcom: apq8064: correct XOADC register address + +From: Dmitry Baryshkov + +[ Upstream commit 554557542e709e190eff8a598f0cde02647d533a ] + +The XOADC is present at the address 0x197 rather than just 197. It +doesn't change a lot (since the driver hardcodes all register +addresses), but the DT should present correct address anyway. + +Fixes: c4b70883ee33 ("ARM: dts: add XOADC and IIO HWMON to APQ8064") +Reviewed-by: Konrad Dybcio +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230928110309.1212221-3-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +index 59fd86b9fb47..099a16c34e1f 100644 +--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +@@ -738,7 +738,7 @@ pwrkey@1c { + + xoadc: xoadc@197 { + compatible = "qcom,pm8921-adc"; +- reg = <197>; ++ reg = <0x197>; + interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; +-- +2.43.0 + diff --git a/queue-6.7/arm-dts-qcom-msm8226-provide-dsi-phy-clocks-to-mmcc.patch b/queue-6.7/arm-dts-qcom-msm8226-provide-dsi-phy-clocks-to-mmcc.patch new file mode 100644 index 00000000000..6fe9c114a51 --- /dev/null +++ b/queue-6.7/arm-dts-qcom-msm8226-provide-dsi-phy-clocks-to-mmcc.patch @@ -0,0 +1,42 @@ +From 600d71604ff0ceea99d7756641096a483fb53515 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jul 2023 09:52:07 +0200 +Subject: ARM: dts: qcom: msm8226: provide dsi phy clocks to mmcc + +From: Luca Weiss + +[ Upstream commit 836d083524888069cd358776a4e6c4ceec04962e ] + +Some mmcc clocks have dsi0pll & dsi0pllbyte as clock parents so we +should provide them in the dt, which I missed in the commit adding the +mdss nodes. + +Fixes: d5fb01ad5eb4 ("ARM: dts: qcom: msm8226: Add mdss nodes") +Signed-off-by: Luca Weiss +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230712-msm8226-dsi-clock-fixup-v1-1-71010b0b89ca@z3ntu.xyz +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +index 97a377b5a0ec..5cd03ea7b084 100644 +--- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +@@ -442,8 +442,8 @@ mmcc: clock-controller@fd8c0000 { + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, +- <0>, +- <0>; ++ <&mdss_dsi0_phy 1>, ++ <&mdss_dsi0_phy 0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", +-- +2.43.0 + diff --git a/queue-6.7/arm-dts-qcom-sdx65-correct-pcie-ep-phy-names.patch b/queue-6.7/arm-dts-qcom-sdx65-correct-pcie-ep-phy-names.patch new file mode 100644 index 00000000000..347b1bfc1b7 --- /dev/null +++ b/queue-6.7/arm-dts-qcom-sdx65-correct-pcie-ep-phy-names.patch @@ -0,0 +1,41 @@ +From 84a6dbf8713b6044c94a26aa8a658ba102bfc146 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Sep 2023 20:31:01 +0200 +Subject: ARM: dts: qcom: sdx65: correct PCIe EP phy-names + +From: Krzysztof Kozlowski + +[ Upstream commit 94da379dba88c4cdd562bad21c9ba5656e5ed5df ] + +Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": + + arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected + +Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP") +Reviewed-by: Konrad Dybcio +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Manivannan Sadhasivam +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230924183103.49487-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +index e559adaaeee7..648899b5220f 100644 +--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +@@ -338,7 +338,7 @@ pcie_ep: pcie-ep@1c00000 { + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; +- phy-names = "pcie-phy"; ++ phy-names = "pciephy"; + + max-link-speed = <3>; + num-lanes = <2>; +-- +2.43.0 + diff --git a/queue-6.7/arm-dts-qcom-sdx65-correct-spmi-node-name.patch b/queue-6.7/arm-dts-qcom-sdx65-correct-spmi-node-name.patch new file mode 100644 index 00000000000..5e95b6e6a80 --- /dev/null +++ b/queue-6.7/arm-dts-qcom-sdx65-correct-spmi-node-name.patch @@ -0,0 +1,39 @@ +From 9d074c2dc9f2bde181a1ae7886af3c56f9ea33ff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Sep 2023 20:31:03 +0200 +Subject: ARM: dts: qcom: sdx65: correct SPMI node name + +From: Krzysztof Kozlowski + +[ Upstream commit a900ad783f507cb396e402827052e70c0c565ae9 ] + +Node names should not have vendor prefixes: + + qcom-sdx65-mtp.dtb: qcom,spmi@c440000: $nodename:0: 'qcom,spmi@c440000' does not match '^spmi@.* + +Reviewed-by: Konrad Dybcio +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230924183103.49487-3-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +index 648899b5220f..27b7f50a1832 100644 +--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi ++++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +@@ -530,7 +530,7 @@ restart@c264000 { + reg = <0x0c264000 0x1000>; + }; + +- spmi_bus: qcom,spmi@c440000 { ++ spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, +-- +2.43.0 + diff --git a/queue-6.7/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch b/queue-6.7/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch new file mode 100644 index 00000000000..38e80a03b36 --- /dev/null +++ b/queue-6.7/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch @@ -0,0 +1,86 @@ +From 0c2439e3006b3bc61db52825fa0e6995c1a9d7bc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 19:52:34 +0100 +Subject: ARM: dts: stm32: don't mix SCMI and non-SCMI board compatibles + +From: Ahmad Fatoum + +[ Upstream commit bfc3c6743de0ecb169026c36cbdbc0d12d22a528 ] + +The binding erroneously decreed that the SCMI variants of the ST +evaluation kits are compatible with the non-SCMI variants. + +This is not correct, as a kernel or bootloader compatible with the non-SCMI +variant is not necessarily able to function, when direct access +to resources is replaced by having to talk SCMI to the secure monitor. + +The binding has been adjusted to reflect thus, so synchronize the device +trees now. + +Fixes: 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)") +Signed-off-by: Ahmad Fatoum +Signed-off-by: Alexandre Torgue +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 2 +- + arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 2 +- + arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 2 +- + arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 3 +-- + 4 files changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +index afcd6285890c..c27963898b5e 100644 +--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts ++++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; +- compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; ++ compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { +diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +index 39358d902000..622618943134 100644 +--- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; +- compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; ++ compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { +diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +index 07ea765a4553..c7c4d7e89d61 100644 +--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; +- compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; ++ compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { +diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +index 813086ec2489..2ab77e64f1bb 100644 +--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +@@ -11,8 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; +- compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", +- "st,stm32mp157"; ++ compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch b/queue-6.7/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch new file mode 100644 index 00000000000..f2a3f5296a3 --- /dev/null +++ b/queue-6.7/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch @@ -0,0 +1,37 @@ +From 0515b2a7d89189239c0b667c8cca44201ab808c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 18:56:34 +0100 +Subject: arm64: dts: hisilicon: hikey970-pmic: fix regulator cells properties + +From: Johan Hovold + +[ Upstream commit 44ab3ee76a5a977864ba0bb6c352dcf6206804e0 ] + +The Hi6421 PMIC regulator child nodes do not have unit addresses so drop +the incorrect '#address-cells' and '#size-cells' properties. + +Fixes: 6219b20e1ecd ("arm64: dts: hisilicon: Add support for Hikey 970 PMIC") +Signed-off-by: Johan Hovold +Signed-off-by: Wei Xu +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +index 970047f2dabd..c06e011a6c3f 100644 +--- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi ++++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +@@ -25,9 +25,6 @@ pmic: pmic@0 { + gpios = <&gpio28 0 0>; + + regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- + ldo3: ldo3 { /* HDMI */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch b/queue-6.7/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch new file mode 100644 index 00000000000..8c4f5e3e1da --- /dev/null +++ b/queue-6.7/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch @@ -0,0 +1,51 @@ +From da98518003ca62aab2efdd1ce3ec66850bc38d43 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 14:02:16 -0600 +Subject: arm64: dts: imx8mm: Reduce GPU to nominal speed + +From: Adam Ford + +[ Upstream commit 1f794d3eed5345413c2b0cf1bcccc92d77681220 ] + +When the GPU nodes were added, the GPU_PLL_OUT was configured +for 1000MHz, but this requires the SoC to run in overdrive mode +which requires an elevated voltage operating point. + +Since this may run some boards out of spec, the default clock +should be set to 800MHz for nominal operating mode. Boards +that run at the higher voltage can update their clocks +accordingly. + +Fixes: 4523be8e46be ("arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core") +Signed-off-by: Adam Ford +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +index 738024baaa57..54faf83cb436 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -1408,7 +1408,7 @@ gpu_3d: gpu@38000000 { + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; +- assigned-clock-rates = <0>, <1000000000>; ++ assigned-clock-rates = <0>, <800000000>; + power-domains = <&pgc_gpu>; + }; + +@@ -1423,7 +1423,7 @@ gpu_2d: gpu@38008000 { + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; +- assigned-clock-rates = <0>, <1000000000>; ++ assigned-clock-rates = <0>, <800000000>; + power-domains = <&pgc_gpu>; + }; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch b/queue-6.7/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch new file mode 100644 index 00000000000..8e5697cffe4 --- /dev/null +++ b/queue-6.7/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch @@ -0,0 +1,62 @@ +From 44a3da1013fb549d0679a8340b997652e8ab89ea Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Oct 2023 17:48:38 +0800 +Subject: arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes + +From: Moudy Ho + +[ Upstream commit 188ffcd7fea79af3cac441268fc99f60e87f03b3 ] + +In order to generalize the node names, the DMA-related nodes +corresponding to MT8183 MDP3 need to be corrected. + +Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes") +Signed-off-by: Moudy Ho +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi +index 976dc968b3ca..df6e9990cd5f 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi +@@ -1660,7 +1660,7 @@ mmsys: syscon@14000000 { + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + +- mdp3-rdma0@14001000 { ++ dma-controller0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; +@@ -1672,6 +1672,7 @@ mdp3-rdma0@14001000 { + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; ++ #dma-cells = <1>; + }; + + mdp3-rsz0@14003000 { +@@ -1692,7 +1693,7 @@ mdp3-rsz1@14004000 { + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + +- mdp3-wrot0@14005000 { ++ dma-controller@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; +@@ -1701,6 +1702,7 @@ mdp3-wrot0@14005000 { + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; ++ #dma-cells = <1>; + }; + + mdp3-wdma@14006000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-mediatek-mt8186-fix-address-warning-for-ad.patch b/queue-6.7/arm64-dts-mediatek-mt8186-fix-address-warning-for-ad.patch new file mode 100644 index 00000000000..d23cf1eae40 --- /dev/null +++ b/queue-6.7/arm64-dts-mediatek-mt8186-fix-address-warning-for-ad.patch @@ -0,0 +1,51 @@ +From 6c8c1b9b5e8b92279c1f7d67c3ae207f122e2dad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:55:33 +0200 +Subject: arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes + +From: Eugen Hristev + +[ Upstream commit 840e341bed3c4331061031dc9db0aff04abafb4b ] + +Fix warnings reported by dtbs_check : + +arch/arm64/boot/dts/mediatek/mt8186.dtsi:1163.35-1168.5: Warning (simple_bus_reg): + /soc/mailbox@10686000: simple-bus unit address format error, expected "10686100" +arch/arm64/boot/dts/mediatek/mt8186.dtsi:1170.35-1175.5: Warning (simple_bus_reg): + /soc/mailbox@10687000: simple-bus unit address format error, expected "10687100" + +by having the right bus address as node name. + +Fixes: 379cf0e639ae ("arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes") +Signed-off-by: Eugen Hristev +Link: https://lore.kernel.org/r/20231204135533.21327-1-eugen.hristev@collabora.com +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/mediatek/mt8186.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi +index 021397671099..2fec6fd1c1a7 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi +@@ -1160,14 +1160,14 @@ adsp: adsp@10680000 { + status = "disabled"; + }; + +- adsp_mailbox0: mailbox@10686000 { ++ adsp_mailbox0: mailbox@10686100 { + compatible = "mediatek,mt8186-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10686100 0 0x1000>; + interrupts = ; + }; + +- adsp_mailbox1: mailbox@10687000 { ++ adsp_mailbox1: mailbox@10687100 { + compatible = "mediatek,mt8186-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10687100 0 0x1000>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-mediatek-mt8186-fix-alias-prefix-for-ovl_2.patch b/queue-6.7/arm64-dts-mediatek-mt8186-fix-alias-prefix-for-ovl_2.patch new file mode 100644 index 00000000000..c8362f6cc37 --- /dev/null +++ b/queue-6.7/arm64-dts-mediatek-mt8186-fix-alias-prefix-for-ovl_2.patch @@ -0,0 +1,38 @@ +From 4d0739679096d22d002efa57023df9b59c71964f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 15:40:31 +0800 +Subject: arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0 + +From: Chen-Yu Tsai + +[ Upstream commit 6ed159e499bc2ebedf94c9086244220824e71672 ] + +The alias prefix for ovl_2l (2 layer overlay) is "ovl-2l", not "ovl_2l". + +Fix this. + +Fixes: 7e07d3322de2 ("arm64: dts: mediatek: mt8186: Add display nodes") +Signed-off-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20231130074032.913511-4-wenst@chromium.org +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/mediatek/mt8186.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi +index df0c04f2ba1d..021397671099 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi +@@ -22,7 +22,7 @@ / { + + aliases { + ovl0 = &ovl0; +- ovl_2l0 = &ovl_2l0; ++ ovl-2l0 = &ovl_2l0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-mediatek-mt8195-revise-vdosys-rdma-node-na.patch b/queue-6.7/arm64-dts-mediatek-mt8195-revise-vdosys-rdma-node-na.patch new file mode 100644 index 00000000000..e697c073df7 --- /dev/null +++ b/queue-6.7/arm64-dts-mediatek-mt8195-revise-vdosys-rdma-node-na.patch @@ -0,0 +1,131 @@ +From da64b0e3c498976e4b69ec6ab4a3ab05bb4aae35 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Oct 2023 17:48:39 +0800 +Subject: arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name + +From: Moudy Ho + +[ Upstream commit 52f4a10f2a860402c130c5c21d055e721d63a7e9 ] + +DMA-related nodes have their own standardized naming. Therefore, +the MT8195 VDOSYS RDMA has been unified and corrected. +Additionally, these modifications will facilitate the further +integration of bindings. + +Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1") +Signed-off-by: Moudy Ho +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++-------- + 1 file changed, 16 insertions(+), 8 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi +index e0ac2e9f5b72..6708c4d21abf 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi +@@ -2873,7 +2873,7 @@ larb3: larb@1c103000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + +- vdo1_rdma0: rdma@1c104000 { ++ vdo1_rdma0: dma-controller@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = ; +@@ -2881,9 +2881,10 @@ vdo1_rdma0: rdma@1c104000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma1: rdma@1c105000 { ++ vdo1_rdma1: dma-controller@1c105000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + interrupts = ; +@@ -2891,9 +2892,10 @@ vdo1_rdma1: rdma@1c105000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma2: rdma@1c106000 { ++ vdo1_rdma2: dma-controller@1c106000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + interrupts = ; +@@ -2901,9 +2903,10 @@ vdo1_rdma2: rdma@1c106000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma3: rdma@1c107000 { ++ vdo1_rdma3: dma-controller@1c107000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + interrupts = ; +@@ -2911,9 +2914,10 @@ vdo1_rdma3: rdma@1c107000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma4: rdma@1c108000 { ++ vdo1_rdma4: dma-controller@1c108000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + interrupts = ; +@@ -2921,9 +2925,10 @@ vdo1_rdma4: rdma@1c108000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma5: rdma@1c109000 { ++ vdo1_rdma5: dma-controller@1c109000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + interrupts = ; +@@ -2931,9 +2936,10 @@ vdo1_rdma5: rdma@1c109000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma6: rdma@1c10a000 { ++ vdo1_rdma6: dma-controller@1c10a000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + interrupts = ; +@@ -2941,9 +2947,10 @@ vdo1_rdma6: rdma@1c10a000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; ++ #dma-cells = <1>; + }; + +- vdo1_rdma7: rdma@1c10b000 { ++ vdo1_rdma7: dma-controller@1c10b000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + interrupts = ; +@@ -2951,6 +2958,7 @@ vdo1_rdma7: rdma@1c10b000 { + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; ++ #dma-cells = <1>; + }; + + merge1: vpp-merge@1c10c000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-acer-aspire1-correct-audio-codec-defi.patch b/queue-6.7/arm64-dts-qcom-acer-aspire1-correct-audio-codec-defi.patch new file mode 100644 index 00000000000..0c3f0ae9031 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-acer-aspire1-correct-audio-codec-defi.patch @@ -0,0 +1,64 @@ +From a8eb37975638c0758b8853a4659b3a3121c56886 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 16:48:11 +0500 +Subject: arm64: dts: qcom: acer-aspire1: Correct audio codec definition + +From: Nikita Travkin + +[ Upstream commit feec9f0add432a867f23e29afcd2f7088889b8e2 ] + +When initially added, a mistake was made in the definition of the codec. + +Despite the fact that the DMIC line is connected on the side of the +codec chip, and relevant passive components, including 0-ohm resistors +connecting the dmics, are present, the dmic line is still cut in +another place on the board, which was overlooked. + +Correct this by replacing the dmic configuration with a comment +describing this hardware detail. + +While at it, also add missing regulators definitions. This is not a +functional change as all the relevant regulators were already added via +the other rail supplies. + +Fixes: 4a9f8f8f2ada ("arm64: dts: qcom: Add Acer Aspire 1") +Signed-off-by: Nikita Travkin +Link: https://lore.kernel.org/r/20231205-aspire1-sound-v2-2-443b7ac0a06f@trvn.ru +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + .../arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +index dbb48934d499..3342cb048038 100644 +--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts ++++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +@@ -209,9 +209,22 @@ alc5682: codec@1a { + AVDD-supply = <&vreg_l15a_1p8>; + MICVDD-supply = <®_codec_3p3>; + VBAT-supply = <®_codec_3p3>; ++ DBVDD-supply = <&vreg_l15a_1p8>; ++ LDO1-IN-supply = <&vreg_l15a_1p8>; ++ ++ /* ++ * NOTE: The board has a path from this codec to the ++ * DMIC microphones in the lid, however some of the option ++ * resistors are absent and the microphones are connected ++ * to the SoC instead. ++ * ++ * If the resistors were to be changed by the user to ++ * connect the codec, the following could be used: ++ * ++ * realtek,dmic1-data-pin = <1>; ++ * realtek,dmic1-clk-pin = <1>; ++ */ + +- realtek,dmic1-data-pin = <1>; +- realtek,dmic1-clk-pin = <1>; + realtek,jd-src = <1>; + }; + }; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch b/queue-6.7/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch new file mode 100644 index 00000000000..6cabce24dc7 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch @@ -0,0 +1,41 @@ +From 3e346a852970c6f9f5bf4f6604e19e635c2110fd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 23:08:05 +0800 +Subject: arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK + +From: Chukun Pan + +[ Upstream commit 5c0dbe8b058436ad5daecb19c60869f832607ea3 ] + +The downstream QSDK kernel [1] and GCC_USB1_MOCK_UTMI_CLK are both 24MHz. +Adjust GCC_USB0_MOCK_UTMI_CLK to 24MHz to avoid the following error: + +clk: couldn't set gcc_usb0_mock_utmi_clk clk rate to 20000000 (-22), current rate: 24000000 + +1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/486c8485f59 + +Fixes: 5726079cd486 ("arm64: dts: ipq6018: Use reference clock to set dwc3 period") +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20231218150805.1228160-1-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index e59b9df96c7e..0b1330b521df 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -557,7 +557,7 @@ usb3: usb@8af8800 { + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, +- <20000000>; ++ <24000000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-qrb2210-rb1-use-usb-host-mode.patch b/queue-6.7/arm64-dts-qcom-qrb2210-rb1-use-usb-host-mode.patch new file mode 100644 index 00000000000..7182fa16a8d --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-qrb2210-rb1-use-usb-host-mode.patch @@ -0,0 +1,45 @@ +From 6bb67aa6e3bbf58b426455a93a77c1560422375c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Oct 2023 12:58:00 +0100 +Subject: arm64: dts: qcom: qrb2210-rb1: use USB host mode + +From: Caleb Connolly + +[ Upstream commit e0cee8dc6757f9f18718eec553be9fffa503e103 ] + +The default for the QCM2290 platform that this board is based on is OTG +mode, however the role detection logic is not hooked up for this board +and the dwc3 driver is configured to not allow role switching from +userspace. + +Force this board to host mode as this is the preferred usecase until we +get role switching hooked up. + +Fixes: e18771961336 ("arm64: dts: qcom: Add initial QTI RB1 device tree") +Signed-off-by: Caleb Connolly +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231025-b4-rb1-usb-host-v1-1-522616c575ef@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index 94885b9c21c8..fd38a6278f2f 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -415,6 +415,10 @@ &usb_qmpphy { + status = "okay"; + }; + ++&usb_dwc3 { ++ dr_mode = "host"; ++}; ++ + &usb_hsphy { + vdd-supply = <&pm2250_l12>; + vdda-pll-supply = <&pm2250_l13>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-qrb4210-rb2-don-t-force-usb-periphera.patch b/queue-6.7/arm64-dts-qcom-qrb4210-rb2-don-t-force-usb-periphera.patch new file mode 100644 index 00000000000..82fed433439 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-qrb4210-rb2-don-t-force-usb-periphera.patch @@ -0,0 +1,41 @@ +From c3612d86c038910d8ccfaa7cae9aeccc0374a843 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 Oct 2023 11:46:58 +0100 +Subject: arm64: dts: qcom: qrb4210-rb2: don't force usb peripheral mode + +From: Caleb Connolly + +[ Upstream commit 27c2ca90e2f34cd3c4849af996e1a96a69e700d3 ] + +The rb2 only has a single USB controller, it can be switched between a +type-c port and an internal USB hub via a DIP switch. Until dynamic +role switching is available it's preferable to put the USB controller +in host mode so that the type-A ports and ethernet are available. + +Signed-off-by: Caleb Connolly +Reviewed-by: Vladimir Zapolskiy +Fixes: eaa53a85748d ("arm64: dts: qcom: qrb4210-rb2: Enable USB node") +Reviewed-by: Konrad Dybcio +Reviewed-by: Bryan O'Donoghue +Link: https://lore.kernel.org/r/20231010-caleb-rb2-host-mode-v1-1-b057d443cd62@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index a7278a9472ed..9738c0dacd58 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -518,7 +518,6 @@ &usb { + + &usb_dwc3 { + maximum-speed = "super-speed"; +- dr_mode = "peripheral"; + }; + + &usb_hsphy { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch b/queue-6.7/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch new file mode 100644 index 00000000000..98ffffa118f --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch @@ -0,0 +1,42 @@ +From decc351e9b3dd31e9075bfba5f35c05bc7d10428 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 10:46:23 +0100 +Subject: arm64: dts: qcom: qrb5165-rb5: correct LED panic indicator + +From: Krzysztof Kozlowski + +[ Upstream commit dc6b5562acbac0285ab3b2dad23930b6434bdfc6 ] + +There is no "panic-indicator" default trigger but a property with that +name: + + qrb5165-rb5.dtb: leds: led-user4: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) + +Fixes: b5cbd84e499a ("arm64: dts: qcom: qrb5165-rb5: Add onboard LED support") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Manivannan Sadhasivam +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231111094623.12476-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +index c8cd40a462a3..f9464caddacc 100644 +--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts ++++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +@@ -64,8 +64,8 @@ led-user4 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; + default-state = "off"; ++ panic-indicator; + }; + + led-wlan { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sa8775p-fix-usb-wakeup-interrupt-type.patch b/queue-6.7/arm64-dts-qcom-sa8775p-fix-usb-wakeup-interrupt-type.patch new file mode 100644 index 00000000000..169fc488a7a --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sa8775p-fix-usb-wakeup-interrupt-type.patch @@ -0,0 +1,67 @@ +From 7d9b541a8dd6589613a935b3d014f90f9d39e6fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 17:43:22 +0100 +Subject: arm64: dts: qcom: sa8775p: fix USB wakeup interrupt types + +From: Johan Hovold + +[ Upstream commit 0984bc0165f7c5203dfffe8cdb5186995f628a80 ] + +The DP/DM wakeup interrupts are edge triggered and which edge to trigger +on depends on use-case and whether a Low speed or Full/High speed device +is connected. + +Note that only triggering on rising edges can be used to detect resume +events but not disconnect events. + +Fixes: de1001525c1a ("arm64: dts: qcom: sa8775p: add USB nodes") +Cc: Shazad Hussain +Signed-off-by: Johan Hovold +Reviewed-by: Andrew Halaney +Link: https://lore.kernel.org/r/20231120164331.8116-3-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi +index 5e1d6756f245..1274dcda2256 100644 +--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi ++++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi +@@ -1610,8 +1610,8 @@ usb_0: usb@a6f8800 { + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 14 IRQ_TYPE_EDGE_RISING>, +- <&pdc 15 IRQ_TYPE_EDGE_RISING>, ++ <&pdc 14 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", +@@ -1697,8 +1697,8 @@ usb_1: usb@a8f8800 { + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 8 IRQ_TYPE_EDGE_RISING>, +- <&pdc 7 IRQ_TYPE_EDGE_RISING>, ++ <&pdc 8 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 7 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", +@@ -1760,8 +1760,8 @@ usb_2: usb@a4f8800 { + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 10 IRQ_TYPE_EDGE_RISING>, +- <&pdc 9 IRQ_TYPE_EDGE_RISING>; ++ <&pdc 10 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 9 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sa8775p-make-watchdog-bark-interrupt-.patch b/queue-6.7/arm64-dts-qcom-sa8775p-make-watchdog-bark-interrupt-.patch new file mode 100644 index 00000000000..1ea511f4e53 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sa8775p-make-watchdog-bark-interrupt-.patch @@ -0,0 +1,42 @@ +From 32f4667826d662cec918de3ba698e8635de88f7e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:33 -0800 +Subject: arm64: dts: qcom: sa8775p: Make watchdog bark interrupt edge + triggered + +From: Douglas Anderson + +[ Upstream commit 48d5cf4772ec6268853158d9ffc54612e988ebe6 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 09b701b89a76 ("arm64: dts: qcom: sa8775p: add the watchdog node") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Reviewed-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20231106144335.v2.6.I909b7c4453d7b7fb0db4b6e49aa21666279d827d@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi +index b6a93b11cbbd..5e1d6756f245 100644 +--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi ++++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi +@@ -2181,7 +2181,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; + reg = <0x0 0x17c10000 0x0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + memtimer: timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..8e787d9a53b --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,58 @@ +From b9707f221e0de1854d13912677d8e9578c41539c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:28 -0800 +Subject: arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 7ac90b4cf107a3999b30844d7899e0331686b33b ] + +On sc7180 when the watchdog timer fires your logs get filled with: + watchdog0: pretimeout event + watchdog0: pretimeout event + watchdog0: pretimeout event + ... + watchdog0: pretimeout event + +If you're using console-ramoops to debug crashes the above gets quite +annoying since it blows away any other log messages that might have +been there. + +The issue is that the "bark" interrupt (AKA the "pretimeout" +interrupt) remains high until the watchdog is pet. Since we've got +things configured as "level" triggered we'll keep getting interrupted +over and over. + +Let's switch to edge triggered. Now we'll get one interrupt when the +"bark" interrupt goes off and won't get another one until the "bark" +interrupt is cleared and asserts again. + +This matches how many older Qualcomm SoCs have things configured. + +Fixes: 28cc13e4060c ("arm64: dts: qcom: sc7180: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.1.Ic7577567baff921347d423b722de8b857602efb1@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi +index 11f353d416b4..c0365832c315 100644 +--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi +@@ -3576,7 +3576,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch b/queue-6.7/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch new file mode 100644 index 00000000000..b6b49336038 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch @@ -0,0 +1,44 @@ +From 127fd247cad390278a1ca174b90b53d7353fb6c4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 13:12:53 +0100 +Subject: arm64: dts: qcom: sc7280: Fix up GPU SIDs + +From: Konrad Dybcio + +[ Upstream commit 94085049fdad7a36fe14dd55e72e712fe55d6bca ] + +GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). +On platforms that support it (in firmware), it is necessary to +describe that link, or Adreno register access will hang the board. + +The current settings are functionally identical, *but* due to what is +likely hardcoded security policies, the secure firmware rejects them, +resulting in the board hanging. To avoid that, alter the settings such +that SID 0 and 1 are described separately. + +Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230926-topic-a643-v2-2-06fa3d899c0a@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 6d01262199dc..ea183eadf700 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -2598,7 +2598,8 @@ gpu: gpu@3d00000 { + "cx_mem", + "cx_dbgc"; + interrupts = ; +- iommus = <&adreno_smmu 0 0x401>; ++ iommus = <&adreno_smmu 0 0x400>, ++ <&adreno_smmu 1 0x400>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch b/queue-6.7/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch new file mode 100644 index 00000000000..c1d85e5d4a5 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch @@ -0,0 +1,43 @@ +From 99228996e313483b443405b8e9e1a5be021726a6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 17:43:25 +0100 +Subject: arm64: dts: qcom: sc7280: fix usb_2 wakeup interrupt types + +From: Johan Hovold + +[ Upstream commit 24f8aba9a7c77c7e9d814a5754798e8346c7dd28 ] + +The DP/DM wakeup interrupts are edge triggered and which edge to trigger +on depends on use-case and whether a Low speed or Full/High speed device +is connected. + +Note that only triggering on rising edges can be used to detect resume +events but not disconnect events. + +Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20231120164331.8116-6-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 1a3db2579806..1dac0b10582e 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3428,8 +3428,8 @@ usb_2: usb@8cf8800 { + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 12 IRQ_TYPE_EDGE_RISING>, +- <&pdc 13 IRQ_TYPE_EDGE_RISING>; ++ <&pdc 12 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 13 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..b1582cf0b94 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From cf1785b8d40640a840e0f1595a3eb86b9a621409 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:29 -0800 +Subject: arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 6897fac411db7b43243f67d4fd4d3f95abf7f656 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 0e51f883daa9 ("arm64: dts: qcom: sc7280: Add APSS watchdog node") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.2.I11f77956d2492c88aca0ef5462123f225caf4fb4@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 66f1eb83cca7..6d01262199dc 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -5222,7 +5222,7 @@ watchdog: watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + status = "reserved"; /* Owned by Gunyah hyp */ + }; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch b/queue-6.7/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch new file mode 100644 index 00000000000..b0fbaa21962 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch @@ -0,0 +1,37 @@ +From 07e18a25ca98c1b7c3e956079a217f7bcf8086f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 13:12:54 +0100 +Subject: arm64: dts: qcom: sc7280: Mark Adreno SMMU as DMA coherent + +From: Konrad Dybcio + +[ Upstream commit 31edad478534186a2718be9206ce7b19f2735f6e ] + +The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such, +mark the GPU one as well. + +Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") +Reviewed-by: Akhil P Oommen +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230926-topic-a643-v2-3-06fa3d899c0a@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index ea183eadf700..1a3db2579806 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -2773,6 +2773,7 @@ adreno_smmu: iommu@3da0000 { + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; ++ dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch b/queue-6.7/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch new file mode 100644 index 00000000000..c363f93f1c4 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch @@ -0,0 +1,44 @@ +From 48b6206c3d3eb8f5bf13d97fc844c164e2e01863 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 15:38:33 +0100 +Subject: arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent + +From: Konrad Dybcio + +[ Upstream commit 827f5fc8d912203c1f971e47d61130b13c6820ba ] + +The SDHCI hosts on SC7280 are cache-coherent, just like on most fairly +recent Qualcomm SoCs. Mark them as such. + +Fixes: 298c81a7d44f ("arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-7280_dmac_sdhci-v1-1-97af7efd64a1@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 1dac0b10582e..f7f616906f6f 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -974,6 +974,7 @@ sdhc_1: mmc@7c4000 { + + bus-width = <8>; + supports-cqe; ++ dma-coherent; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; +@@ -3331,6 +3332,7 @@ sdhc_2: mmc@8804000 { + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; ++ dma-coherent; + + qcom,dll-config = <0x0007642c>; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8180x-fix-up-pcie-nodes.patch b/queue-6.7/arm64-dts-qcom-sc8180x-fix-up-pcie-nodes.patch new file mode 100644 index 00000000000..3a2c9f431d8 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8180x-fix-up-pcie-nodes.patch @@ -0,0 +1,55 @@ +From 0f7878e03e2c8ae3772776f9aafa2b7562b3205c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 14:05:06 +0100 +Subject: arm64: dts: qcom: sc8180x: Fix up PCIe nodes + +From: Konrad Dybcio + +[ Upstream commit 78403b37f6770441f80a78d13772394731afe055 ] + +Duplicated clock output names cause probe errors and wrong clocks cause +hardware not to work. Fix such issues. + +Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231219-topic-8180_pcie-v1-1-c2acbba4723c@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi +index 59ab5428348d..b5eb84287870 100644 +--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi +@@ -1762,7 +1762,7 @@ pcie0_phy: phy@1c06000 { + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, +- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, ++ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", +@@ -1860,7 +1860,7 @@ pcie3_phy: phy@1c0c000 { + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, +- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, ++ <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", +@@ -2066,7 +2066,7 @@ pcie2_phy: phy@1c1c000 { + "refgen", + "pipe"; + #clock-cells = <0>; +- clock-output-names = "pcie_3_pipe_clk"; ++ clock-output-names = "pcie_2_pipe_clk"; + + #phy-cells = <0>; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8180x-mark-pcie-hosts-cache-coheren.patch b/queue-6.7/arm64-dts-qcom-sc8180x-mark-pcie-hosts-cache-coheren.patch new file mode 100644 index 00000000000..82e99acf0b1 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8180x-mark-pcie-hosts-cache-coheren.patch @@ -0,0 +1,59 @@ +From f43c1ceb90005dd22c4a2eb8bdfd30c9e93378da Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 19:40:21 +0100 +Subject: arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent + +From: Konrad Dybcio + +[ Upstream commit 45e8c72712345263208f7c94f334fa718634f557 ] + +The PCIe controllers on 8180 are cache-coherent. Mark them as such. + +Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231219-topic-8180_pcie_dmac-v1-1-5d00fc1b23fd@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8180x.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi +index a34f438ef2d9..59ab5428348d 100644 +--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi +@@ -1751,6 +1751,7 @@ pcie0: pci@1c00000 { + + phys = <&pcie0_phy>; + phy-names = "pciephy"; ++ dma-coherent; + + status = "disabled"; + }; +@@ -1848,6 +1849,7 @@ pcie3: pci@1c08000 { + + phys = <&pcie3_phy>; + phy-names = "pciephy"; ++ dma-coherent; + + status = "disabled"; + }; +@@ -1946,6 +1948,7 @@ pcie1: pci@1c10000 { + + phys = <&pcie1_phy>; + phy-names = "pciephy"; ++ dma-coherent; + + status = "disabled"; + }; +@@ -2044,6 +2047,7 @@ pcie2: pci@1c18000 { + + phys = <&pcie2_phy>; + phy-names = "pciephy"; ++ dma-coherent; + + status = "disabled"; + }; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8180x-primus-fix-hall_int-polarity.patch b/queue-6.7/arm64-dts-qcom-sc8180x-primus-fix-hall_int-polarity.patch new file mode 100644 index 00000000000..e9fa8db004d --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8180x-primus-fix-hall_int-polarity.patch @@ -0,0 +1,41 @@ +From c853ab2c489e57a411177592aafc68584b14d48f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 16:11:10 -0800 +Subject: arm64: dts: qcom: sc8180x-primus: Fix HALL_INT polarity + +From: Bjorn Andersson + +[ Upstream commit 1aaa08e8de365cce59203541cafadb5053b1ec1a ] + +The hall sensor interrupt on the Primus is active low, which means that +with the current configuration the device attempts to suspend when the +LID is open. + +Fix the polarity of the HALL_INT GPIO to avoid this. + +Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") +Signed-off-by: Bjorn Andersson +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231130-sc8180x-primus-lid-polarity-v1-1-da917b59604b@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +index fd2fab4895b3..a40ef23a2a4f 100644 +--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts ++++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +@@ -43,7 +43,7 @@ gpio-keys { + pinctrl-0 = <&hall_int_active_state>; + + lid-switch { +- gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; ++ gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch b/queue-6.7/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch new file mode 100644 index 00000000000..858892fb0d0 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch @@ -0,0 +1,41 @@ +From b079510e778cbfb805dcdb71d4229f21333d90a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:34 -0800 +Subject: arm64: dts: qcom: sc8280xp: Make watchdog bark interrupt edge + triggered + +From: Douglas Anderson + +[ Upstream commit 6c4a9c7ea486da490400c84ba2768c90d228c283 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.7.I1c8ab71570f6906fd020decb80675f05fbe1fe74@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +index cad59af7ccef..b8081513176a 100644 +--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +@@ -4225,7 +4225,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-add-missing-camera-led-.patch b/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-add-missing-camera-led-.patch new file mode 100644 index 00000000000..9d2966e2f91 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-add-missing-camera-led-.patch @@ -0,0 +1,53 @@ +From d287a3278949307a9cada1a2e21097b6e81fde3a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 3 Oct 2023 11:36:47 +0200 +Subject: arm64: dts: qcom: sc8280xp-x13s: add missing camera LED pin config + +From: Johan Hovold + +[ Upstream commit a3457cc5bc30ad053c90ae9f14e9b7723d204a98 ] + +Add the missing pin configuration for the recently added camera +indicator LED. + +Fixes: 1c63dd1c5fda ("arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED") +Cc: Konrad Dybcio +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20231003093647.3840-1-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +index 6a4c6cc19c09..f2055899ae7a 100644 +--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts ++++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +@@ -82,6 +82,9 @@ switch-lid { + leds { + compatible = "gpio-leds"; + ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cam_indicator_en>; ++ + led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; +@@ -1278,6 +1281,13 @@ hstp-sw-ctrl-pins { + }; + }; + ++ cam_indicator_en: cam-indicator-en-state { ++ pins = "gpio28"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-use-the-correct-dp-phy-.patch b/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-use-the-correct-dp-phy-.patch new file mode 100644 index 00000000000..30557a35589 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sc8280xp-x13s-use-the-correct-dp-phy-.patch @@ -0,0 +1,39 @@ +From 985a8bb88c39229b312a9577ac080e43a69c438a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 29 Sep 2023 18:02:57 +0200 +Subject: arm64: dts: qcom: sc8280xp-x13s: Use the correct DP PHY compatible + +From: Konrad Dybcio + +[ Upstream commit 0cd080dd6d08817c9980d2069197b066636b0f23 ] + +The DP PHY needs different settings when an eDP display is used. +Make sure these apply on the X13s. + +FWIW +I could not notice any user-facing change stemming from this commit. + +Fixes: f48c70b111b4 ("arm64: dts: qcom: sc8280xp-x13s: enable eDP display") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230929-topic-x13s_edpphy-v1-1-ce59f9eb4226@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +index 38edaf51aa34..6a4c6cc19c09 100644 +--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts ++++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +@@ -601,6 +601,7 @@ mdss0_dp3_out: endpoint { + }; + + &mdss0_dp3_phy { ++ compatible = "qcom,sc8280xp-edp-phy"; + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch b/queue-6.7/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch new file mode 100644 index 00000000000..4f31e819f9d --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch @@ -0,0 +1,41 @@ +From 17fd88982dd3704d3a72a62ae3fed4c26266d7c4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 10:56:16 +0100 +Subject: arm64: dts: qcom: sdm845-db845c: correct LED panic indicator + +From: Krzysztof Kozlowski + +[ Upstream commit 0c90c75e663246203a2b7f6dd9e08a110f4c3c43 ] + +There is no "panic-indicator" default trigger but a property with that +name: + + sdm845-db845c.dtb: leds: led-0: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) + +Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231111095617.16496-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +index c7eba6c491be..7e7bf3fb3be6 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts ++++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +@@ -67,8 +67,8 @@ led-0 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; + default-state = "off"; ++ panic-indicator; + }; + + led-1 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..c8c40e0eb03 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 0200f1a3bf99395ae59e37f8cb00a70955631327 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:30 -0800 +Subject: arm64: dts: qcom: sdm845: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 263b348499454f38d36b9442c3cf9279c571bb54 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 36c436b03c58 ("arm64: dts: qcom: sdm845: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.3.I16675ebe5517c68453a1bd7f4334ff885f806c03@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi +index bf5e6eb9d313..9648505644ff 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -5088,7 +5088,7 @@ watchdog@17980000 { + compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; + reg = <0 0x17980000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + apss_shared: mailbox@17990000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm6125-add-interrupts-to-dwc3-usb-con.patch b/queue-6.7/arm64-dts-qcom-sm6125-add-interrupts-to-dwc3-usb-con.patch new file mode 100644 index 00000000000..6fe5359a25b --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm6125-add-interrupts-to-dwc3-usb-con.patch @@ -0,0 +1,46 @@ +From 4e6b937e1ae87e622ca3201a25839485b2bbf141 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 17:42:28 +0100 +Subject: arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller + +From: Krzysztof Kozlowski + +[ Upstream commit 67e4656f4487b95a39e45884c99235f62ebfaa47 ] + +Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor +code of Trinket DTSI from Xiaomi Laurel device, to fix dtbs_check +warnings: + + sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'interrupt-names' is a required property + sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'oneOf' conditional failed, one must be fixed: + 'interrupts' is a required property + 'interrupts-extended' is a required property + +Signed-off-by: Krzysztof Kozlowski +Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") +Reviewed-by: Marijn Suijten +Link: https://lore.kernel.org/r/20231111164229.63803-5-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi +index eb07eca3a48d..1dd3a4056e26 100644 +--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi +@@ -1185,6 +1185,10 @@ usb3: usb@4ef8800 { + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + ++ interrupts = , ++ ; ++ interrupt-names = "hs_phy_irq", "ss_phy_irq"; ++ + power-domains = <&gcc USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..4571241d2f4 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From b80d680f36fa44349a7ec91adc4cae9174cf0726 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:35 -0800 +Subject: arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 5b84bb2b8d86595544fc8272364b0f1a34b68a4f ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.8.Ic1d4402e99c70354d501ccd98105e908a902f671@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi +index 8fd6f4d03490..6464e144c228 100644 +--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi +@@ -2524,7 +2524,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm6375-fix-usb-wakeup-interrupt-types.patch b/queue-6.7/arm64-dts-qcom-sm6375-fix-usb-wakeup-interrupt-types.patch new file mode 100644 index 00000000000..778c00ff2bf --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm6375-fix-usb-wakeup-interrupt-types.patch @@ -0,0 +1,43 @@ +From 76ac014a70d1f754ea933151b068d1c71423f384 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 17:43:29 +0100 +Subject: arm64: dts: qcom: sm6375: fix USB wakeup interrupt types + +From: Johan Hovold + +[ Upstream commit 41952be6661b20f56c2c5b06c431880dd975b747 ] + +The DP/DM wakeup interrupts are edge triggered and which edge to trigger +on depends on use-case and whether a Low speed or Full/High speed device +is connected. + +Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") +Cc: stable@vger.kernel.org # 6.2 +Cc: Konrad Dybcio +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20231120164331.8116-10-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Stable-dep-of: d3246a0cf43f ("arm64: dts: qcom: sm6375: Hook up MPM") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm6375.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi +index e7ff55443da7..b479f3d9a3a8 100644 +--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi +@@ -1362,8 +1362,8 @@ usb_1: usb@4ef8800 { + + interrupts = , + , +- , +- ; ++ , ++ ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm6375-hook-up-mpm.patch b/queue-6.7/arm64-dts-qcom-sm6375-hook-up-mpm.patch new file mode 100644 index 00000000000..d6272c4cab1 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm6375-hook-up-mpm.patch @@ -0,0 +1,115 @@ +From 961f39ad85c8c9fa83464e03aedd6276aed05c52 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 01:01:08 +0100 +Subject: arm64: dts: qcom: sm6375: Hook up MPM + +From: Konrad Dybcio + +[ Upstream commit d3246a0cf43fd24a1986163284edd2389143809d ] + +Add a node for MPM and wire it up on consumers that use it. This also +fixes a very bad and sad assumption I made when initially porting this +SoC that the downstream MPM-TLMM mappings were 1-1. That apparently +changed some time ago, so with this patch the MPM consumers will actually +be hooked up to the correct interrupt lines. + +Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231215-topic-mpm_dt-v1-1-c6636fc75ce3@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm6375.dtsi | 41 +++++++++++++++++++++++----- + 1 file changed, 34 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi +index b479f3d9a3a8..e56f7ea4ebc6 100644 +--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi +@@ -311,6 +311,25 @@ scm { + }; + }; + ++ mpm: interrupt-controller { ++ compatible = "qcom,mpm"; ++ qcom,rpm-msg-ram = <&apss_mpm>; ++ interrupts = ; ++ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ #power-domain-cells = <0>; ++ interrupt-parent = <&intc>; ++ qcom,mpm-pin-count = <96>; ++ qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */ ++ <12 422>, /* DWC3 ss_phy_irq */ ++ <86 183>, /* MPM wake, SPMI */ ++ <89 314>, /* TSENS0 0C */ ++ <90 315>, /* TSENS1 0C */ ++ <93 164>, /* DWC3 dm_hs_phy_irq */ ++ <94 165>; /* DWC3 dp_hs_phy_irq */ ++ }; ++ + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ +@@ -486,6 +505,7 @@ CPU_PD7: power-domain-cpu7 { + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; ++ power-domains = <&mpm>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; +@@ -808,7 +828,7 @@ tlmm: pinctrl@500000 { + reg = <0 0x00500000 0 0x800000>; + interrupts = ; + gpio-ranges = <&tlmm 0 0 157>; +- /* TODO: Hook up MPM as wakeup-parent when it's there */ ++ wakeup-parent = <&mpm>; + interrupt-controller; + gpio-controller; + #interrupt-cells = <2>; +@@ -930,7 +950,7 @@ spmi_bus: spmi@1c40000 { + <0 0x01c0a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; +- interrupts = ; ++ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; +@@ -962,8 +982,15 @@ tsens1: thermal-sensor@4413000 { + }; + + rpm_msg_ram: sram@45f0000 { +- compatible = "qcom,rpm-msg-ram"; ++ compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0 0x045f0000 0 0x7000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x0 0x045f0000 0x7000>; ++ ++ apss_mpm: sram@1b8 { ++ reg = <0x1b8 0x48>; ++ }; + }; + + sram@4690000 { +@@ -1360,10 +1387,10 @@ usb_1: usb@4ef8800 { + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + +- interrupts = , +- , +- , +- ; ++ interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, ++ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, ++ <&mpm 93 IRQ_TYPE_EDGE_BOTH>, ++ <&mpm 94 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch b/queue-6.7/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch new file mode 100644 index 00000000000..ef952922bc7 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch @@ -0,0 +1,70 @@ +From 13072f8348069493f1183cd355cfde0916065fef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 19:40:35 +0200 +Subject: arm64: dts: qcom: sm8150-hdk: fix SS USB regulators + +From: Dmitry Baryshkov + +[ Upstream commit a509adf05b2aac31b22781f5aa09e4768a5b6c39 ] + +The SM8150-HDK uses two different regulators to power up SuperSpeed USB +PHYs. The L5A regulator is used for the second USB host, while the first +(OTG) USB host uses different regulator, L18A. Fix the regulator for the +usb_1 QMPPHY and (to remove possible confusion) drop the +usb_ss_dp_core_1/_2 labels. + +Fixes: 0ab1b2d10afe ("arm64: dts: qcom: add sm8150 hdk dts") +Reviewed-by: Konrad Dybcio +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20231215174152.315403-4-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +index bb161b536da4..f4c6e1309a7e 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts ++++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +@@ -127,8 +127,6 @@ vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: +- vdda_usb_ss_dp_core_1: +- vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { +@@ -210,6 +208,12 @@ vreg_l17a_3p0: ldo17 { + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; ++ ++ vreg_l18a_0p8: ldo18 { ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ regulator-initial-mode = ; ++ }; + }; + + regulators-1 { +@@ -445,13 +449,13 @@ &usb_2_hsphy { + &usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; ++ vdda-pll-supply = <&vreg_l18a_0p8>; + }; + + &usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; ++ vdda-pll-supply = <&vreg_l5a_0p875>; + }; + + &usb_1 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8150-make-dispcc-cast-minimal-vote-.patch b/queue-6.7/arm64-dts-qcom-sm8150-make-dispcc-cast-minimal-vote-.patch new file mode 100644 index 00000000000..d7dc1a94f9e --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8150-make-dispcc-cast-minimal-vote-.patch @@ -0,0 +1,38 @@ +From 396f7a90c18df7c9982b42a3a01ff1f69f9f8f7a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 19:40:33 +0200 +Subject: arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX + +From: Dmitry Baryshkov + +[ Upstream commit 617de4ce7b1c4b41c1316e493d4717cd2f208def ] + +Add required-opps property to the display clock controller. This makes +it cast minimal vote on the MMCX lane and prevents further 'clock stuck' +errors when enabling the display. + +Fixes: 2ef3bb17c45c ("arm64: dts: qcom: sm8150: Add DISPCC node") +Acked-by: Konrad Dybcio +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20231215174152.315403-2-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi +index ad4fab61222b..0e1aa8675879 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi +@@ -3932,6 +3932,7 @@ dispcc: clock-controller@af00000 { + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SM8150_MMCX>; ++ required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..a493b49a77a --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From dce666cfe8ad6a70c51267e5401a71048e53c868 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:31 -0800 +Subject: arm64: dts: qcom: sm8150: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 9204e9a4099212c850e1703c374ef4538080825b ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: b094c8f8dd2a ("arm64: dts: qcom: sm8150: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.4.I23d0aa6c8f1fec5c26ad9b3c610df6f4c5392850@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi +index 97623af13464..ad4fab61222b 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi +@@ -4170,7 +4170,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch b/queue-6.7/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..dc138974af4 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From ec8a18fb788e9de821ef7aec81ed614156cad815 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:32 -0800 +Subject: arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 735d80e2e8e5d073ae8b1fff8b1589ea284aa5af ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 46a4359f9156 ("arm64: dts: qcom: sm8250: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.5.I2910e7c10493d896841e9785c1817df9b9a58701@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi +index be970472f6c4..72db75ca7731 100644 +--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi +@@ -6018,7 +6018,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8350-fix-dma0-address.patch b/queue-6.7/arm64-dts-qcom-sm8350-fix-dma0-address.patch new file mode 100644 index 00000000000..d7ef641642e --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8350-fix-dma0-address.patch @@ -0,0 +1,42 @@ +From cc4b812bc501639cb0a034dc5c4093f2f37773e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 23:07:40 +0100 +Subject: arm64: dts: qcom: sm8350: Fix DMA0 address + +From: Nia Espera + +[ Upstream commit 01a9e9eb6cdbce175ddea3cbe1163daed6d54344 ] + +DMA0 node downstream is specified at 0x900000, so fix the typo. Without +this, enabling any i2c node using DMA0 causes a hang. + +Fixes: bc08fbf49bc8 ("arm64: dts: qcom: sm8350: Define GPI DMA engines") +Fixes: 41d6bca799b3 ("arm64: dts: qcom: sm8350: correct DMA controller unit address") +Reviewed-by: Konrad Dybcio +Signed-off-by: Nia Espera +Link: https://lore.kernel.org/r/20231111-nia-sm8350-for-upstream-v4-2-3a638b02eea5@igalia.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi +index b46236235b7f..1d597af15bb3 100644 +--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi +@@ -919,9 +919,9 @@ spi19: spi@894000 { + }; + }; + +- gpi_dma0: dma-controller@9800000 { ++ gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; +- reg = <0 0x09800000 0 0x60000>; ++ reg = <0 0x00900000 0 0x60000>; + interrupts = , + , + , +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8450-correct-tx-soundwire-clock.patch b/queue-6.7/arm64-dts-qcom-sm8450-correct-tx-soundwire-clock.patch new file mode 100644 index 00000000000..441fe835498 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8450-correct-tx-soundwire-clock.patch @@ -0,0 +1,43 @@ +From 26b5b382b0a00dd7efe0190761f94ecb3d0ce16c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 15:05:36 +0100 +Subject: arm64: dts: qcom: sm8450: correct TX Soundwire clock + +From: Krzysztof Kozlowski + +[ Upstream commit 20e886590a310665244a354e3b693b881544edec ] + +The TX Soundwire controller should take clock from TX macro codec, not +VA macro codec clock, otherwise the clock stays disabled. This looks +like a copy-paste issue, because the SC8280xp code uses here correctly +clock from TX macro. The VA macro clock is already consumed by TX macro +codec, thus it won't be disabled by this change. + +Fixes: 14341e76dbc7 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") +Reported-by: Neil Armstrong +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Neil Armstrong +Acked-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231129140537.161720-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi +index 1783fa78bdbc..dc904ccb3d6c 100644 +--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi +@@ -2309,7 +2309,7 @@ swr2: soundwire-controller@33b0000 { + ; + interrupt-names = "core", "wakeup"; + +- clocks = <&vamacro>; ++ clocks = <&txmacro>; + clock-names = "iface"; + label = "TX"; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8550-correct-tx-soundwire-clock.patch b/queue-6.7/arm64-dts-qcom-sm8550-correct-tx-soundwire-clock.patch new file mode 100644 index 00000000000..212b276e47d --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8550-correct-tx-soundwire-clock.patch @@ -0,0 +1,42 @@ +From 18c82ac499b59e3d0d2e43b11a5b952d3f0c1fb3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 15:05:37 +0100 +Subject: arm64: dts: qcom: sm8550: correct TX Soundwire clock + +From: Krzysztof Kozlowski + +[ Upstream commit ead0f132fc494b46fcd94788456f9b264fd631bb ] + +The TX Soundwire controller should take clock from TX macro codec, not +VA macro codec clock, otherwise the clock stays disabled. This looks +like a copy-paste issue, because the SC8280xp code uses here correctly +clock from TX macro. The VA macro clock is already consumed by TX macro +codec, thus it won't be disabled by this change. + +Fixes: 61b006389bb7 ("arm64: dts: qcom: sm8550: add Soundwire controllers") +Reported-by: Neil Armstrong +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20231129140537.161720-2-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index 7b9ddde0b2c9..09353b27bcad 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -2194,7 +2194,7 @@ swr2: soundwire-controller@6d30000 { + interrupts = , + ; + interrupt-names = "core", "wakeup"; +- clocks = <&lpass_vamacro>; ++ clocks = <&lpass_txmacro>; + clock-names = "iface"; + label = "TX"; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8550-fix-usb-wakeup-interrupt-types.patch b/queue-6.7/arm64-dts-qcom-sm8550-fix-usb-wakeup-interrupt-types.patch new file mode 100644 index 00000000000..88690a20cf5 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8550-fix-usb-wakeup-interrupt-types.patch @@ -0,0 +1,45 @@ +From 3a9713788a76dc15751acfc534ec49b735054e39 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 17:43:31 +0100 +Subject: arm64: dts: qcom: sm8550: fix USB wakeup interrupt types + +From: Johan Hovold + +[ Upstream commit 29d91ecf530a4ef0b7f94cb8cde07ed69731e45d ] + +The DP/DM wakeup interrupts are edge triggered and which edge to trigger +on depends on use-case and whether a Low speed or Full/High speed device +is connected. + +Note that only triggering on rising edges can be used to detect resume +events but not disconnect events. + +Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") +Cc: Abel Vesa +Signed-off-by: Johan Hovold +Reviewed-by: Abel Vesa +Link: https://lore.kernel.org/r/20231120164331.8116-12-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index 09353b27bcad..6c2b4da8e90a 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -2923,8 +2923,8 @@ usb_1: usb@a6f8800 { + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 15 IRQ_TYPE_EDGE_RISING>, +- <&pdc 14 IRQ_TYPE_EDGE_RISING>; ++ <&pdc 15 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8550-separate-out-x3-idle-state.patch b/queue-6.7/arm64-dts-qcom-sm8550-separate-out-x3-idle-state.patch new file mode 100644 index 00000000000..1118b75886d --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8550-separate-out-x3-idle-state.patch @@ -0,0 +1,54 @@ +From e32edc46f6660e18ad040ab439a895b82050037d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:12 +0100 +Subject: arm64: dts: qcom: sm8550: Separate out X3 idle state + +From: Konrad Dybcio + +[ Upstream commit 28b735232d5e16a34f98dbac1e7b5401c1c16d89 ] + +The X3 core has different entry/exit/residency time requirements than +the big cluster. Denote them to stop confusing the scheduler. + +Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-11-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index 6c2b4da8e90a..a3aba04e4c4a 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -300,6 +300,16 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + min-residency-us = <4791>; + local-timer-stop; + }; ++ ++ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { ++ compatible = "arm,idle-state"; ++ idle-state-name = "goldplus-rail-power-collapse"; ++ arm,psci-suspend-param = <0x40000004>; ++ entry-latency-us = <500>; ++ exit-latency-us = <1350>; ++ min-residency-us = <7480>; ++ local-timer-stop; ++ }; + }; + + domain-idle-states { +@@ -400,7 +410,7 @@ CPU_PD6: power-domain-cpu6 { + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; +- domain-idle-states = <&BIG_CPU_SLEEP_0>; ++ domain-idle-states = <&PRIME_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-qcom-sm8550-update-idle-state-time-require.patch b/queue-6.7/arm64-dts-qcom-sm8550-update-idle-state-time-require.patch new file mode 100644 index 00000000000..4b2d78d4eb6 --- /dev/null +++ b/queue-6.7/arm64-dts-qcom-sm8550-update-idle-state-time-require.patch @@ -0,0 +1,77 @@ +From 18f4d768b6d8877fc0e488d241e1d81bce6e8a53 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:13 +0100 +Subject: arm64: dts: qcom: sm8550: Update idle state time requirements + +From: Konrad Dybcio + +[ Upstream commit ad6556fb45d4ab91ad786a2025cbe2b0f2e6cf77 ] + +The idle state entry/exit/residency times differ from what shipped on +production devices, mostly being overly optimistic in entry times and +overly pessimistic in minimal residency times. Align them with +downstream sources. + +Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-12-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index a3aba04e4c4a..5cf813a579d5 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -285,9 +285,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; +- entry-latency-us = <800>; ++ entry-latency-us = <550>; + exit-latency-us = <750>; +- min-residency-us = <4090>; ++ min-residency-us = <6700>; + local-timer-stop; + }; + +@@ -296,8 +296,8 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; +- exit-latency-us = <1550>; +- min-residency-us = <4791>; ++ exit-latency-us = <1300>; ++ min-residency-us = <8136>; + local-timer-stop; + }; + +@@ -316,17 +316,17 @@ domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; +- entry-latency-us = <1050>; +- exit-latency-us = <2500>; +- min-residency-us = <5309>; ++ entry-latency-us = <750>; ++ exit-latency-us = <2350>; ++ min-residency-us = <9144>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c344>; +- entry-latency-us = <2700>; +- exit-latency-us = <3500>; +- min-residency-us = <13959>; ++ entry-latency-us = <2800>; ++ exit-latency-us = <4400>; ++ min-residency-us = <10150>; + }; + }; + }; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch b/queue-6.7/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch new file mode 100644 index 00000000000..319c99bcbe1 --- /dev/null +++ b/queue-6.7/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch @@ -0,0 +1,39 @@ +From 5be513523ad6eb3de0551fe009c77ca1693be400 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 10:32:25 +0100 +Subject: arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin + control + +From: Geert Uytterhoeven + +[ Upstream commit fc67495680f60e88bb8ca43421c1dd628928d581 ] + +The pin control description for the serial console was added, but not +enabled, due to missing pinctrl properties in the serial port device +node. + +Fixes: 7a8d590de8132853 ("arm64: dts: renesas: white-hawk-cpu: Add serial port pin control") +Signed-off-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/8a51516581cd71ecbfa174af9c7cebad1fc83c5b.1702459865.git.geert+renesas@glider.be +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +index bb4a5270f71b..913f70fe6c5c 100644 +--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +@@ -187,6 +187,9 @@ &extalr_clk { + }; + + &hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ + status = "okay"; + }; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-rockchip-fix-led-pinctrl-of-lubancat-1.patch b/queue-6.7/arm64-dts-rockchip-fix-led-pinctrl-of-lubancat-1.patch new file mode 100644 index 00000000000..7e34001310e --- /dev/null +++ b/queue-6.7/arm64-dts-rockchip-fix-led-pinctrl-of-lubancat-1.patch @@ -0,0 +1,38 @@ +From 0e1fe7cca133812cfa0986e47b8e24cd023b7668 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Dec 2023 08:50:55 +0800 +Subject: arm64: dts: rockchip: Fix led pinctrl of lubancat 1 + +From: Andy Yan + +[ Upstream commit 8586a5d217ef7bfeee24943c600a8a7890d6f477 ] + +According to the schematics, the gpio control sys_led is GPIO0_C5. + +Fixes: 8d94da58de53 ("arm64: dts: rockchip: Add EmbedFire LubanCat 1") +Reported-by: Zhang Ning +Closes: https://lore.kernel.org/linux-rockchip/OS0P286MB06412D049D8BF7B063D41350CD95A@OS0P286MB0641.JPNP286.PROD.OUTLOOK.COM/T/#u +Signed-off-by: Andy Yan +Link: https://lore.kernel.org/r/20231225005055.3102743-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts b/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts +index 1c6d83b47cd2..6ecdf5d28339 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts +@@ -455,7 +455,7 @@ &pcie2x1 { + &pinctrl { + leds { + sys_led_pin: sys-status-led-pin { +- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-ti-iot2050-re-add-aliases.patch b/queue-6.7/arm64-dts-ti-iot2050-re-add-aliases.patch new file mode 100644 index 00000000000..f9d92d7bee0 --- /dev/null +++ b/queue-6.7/arm64-dts-ti-iot2050-re-add-aliases.patch @@ -0,0 +1,44 @@ +From fc9f314945be6d0d374418b2aff016a3090e4491 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 4 Nov 2023 09:52:15 +0100 +Subject: arm64: dts: ti: iot2050: Re-add aliases + +From: Jan Kiszka + +[ Upstream commit ad8edf4ff37ab157f6547da173aedc9f4e5c4015 ] + +Lost while dropping them from the common dtsi. + +Fixes: ffc449e016e2 ("arm64: dts: ti: k3-am65: Drop aliases") +Signed-off-by: Jan Kiszka +Link: https://lore.kernel.org/r/1edbc1b56ed4ff2256d7afb7db3cab4b3a423692.1699087938.git.jan.kiszka@siemens.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +index ba1c14a54acf..b849648d51f9 100644 +--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +@@ -14,6 +14,16 @@ + + / { + aliases { ++ serial0 = &wkup_uart0; ++ serial1 = &mcu_uart0; ++ serial2 = &main_uart0; ++ serial3 = &main_uart1; ++ i2c0 = &wkup_i2c0; ++ i2c1 = &mcu_i2c0; ++ i2c2 = &main_i2c0; ++ i2c3 = &main_i2c1; ++ i2c4 = &main_i2c2; ++ i2c5 = &main_i2c3; + spi0 = &mcu_spi0; + mmc0 = &sdhci1; + mmc1 = &sdhci0; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch b/queue-6.7/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch new file mode 100644 index 00000000000..03d25c4656e --- /dev/null +++ b/queue-6.7/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch @@ -0,0 +1,47 @@ +From d6388a19e13f7f50931c42e0032d3132df282612 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 27 Oct 2023 12:29:30 +0530 +Subject: arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes + +From: Nitin Yadav + +[ Upstream commit 7dc4af358cc382c5d20bd5b726e53ef0f526eb6d ] + +Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according +to AM62A7 datasheet[0]. + +[0] https://www.ti.com/lit/gpn/am62a3 Section: 6.3.10 GPIO (Page No. 52-55) +Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") +Signed-off-by: Nitin Yadav +Link: https://lore.kernel.org/r/20231027065930.1187405-1-n-yadav@ti.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +index 4ae7fdc5221b..ccd708b09acd 100644 +--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +@@ -462,7 +462,7 @@ main_gpio0: gpio@600000 { + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; +- ti,ngpio = <87>; ++ ti,ngpio = <92>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; +@@ -480,7 +480,7 @@ main_gpio1: gpio@601000 { + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; +- ti,ngpio = <88>; ++ ti,ngpio = <52>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch b/queue-6.7/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch new file mode 100644 index 00000000000..346e0581807 --- /dev/null +++ b/queue-6.7/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch @@ -0,0 +1,47 @@ +From d238cb1729b206566d86c35cd2e063f1bc600866 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 11:57:48 +0200 +Subject: arm64: dts: ti: k3-am65-main: Fix DSS irq trigger type + +From: Tomi Valkeinen + +[ Upstream commit b57160859263c083c49482b0d083a586b1517f78 ] + +DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING in the DT file, but +the TRM says it is level triggered. + +For some reason triggering on rising edge results in double the amount +of expected interrupts, e.g. for normal page flipping test the number of +interrupts per second is 2 * fps. It is as if the IRQ triggers on both +edges. There are no other side effects to this issue than slightly +increased CPU & power consumption due to the extra interrupt. + +Switching to IRQ_TYPE_LEVEL_HIGH is correct and fixes the issue, so +let's do that. + +Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") +Signed-off-by: Tomi Valkeinen +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231106-am65-dss-clk-edge-v1-1-4a959fec0e1e@ideasonboard.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +index 5ebb87f467de..29048d6577cf 100644 +--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +@@ -1034,7 +1034,7 @@ dss: dss@4a00000 { + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; + +- interrupts = ; ++ interrupts = ; + + dma-coherent; + +-- +2.43.0 + diff --git a/queue-6.7/arm64-dts-xilinx-apply-overlays-to-base-dtbs.patch b/queue-6.7/arm64-dts-xilinx-apply-overlays-to-base-dtbs.patch new file mode 100644 index 00000000000..49fdcc034e3 --- /dev/null +++ b/queue-6.7/arm64-dts-xilinx-apply-overlays-to-base-dtbs.patch @@ -0,0 +1,49 @@ +From 36c4ea2fcde42be3dc41a80a2006925fd7e70eaa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Sep 2023 16:47:47 -0500 +Subject: arm64: dts: xilinx: Apply overlays to base dtbs + +From: Rob Herring + +[ Upstream commit 23b697ec85f3e7beed271b9f344c54821de2251e ] + +DT overlays in tree need to be applied to a base DTB to validate they +apply, to run schema checks on them, and to catch any errors at compile +time. Defining the "-dtbs" variable is not enough as the combined DT must +be added to dtbs-y. + +zynqmp-sck-kr-g-revA.dtso and zynqmp-sck-kr-g-revB.dtso don't exist, so drop +them. + +Signed-off-by: Rob Herring +Fixes: 45fe0dc4ea2e ("arm64: xilinx: Use zynqmp prefix for SOM dt overlays") +Link: https://lore.kernel.org/r/20230911214751.2202913-1-robh@kernel.org +Signed-off-by: Michal Simek +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/xilinx/Makefile | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile +index 5e40c0b4fa0a..1068b0fa8e98 100644 +--- a/arch/arm64/boot/dts/xilinx/Makefile ++++ b/arch/arm64/boot/dts/xilinx/Makefile +@@ -22,11 +22,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb + + zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb + zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb + zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb + zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +- +-zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +-zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +-zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +-zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo ++dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb +-- +2.43.0 + diff --git a/queue-6.7/asm-generic-fix-32-bit-__generic_cmpxchg_local.patch b/queue-6.7/asm-generic-fix-32-bit-__generic_cmpxchg_local.patch new file mode 100644 index 00000000000..0203628a87b --- /dev/null +++ b/queue-6.7/asm-generic-fix-32-bit-__generic_cmpxchg_local.patch @@ -0,0 +1,39 @@ +From c0e437618e19e30830e7e4a33e5b6832c480b842 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 4 Jan 2024 09:40:10 +0000 +Subject: asm-generic: Fix 32 bit __generic_cmpxchg_local + +From: David McKay + +[ Upstream commit d93cca2f3109f88c94a32d3322ec8b2854a9c339 ] + +Commit 656e9007ef58 ("asm-generic: avoid __generic_cmpxchg_local +warnings") introduced a typo that means the code is incorrect for 32 bit +values. It will work fine for postive numbers, but will fail for +negative numbers on a system where longs are 64 bit. + +Fixes: 656e9007ef58 ("asm-generic: avoid __generic_cmpxchg_local warnings") +Signed-off-by: David McKay +Signed-off-by: Stuart Menefy +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + include/asm-generic/cmpxchg-local.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/asm-generic/cmpxchg-local.h b/include/asm-generic/cmpxchg-local.h +index 3df9f59a544e..f27d66fdc00a 100644 +--- a/include/asm-generic/cmpxchg-local.h ++++ b/include/asm-generic/cmpxchg-local.h +@@ -34,7 +34,7 @@ static inline unsigned long __generic_cmpxchg_local(volatile void *ptr, + *(u16 *)ptr = (new & 0xffffu); + break; + case 4: prev = *(u32 *)ptr; +- if (prev == (old & 0xffffffffffu)) ++ if (prev == (old & 0xffffffffu)) + *(u32 *)ptr = (new & 0xffffffffu); + break; + case 8: prev = *(u64 *)ptr; +-- +2.43.0 + diff --git a/queue-6.7/asoc-amd-vangogh-drop-conflicting-acpi-based-probing.patch b/queue-6.7/asoc-amd-vangogh-drop-conflicting-acpi-based-probing.patch new file mode 100644 index 00000000000..bef589b5bf4 --- /dev/null +++ b/queue-6.7/asoc-amd-vangogh-drop-conflicting-acpi-based-probing.patch @@ -0,0 +1,112 @@ +From 8979e4bfb3f2bcde5f92f64ce82db3163e79694d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 9 Dec 2023 22:32:19 +0200 +Subject: ASoC: amd: vangogh: Drop conflicting ACPI-based probing + +From: Cristian Ciocaltea + +[ Upstream commit ddd1ee12a8fb6e4d6f86eddeba64c135eee56623 ] + +The Vangogh machine driver variant based on the MAX98388 amplifier, as +found on Valve's Steam Deck OLED, relies on probing via an ACPI match +table. This worked fine until commit 197b1f7f0df1 ("ASoC: amd: Add new +dmi entries to config entry") enabled SOF support for the target machine +(i.e. Galileo product), causing the sound card to enter the deferred +probe state indefinitely: + +$ cat /sys/kernel/debug/devices_deferred +AMDI8821:00 acp5x_mach: Register card (acp5x-max98388) failed + +The issue is related to commit e89f45edb747 ("ASoC: amd: vangogh: Add +check for acp config flags in vangogh platform"), which tries to +mitigate potential conflicts between SOF and generic ACP Vangogh +drivers, due to sharing the PCI device IDs. + +However, the solution is effective only if the machine driver is +directly probed by pci-acp5x through platform_device_register_full(). + +Hence, remove the conflicting ACPI based probing and rely exclusively on +DMI quirks for sound card setup. + +Fixes: dba22efd0d17 ("ASoC: amd: vangogh: Add support for NAU8821/MAX98388 variant") +Signed-off-by: Cristian Ciocaltea +Reviewed-by: Emil Velikov +Link: https://msgid.link/r/20231209203229.878730-2-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/amd/vangogh/acp5x-mach.c | 35 +++++++++++------------------- + 1 file changed, 13 insertions(+), 22 deletions(-) + +diff --git a/sound/soc/amd/vangogh/acp5x-mach.c b/sound/soc/amd/vangogh/acp5x-mach.c +index de4b478a983d..7878e061ecb9 100644 +--- a/sound/soc/amd/vangogh/acp5x-mach.c ++++ b/sound/soc/amd/vangogh/acp5x-mach.c +@@ -439,7 +439,15 @@ static const struct dmi_system_id acp5x_vg_quirk_table[] = { + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Valve"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jupiter"), +- } ++ }, ++ .driver_data = (void *)&acp5x_8821_35l41_card, ++ }, ++ { ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Valve"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Galileo"), ++ }, ++ .driver_data = (void *)&acp5x_8821_98388_card, + }, + {} + }; +@@ -452,25 +460,15 @@ static int acp5x_probe(struct platform_device *pdev) + struct snd_soc_card *card; + int ret; + +- card = (struct snd_soc_card *)device_get_match_data(dev); +- if (!card) { +- /* +- * This is normally the result of directly probing the driver +- * in pci-acp5x through platform_device_register_full(), which +- * is necessary for the CS35L41 variant, as it doesn't support +- * ACPI probing and relies on DMI quirks. +- */ +- dmi_id = dmi_first_match(acp5x_vg_quirk_table); +- if (!dmi_id) +- return -ENODEV; +- +- card = &acp5x_8821_35l41_card; +- } ++ dmi_id = dmi_first_match(acp5x_vg_quirk_table); ++ if (!dmi_id || !dmi_id->driver_data) ++ return -ENODEV; + + machine = devm_kzalloc(dev, sizeof(*machine), GFP_KERNEL); + if (!machine) + return -ENOMEM; + ++ card = dmi_id->driver_data; + card->dev = dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, machine); +@@ -482,17 +480,10 @@ static int acp5x_probe(struct platform_device *pdev) + return 0; + } + +-static const struct acpi_device_id acp5x_acpi_match[] = { +- { "AMDI8821", (kernel_ulong_t)&acp5x_8821_98388_card }, +- {}, +-}; +-MODULE_DEVICE_TABLE(acpi, acp5x_acpi_match); +- + static struct platform_driver acp5x_mach_driver = { + .driver = { + .name = DRV_NAME, + .pm = &snd_soc_pm_ops, +- .acpi_match_table = acp5x_acpi_match, + }, + .probe = acp5x_probe, + }; +-- +2.43.0 + diff --git a/queue-6.7/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch b/queue-6.7/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch new file mode 100644 index 00000000000..84a0d204360 --- /dev/null +++ b/queue-6.7/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch @@ -0,0 +1,64 @@ +From d971ba4076338dc3f5e96d9a0baffeb0436896a2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 14:20:31 +0100 +Subject: ASoC: cs35l33: Fix GPIO name and drop legacy include + +From: Linus Walleij + +[ Upstream commit 50678d339d670a92658e5538ebee30447c88ccb3 ] + +This driver includes the legacy GPIO APIs and + but does not use any symbols from any of +them. + +Drop the includes. + +Further the driver is requesting "reset-gpios" rather than +just "reset" from the GPIO framework. This is wrong because +the gpiolib core will add "-gpios" before processing the +request from e.g. device tree. Drop the suffix. + +The last problem means that the optional RESET GPIO has +never been properly retrieved and used even if it existed, +but nobody noticed. + +Fixes: 3333cb7187b9 ("ASoC: cs35l33: Initial commit of the cs35l33 CODEC driver.") +Acked-by: Charles Keepax +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20231201-descriptors-sound-cirrus-v2-2-ee9f9d4655eb@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/cs35l33.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/cs35l33.c b/sound/soc/codecs/cs35l33.c +index 4010a2d33a33..a19a2bafb37c 100644 +--- a/sound/soc/codecs/cs35l33.c ++++ b/sound/soc/codecs/cs35l33.c +@@ -22,13 +22,11 @@ + #include + #include + #include +-#include + #include + #include + #include + #include + #include +-#include + #include + + #include "cs35l33.h" +@@ -1165,7 +1163,7 @@ static int cs35l33_i2c_probe(struct i2c_client *i2c_client) + + /* We could issue !RST or skip it based on AMP topology */ + cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, +- "reset-gpios", GPIOD_OUT_HIGH); ++ "reset", GPIOD_OUT_HIGH); + if (IS_ERR(cs35l33->reset_gpio)) { + dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n", + __func__); +-- +2.43.0 + diff --git a/queue-6.7/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch b/queue-6.7/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch new file mode 100644 index 00000000000..2f262852f3c --- /dev/null +++ b/queue-6.7/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch @@ -0,0 +1,65 @@ +From 93d0ee67f6e8fb35eb89940fca6039a8f7b35e37 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 14:20:32 +0100 +Subject: ASoC: cs35l34: Fix GPIO name and drop legacy include + +From: Linus Walleij + +[ Upstream commit a6122b0b4211d132934ef99e7b737910e6d54d2f ] + +This driver includes the legacy GPIO APIs and + but does not use any symbols from any of +them. + +Drop the includes. + +Further the driver is requesting "reset-gpios" rather than +just "reset" from the GPIO framework. This is wrong because +the gpiolib core will add "-gpios" before processing the +request from e.g. device tree. Drop the suffix. + +The last problem means that the optional RESET GPIO has +never been properly retrieved and used even if it existed, +but nobody noticed. + +Fixes: c1124c09e103 ("ASoC: cs35l34: Initial commit of the cs35l34 CODEC driver.") +Acked-by: Charles Keepax +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20231201-descriptors-sound-cirrus-v2-3-ee9f9d4655eb@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/cs35l34.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/cs35l34.c b/sound/soc/codecs/cs35l34.c +index e5871736fa29..cca59de66b73 100644 +--- a/sound/soc/codecs/cs35l34.c ++++ b/sound/soc/codecs/cs35l34.c +@@ -20,14 +20,12 @@ + #include + #include + #include +-#include + #include + #include + #include + #include + #include + #include +-#include + #include + #include + #include +@@ -1061,7 +1059,7 @@ static int cs35l34_i2c_probe(struct i2c_client *i2c_client) + dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); + + cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, +- "reset-gpios", GPIOD_OUT_LOW); ++ "reset", GPIOD_OUT_LOW); + if (IS_ERR(cs35l34->reset_gpio)) { + ret = PTR_ERR(cs35l34->reset_gpio); + goto err_regulator; +-- +2.43.0 + diff --git a/queue-6.7/asoc-fsl_rpmsg-update-kconfig-dependencies.patch b/queue-6.7/asoc-fsl_rpmsg-update-kconfig-dependencies.patch new file mode 100644 index 00000000000..995f209c112 --- /dev/null +++ b/queue-6.7/asoc-fsl_rpmsg-update-kconfig-dependencies.patch @@ -0,0 +1,44 @@ +From ff02de6eef7f03e508ced05ddcd6de8a690414a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 12:31:17 +0100 +Subject: ASoC: fsl_rpmsg: update Kconfig dependencies + +From: Arnd Bergmann + +[ Upstream commit 9cce9c4806a89439ea34aad2e382150d68c7ea95 ] + +SND_SOC_IMX_RPMSG gained a new dependency and gets selected by SND_SOC_FSL_RPMSG, +which as a result needs to have the same dependency, or produce a build failure +based on that: + +WARNING: unmet direct dependencies detected for SND_SOC_IMX_RPMSG + Depends on [n]: SOUND [=y] && SND [=y] && SND_SOC [=y] && SND_IMX_SOC [=y] && RPMSG [=y] && OF [=y] && I2C [=n] + Selected by [y]: + - SND_SOC_FSL_RPMSG [=y] && SOUND [=y] && SND [=y] && SND_SOC [=y] && COMMON_CLK [=y] && RPMSG [=y] && (SND_IMX_SOC [=y] || SND_IMX_SOC [=y]=n) && SND_IMX_SOC [=y]!=n +x86_64-linux-ld: sound/soc/fsl/imx-rpmsg.o: in function `imx_rpmsg_late_probe': +imx-rpmsg.c:(.text+0x11e): undefined reference to `i2c_find_device_by_fwnode' + +Fixes: f83d38def6b1 ("ASoC: imx-rpmsg: SND_SOC_IMX_RPMSG should depend on OF and I2C") +Signed-off-by: Arnd Bergmann +Link: https://lore.kernel.org/r/20231129113204.2869356-1-arnd@kernel.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/fsl/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig +index be342ee03fb9..d14061e88e58 100644 +--- a/sound/soc/fsl/Kconfig ++++ b/sound/soc/fsl/Kconfig +@@ -121,6 +121,7 @@ config SND_SOC_FSL_UTILS + config SND_SOC_FSL_RPMSG + tristate "NXP Audio Base On RPMSG support" + depends on COMMON_CLK ++ depends on OF && I2C + depends on RPMSG + depends on SND_IMX_SOC || SND_IMX_SOC = n + select SND_SOC_IMX_RPMSG if SND_IMX_SOC != n +-- +2.43.0 + diff --git a/queue-6.7/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch b/queue-6.7/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch new file mode 100644 index 00000000000..fdddf1158d6 --- /dev/null +++ b/queue-6.7/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch @@ -0,0 +1,67 @@ +From e48e51bba281e03bd736e8e7d502422733b685f3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:41:58 -0600 +Subject: ASoC: Intel: glk_rt5682_max98357a: fix board id mismatch + +From: Brent Lu + +[ Upstream commit 486ede0df82dd74472c6f5651e38ff48f7f766c1 ] + +The drv_name in enumeration table for ALC5682I-VS codec does not match +the board id string in machine driver. Modify the entry of "10EC5682" +to enumerate "RTL5682" as well and remove invalid entry. + +Fixes: 88b4d77d6035 ("ASoC: Intel: glk_rt5682_max98357a: support ALC5682I-VS codec") +Reported-by: Curtis Malainey +Reviewed-by: Curtis Malainey +Reviewed-by: Bard Liao +Signed-off-by: Brent Lu +Signed-off-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20231204214200.203100-4-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/common/soc-acpi-intel-glk-match.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/sound/soc/intel/common/soc-acpi-intel-glk-match.c b/sound/soc/intel/common/soc-acpi-intel-glk-match.c +index 387e73100884..8911c90bbaf6 100644 +--- a/sound/soc/intel/common/soc-acpi-intel-glk-match.c ++++ b/sound/soc/intel/common/soc-acpi-intel-glk-match.c +@@ -19,6 +19,11 @@ static const struct snd_soc_acpi_codecs glk_codecs = { + .codecs = {"MX98357A"} + }; + ++static const struct snd_soc_acpi_codecs glk_rt5682_rt5682s_hp = { ++ .num_codecs = 2, ++ .codecs = {"10EC5682", "RTL5682"}, ++}; ++ + struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[] = { + { + .id = "INT343A", +@@ -35,20 +40,13 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[] = { + .sof_tplg_filename = "sof-glk-da7219.tplg", + }, + { +- .id = "10EC5682", ++ .comp_ids = &glk_rt5682_rt5682s_hp, + .drv_name = "glk_rt5682_mx98357a", + .fw_filename = "intel/dsp_fw_glk.bin", + .machine_quirk = snd_soc_acpi_codec_list, + .quirk_data = &glk_codecs, + .sof_tplg_filename = "sof-glk-rt5682.tplg", + }, +- { +- .id = "RTL5682", +- .drv_name = "glk_rt5682_max98357a", +- .machine_quirk = snd_soc_acpi_codec_list, +- .quirk_data = &glk_codecs, +- .sof_tplg_filename = "sof-glk-rt5682.tplg", +- }, + { + .id = "10134242", + .drv_name = "glk_cs4242_mx98357a", +-- +2.43.0 + diff --git a/queue-6.7/asoc-intel-sof_sdw_rt_sdca_jack_common-ctx-headset_c.patch b/queue-6.7/asoc-intel-sof_sdw_rt_sdca_jack_common-ctx-headset_c.patch new file mode 100644 index 00000000000..c7b2e641086 --- /dev/null +++ b/queue-6.7/asoc-intel-sof_sdw_rt_sdca_jack_common-ctx-headset_c.patch @@ -0,0 +1,48 @@ +From 3307c9758926e1b6588c9af5b6fbe5149ed10285 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:41:59 -0600 +Subject: ASoC: Intel: sof_sdw_rt_sdca_jack_common: ctx->headset_codec_dev = + NULL +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Bard Liao + +[ Upstream commit e38e252dbceeef7d2f848017132efd68e9ae1416 ] + +sof_sdw_rt_sdca_jack_exit() are used by different codecs, and some of +them use the same dai name. +For example, rt712 and rt713 both use "rt712-sdca-aif1" and +sof_sdw_rt_sdca_jack_exit(). +As a result, sof_sdw_rt_sdca_jack_exit() will be called twice by +mc_dailink_exit_loop(). Set ctx->headset_codec_dev = NULL; after +put_device(ctx->headset_codec_dev); to avoid ctx->headset_codec_dev +being put twice. + +Fixes: 5360c6704638 ("ASoC: Intel: sof_sdw: add rt712 support") +Reviewed-by: Péter Ujfalusi +Signed-off-by: Bard Liao +Signed-off-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20231204214200.203100-5-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/boards/sof_sdw_rt_sdca_jack_common.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/intel/boards/sof_sdw_rt_sdca_jack_common.c b/sound/soc/intel/boards/sof_sdw_rt_sdca_jack_common.c +index 65bbcee88d6d..49a513399dc4 100644 +--- a/sound/soc/intel/boards/sof_sdw_rt_sdca_jack_common.c ++++ b/sound/soc/intel/boards/sof_sdw_rt_sdca_jack_common.c +@@ -168,6 +168,7 @@ int sof_sdw_rt_sdca_jack_exit(struct snd_soc_card *card, struct snd_soc_dai_link + + device_remove_software_node(ctx->headset_codec_dev); + put_device(ctx->headset_codec_dev); ++ ctx->headset_codec_dev = NULL; + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.7/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch b/queue-6.7/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch new file mode 100644 index 00000000000..aee77df6c12 --- /dev/null +++ b/queue-6.7/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch @@ -0,0 +1,53 @@ +From f9e4895b6c1b3f26e3a1377abdbda77b8711d6fe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 26 Nov 2023 22:40:18 +0100 +Subject: ASoC: rt5645: Drop double EF20 entry from dmi_platform_data[] + +From: Hans de Goede + +[ Upstream commit 51add1687f39292af626ac3c2046f49241713273 ] + +dmi_platform_data[] first contains a DMI entry matching: + + DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), + +and then contains an identical entry except for the match being: + + DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), + +Since these are partial (non exact) DMI matches the first match +will also match any board with "EF20EA" in their DMI product-name, +drop the second, redundant, entry. + +Fixes: a4dae468cfdd ("ASoC: rt5645: Add ACPI-defined GPIO for ECS EF20 series") +Cc: Chris Chiu +Signed-off-by: Hans de Goede +Link: https://msgid.link/r/20231126214024.300505-2-hdegoede@redhat.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/rt5645.c | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c +index a0d01d71d8b5..edcb85bd8ea7 100644 +--- a/sound/soc/codecs/rt5645.c ++++ b/sound/soc/codecs/rt5645.c +@@ -3854,14 +3854,6 @@ static const struct dmi_system_id dmi_platform_data[] = { + }, + .driver_data = (void *)&ecs_ef20_platform_data, + }, +- { +- .ident = "EF20EA", +- .callback = cht_rt5645_ef20_quirk_cb, +- .matches = { +- DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), +- }, +- .driver_data = (void *)&ecs_ef20_platform_data, +- }, + { } + }; + +-- +2.43.0 + diff --git a/queue-6.7/asoc-sof-intel-pci-mtl-fix-arl-s-definitions.patch b/queue-6.7/asoc-sof-intel-pci-mtl-fix-arl-s-definitions.patch new file mode 100644 index 00000000000..5e9c60be848 --- /dev/null +++ b/queue-6.7/asoc-sof-intel-pci-mtl-fix-arl-s-definitions.patch @@ -0,0 +1,129 @@ +From 9b47161088ab9fd9b5c62cf2e57ecf5e6b897979 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:27:09 -0600 +Subject: ASoC: SOF: Intel: pci-mtl: fix ARL-S definitions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pierre-Louis Bossart + +[ Upstream commit a00be6dc9bb80796244196033aa5eb258b6af47a ] + +The initial copy/paste from MTL was incorrect, the hardware is +different and requires different descriptors along with a dedicated +firmware binary. + +Fixes: 3851831f529e ("ASoC: SOF: Intel: pci-mtl: use ARL specific firmware definitions") +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Péter Ujfalusi +Reviewed-by: Kai Vehmanen +Acked-by: Mark Brown +Link: https://lore.kernel.org/r/20231204212710.185976-5-pierre-louis.bossart@linux.intel.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/soc/sof/intel/hda.h | 1 + + sound/soc/sof/intel/mtl.c | 28 ++++++++++++++++++++++++++++ + sound/soc/sof/intel/pci-mtl.c | 12 ++++++------ + 3 files changed, 35 insertions(+), 6 deletions(-) + +diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h +index d628d6a3a7e5..1592e27bc14d 100644 +--- a/sound/soc/sof/intel/hda.h ++++ b/sound/soc/sof/intel/hda.h +@@ -882,6 +882,7 @@ extern const struct sof_intel_dsp_desc ehl_chip_info; + extern const struct sof_intel_dsp_desc jsl_chip_info; + extern const struct sof_intel_dsp_desc adls_chip_info; + extern const struct sof_intel_dsp_desc mtl_chip_info; ++extern const struct sof_intel_dsp_desc arl_s_chip_info; + extern const struct sof_intel_dsp_desc lnl_chip_info; + + /* Probes support */ +diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c +index 254dbbeac1d0..7946110e7adf 100644 +--- a/sound/soc/sof/intel/mtl.c ++++ b/sound/soc/sof/intel/mtl.c +@@ -746,3 +746,31 @@ const struct sof_intel_dsp_desc mtl_chip_info = { + .hw_ip_version = SOF_INTEL_ACE_1_0, + }; + EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); ++ ++const struct sof_intel_dsp_desc arl_s_chip_info = { ++ .cores_num = 2, ++ .init_core_mask = BIT(0), ++ .host_managed_cores_mask = BIT(0), ++ .ipc_req = MTL_DSP_REG_HFIPCXIDR, ++ .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, ++ .ipc_ack = MTL_DSP_REG_HFIPCXIDA, ++ .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, ++ .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, ++ .rom_status_reg = MTL_DSP_ROM_STS, ++ .rom_init_timeout = 300, ++ .ssp_count = MTL_SSP_COUNT, ++ .ssp_base_offset = CNL_SSP_BASE_OFFSET, ++ .sdw_shim_base = SDW_SHIM_BASE_ACE, ++ .sdw_alh_base = SDW_ALH_BASE_ACE, ++ .d0i3_offset = MTL_HDA_VS_D0I3C, ++ .read_sdw_lcount = hda_sdw_check_lcount_common, ++ .enable_sdw_irq = mtl_enable_sdw_irq, ++ .check_sdw_irq = mtl_dsp_check_sdw_irq, ++ .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, ++ .check_ipc_irq = mtl_dsp_check_ipc_irq, ++ .cl_init = mtl_dsp_cl_init, ++ .power_down_dsp = mtl_power_down_dsp, ++ .disable_interrupts = mtl_dsp_disable_interrupts, ++ .hw_ip_version = SOF_INTEL_ACE_1_0, ++}; ++EXPORT_SYMBOL_NS(arl_s_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); +diff --git a/sound/soc/sof/intel/pci-mtl.c b/sound/soc/sof/intel/pci-mtl.c +index 0f378f45486d..60d5e73cdad2 100644 +--- a/sound/soc/sof/intel/pci-mtl.c ++++ b/sound/soc/sof/intel/pci-mtl.c +@@ -50,7 +50,7 @@ static const struct sof_dev_desc mtl_desc = { + .ops_free = hda_ops_free, + }; + +-static const struct sof_dev_desc arl_desc = { ++static const struct sof_dev_desc arl_s_desc = { + .use_acpi_target_states = true, + .machines = snd_soc_acpi_intel_arl_machines, + .alt_machines = snd_soc_acpi_intel_arl_sdw_machines, +@@ -58,21 +58,21 @@ static const struct sof_dev_desc arl_desc = { + .resindex_pcicfg_base = -1, + .resindex_imr_base = -1, + .irqindex_host_ipc = -1, +- .chip_info = &mtl_chip_info, ++ .chip_info = &arl_s_chip_info, + .ipc_supported_mask = BIT(SOF_IPC_TYPE_4), + .ipc_default = SOF_IPC_TYPE_4, + .dspless_mode_supported = true, /* Only supported for HDaudio */ + .default_fw_path = { +- [SOF_IPC_TYPE_4] = "intel/sof-ipc4/arl", ++ [SOF_IPC_TYPE_4] = "intel/sof-ipc4/arl-s", + }, + .default_lib_path = { +- [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/arl", ++ [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/arl-s", + }, + .default_tplg_path = { + [SOF_IPC_TYPE_4] = "intel/sof-ace-tplg", + }, + .default_fw_filename = { +- [SOF_IPC_TYPE_4] = "sof-arl.ri", ++ [SOF_IPC_TYPE_4] = "sof-arl-s.ri", + }, + .nocodec_tplg_filename = "sof-arl-nocodec.tplg", + .ops = &sof_mtl_ops, +@@ -83,7 +83,7 @@ static const struct sof_dev_desc arl_desc = { + /* PCI IDs */ + static const struct pci_device_id sof_pci_ids[] = { + { PCI_DEVICE_DATA(INTEL, HDA_MTL, &mtl_desc) }, +- { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, &arl_desc) }, ++ { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, &arl_s_desc) }, + { 0, } + }; + MODULE_DEVICE_TABLE(pci, sof_pci_ids); +-- +2.43.0 + diff --git a/queue-6.7/asoc-sof-topology-use-partial-match-for-disconnectin.patch b/queue-6.7/asoc-sof-topology-use-partial-match-for-disconnectin.patch new file mode 100644 index 00000000000..ca417113b54 --- /dev/null +++ b/queue-6.7/asoc-sof-topology-use-partial-match-for-disconnectin.patch @@ -0,0 +1,40 @@ +From 5b6763a53f9cd58e1f643a5db2666821268919d8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:47:10 -0600 +Subject: ASoC: SOF: topology: Use partial match for disconnecting DAI link and + DAI widget + +From: Bard Liao + +[ Upstream commit 2f03970198d6438d95b96f69041254bd39aafed0 ] + +We use partial match for connecting DAI link and DAI widget. We need to +use partial match for disconnecting, too. + +Fixes: fe88788779fc ("ASoC: SOF: topology: Use partial match for connecting DAI link and DAI widget") +Reviewed-by: Ranjani Sridharan +Signed-off-by: Bard Liao +Signed-off-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20231204214713.208951-2-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/sof/topology.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sof/topology.c b/sound/soc/sof/topology.c +index 37ec671a2d76..7133ec13322b 100644 +--- a/sound/soc/sof/topology.c ++++ b/sound/soc/sof/topology.c +@@ -1134,7 +1134,7 @@ static void sof_disconnect_dai_widget(struct snd_soc_component *scomp, + list_for_each_entry(rtd, &card->rtd_list, list) { + /* does stream match DAI link ? */ + if (!rtd->dai_link->stream_name || +- strcmp(sname, rtd->dai_link->stream_name)) ++ !strstr(rtd->dai_link->stream_name, sname)) + continue; + + for_each_rtd_cpu_dais(rtd, i, cpu_dai) +-- +2.43.0 + diff --git a/queue-6.7/asoc-tas2781-add-support-for-fw-version-0x0503.patch b/queue-6.7/asoc-tas2781-add-support-for-fw-version-0x0503.patch new file mode 100644 index 00000000000..1d53d7087a2 --- /dev/null +++ b/queue-6.7/asoc-tas2781-add-support-for-fw-version-0x0503.patch @@ -0,0 +1,37 @@ +From b6de12cbd2df3a6d3b77a9da1e886303667b6868 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 01:25:39 +0100 +Subject: ASoC: tas2781: add support for FW version 0x0503 + +From: Gergo Koteles + +[ Upstream commit ee00330a5b78e2acf4b3aac32913da43e2c12a26 ] + +Layout of FW version 0x0503 is compatible with 0x0502. +Already supported by TI's tas2781-linux-driver tree. +https://git.ti.com/cgit/tas2781-linux-drivers/tas2781-linux-driver/ + +Fixes: 915f5eadebd2 ("ASoC: tas2781: firmware lib") +Signed-off-by: Gergo Koteles +Link: https://msgid.link/r/98d4ee4e01e834af72a1a0bea6736facf43582e0.1702513517.git.soyer@irl.hu +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/tas2781-fmwlib.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/codecs/tas2781-fmwlib.c b/sound/soc/codecs/tas2781-fmwlib.c +index 5c09e441a936..85e14ff61769 100644 +--- a/sound/soc/codecs/tas2781-fmwlib.c ++++ b/sound/soc/codecs/tas2781-fmwlib.c +@@ -1982,6 +1982,7 @@ static int tasdevice_dspfw_ready(const struct firmware *fmw, + case 0x301: + case 0x302: + case 0x502: ++ case 0x503: + tas_priv->fw_parse_variable_header = + fw_parse_variable_header_kernel; + tas_priv->fw_parse_program_data = +-- +2.43.0 + diff --git a/queue-6.7/blk-cgroup-fix-rcu-lockdep-warning-in-blkg_lookup.patch b/queue-6.7/blk-cgroup-fix-rcu-lockdep-warning-in-blkg_lookup.patch new file mode 100644 index 00000000000..b6d3532812a --- /dev/null +++ b/queue-6.7/blk-cgroup-fix-rcu-lockdep-warning-in-blkg_lookup.patch @@ -0,0 +1,46 @@ +From aef0e9012dca110bdbfacbac5c73858c837f7758 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 09:28:33 +0800 +Subject: blk-cgroup: fix rcu lockdep warning in blkg_lookup() + +From: Ming Lei + +[ Upstream commit 393cd8ffd832f23eec3a105553eff622e8198918 ] + +blkg_lookup() is called with either queue_lock or rcu read lock, so +use rcu_dereference_check(lockdep_is_held(&q->queue_lock)) for +retrieving 'blkg', which way models the check exactly for covering +queue lock or rcu read lock. + +Fix lockdep warning of "block/blk-cgroup.h:254 suspicious rcu_dereference_check() usage!" +from blkg_lookup(). + +Tested-by: Changhui Zhong +Signed-off-by: Ming Lei +Reviewed-by: Yu Kuai +Fixes: 83462a6c971c ("blkcg: Drop unnecessary RCU read [un]locks from blkg_conf_prep/finish()") +Acked-by: Tejun Heo +Link: https://lore.kernel.org/r/20231219012833.2129540-1-ming.lei@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/blk-cgroup.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/block/blk-cgroup.h b/block/blk-cgroup.h +index fd482439afbc..b927a4a0ad03 100644 +--- a/block/blk-cgroup.h ++++ b/block/blk-cgroup.h +@@ -252,7 +252,8 @@ static inline struct blkcg_gq *blkg_lookup(struct blkcg *blkcg, + if (blkcg == &blkcg_root) + return q->root_blkg; + +- blkg = rcu_dereference(blkcg->blkg_hint); ++ blkg = rcu_dereference_check(blkcg->blkg_hint, ++ lockdep_is_held(&q->queue_lock)); + if (blkg && blkg->q == q) + return blkg; + +-- +2.43.0 + diff --git a/queue-6.7/block-add-check-of-minors-and-first_minor-in-device_.patch b/queue-6.7/block-add-check-of-minors-and-first_minor-in-device_.patch new file mode 100644 index 00000000000..402fff7ffe5 --- /dev/null +++ b/queue-6.7/block-add-check-of-minors-and-first_minor-in-device_.patch @@ -0,0 +1,45 @@ +From 9ed0e620fb8cac81aecf62f2db1650ed81d875d1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 15:59:42 +0800 +Subject: block: add check of 'minors' and 'first_minor' in device_add_disk() + +From: Li Nan + +[ Upstream commit 4c434392c4777881d01beada6701eff8c76b43fe ] + +'first_minor' represents the starting minor number of disks, and +'minors' represents the number of partitions in the device. Neither +of them can be greater than MINORMASK + 1. + +Commit e338924bd05d ("block: check minor range in device_add_disk()") +only added the check of 'first_minor + minors'. However, their sum might +be less than MINORMASK but their values are wrong. Complete the checks now. + +Fixes: e338924bd05d ("block: check minor range in device_add_disk()") +Signed-off-by: Li Nan +Reviewed-by: Christoph Hellwig +Link: https://lore.kernel.org/r/20231219075942.840255-1-linan666@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/genhd.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/block/genhd.c b/block/genhd.c +index 13db3a7943d8..d74fb5b4ae68 100644 +--- a/block/genhd.c ++++ b/block/genhd.c +@@ -432,7 +432,9 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + DISK_MAX_PARTS); + disk->minors = DISK_MAX_PARTS; + } +- if (disk->first_minor + disk->minors > MINORMASK + 1) ++ if (disk->first_minor > MINORMASK || ++ disk->minors > MINORMASK + 1 || ++ disk->first_minor + disk->minors > MINORMASK + 1) + goto out_exit_elevator; + } else { + if (WARN_ON(disk->minors)) +-- +2.43.0 + diff --git a/queue-6.7/block-set-memalloc_noio-to-false-on-device_add_disk-.patch b/queue-6.7/block-set-memalloc_noio-to-false-on-device_add_disk-.patch new file mode 100644 index 00000000000..14f7d019a22 --- /dev/null +++ b/queue-6.7/block-set-memalloc_noio-to-false-on-device_add_disk-.patch @@ -0,0 +1,39 @@ +From d8b53fd695d3f89bd2c393367f1eb679dfd68238 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 15:53:56 +0800 +Subject: block: Set memalloc_noio to false on device_add_disk() error path + +From: Li Nan + +[ Upstream commit 5fa3d1a00c2d4ba14f1300371ad39d5456e890d7 ] + +On the error path of device_add_disk(), device's memalloc_noio flag was +set but not cleared. As the comment of pm_runtime_set_memalloc_noio(), +"The function should be called between device_add() and device_del()". +Clear this flag before device_del() now. + +Fixes: 25e823c8c37d ("block/genhd.c: apply pm_runtime_set_memalloc_noio on block devices") +Signed-off-by: Li Nan +Reviewed-by: Christoph Hellwig +Link: https://lore.kernel.org/r/20231211075356.1839282-1-linan666@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/genhd.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/block/genhd.c b/block/genhd.c +index c9d06f72c587..13db3a7943d8 100644 +--- a/block/genhd.c ++++ b/block/genhd.c +@@ -542,6 +542,7 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + kobject_put(disk->part0->bd_holder_dir); + out_del_block_link: + sysfs_remove_link(block_depr, dev_name(ddev)); ++ pm_runtime_set_memalloc_noio(ddev, false); + out_device_del: + device_del(ddev); + out_free_ext_minor: +-- +2.43.0 + diff --git a/queue-6.7/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch b/queue-6.7/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch new file mode 100644 index 00000000000..75d46ce01ff --- /dev/null +++ b/queue-6.7/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch @@ -0,0 +1,37 @@ +From 5ef6cfc57f7c296e9e545afc2f0c43eb8b15915e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 10:05:01 -0500 +Subject: blocklayoutdriver: Fix reference leak of pnfs_device_node + +From: Benjamin Coddington + +[ Upstream commit 1530827b90025cdf80c9b0d07a166d045a0a7b81 ] + +The error path for blocklayout's device lookup is missing a reference drop +for the case where a lookup finds the device, but the device is marked with +NFS_DEVICEID_UNAVAILABLE. + +Fixes: b3dce6a2f060 ("pnfs/blocklayout: handle transient devices") +Signed-off-by: Benjamin Coddington +Signed-off-by: Anna Schumaker +Signed-off-by: Sasha Levin +--- + fs/nfs/blocklayout/blocklayout.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/fs/nfs/blocklayout/blocklayout.c b/fs/nfs/blocklayout/blocklayout.c +index 943aeea1eb16..1d1d7abc3205 100644 +--- a/fs/nfs/blocklayout/blocklayout.c ++++ b/fs/nfs/blocklayout/blocklayout.c +@@ -580,6 +580,8 @@ bl_find_get_deviceid(struct nfs_server *server, + nfs4_delete_deviceid(node->ld, node->nfs_client, id); + goto retry; + } ++ ++ nfs4_put_deviceid_node(node); + return ERR_PTR(-ENODEV); + } + +-- +2.43.0 + diff --git a/queue-6.7/bluetooth-btmtkuart-fix-recv_buf-return-value.patch b/queue-6.7/bluetooth-btmtkuart-fix-recv_buf-return-value.patch new file mode 100644 index 00000000000..f5a6c2b3c9a --- /dev/null +++ b/queue-6.7/bluetooth-btmtkuart-fix-recv_buf-return-value.patch @@ -0,0 +1,68 @@ +From c8aa845732da7b8c20f60139d692673c2fe8dfdd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 17:40:19 +0100 +Subject: Bluetooth: btmtkuart: fix recv_buf() return value + +From: Francesco Dolcini + +[ Upstream commit 64057f051f20c2a2184b9db7f8037d928d68a4f4 ] + +Serdev recv_buf() callback is supposed to return the amount of bytes +consumed, therefore an int in between 0 and count. + +Do not return negative number in case of issue, just print an error and +return count. This fixes a WARN in ttyport_receive_buf(). + +Link: https://lore.kernel.org/all/087be419-ec6b-47ad-851a-5e1e3ea5cfcc@kernel.org/ +Fixes: 7237c4c9ec92 ("Bluetooth: mediatek: Add protocol support for MediaTek serial devices") +Signed-off-by: Francesco Dolcini +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btmtkuart.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/drivers/bluetooth/btmtkuart.c b/drivers/bluetooth/btmtkuart.c +index 935feab815d9..203a000a84e3 100644 +--- a/drivers/bluetooth/btmtkuart.c ++++ b/drivers/bluetooth/btmtkuart.c +@@ -336,7 +336,7 @@ mtk_stp_split(struct btmtkuart_dev *bdev, const unsigned char *data, int count, + return data; + } + +-static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) ++static void btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) + { + struct btmtkuart_dev *bdev = hci_get_drvdata(hdev); + const unsigned char *p_left = data, *p_h4; +@@ -375,25 +375,20 @@ static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) + bt_dev_err(bdev->hdev, + "Frame reassembly failed (%d)", err); + bdev->rx_skb = NULL; +- return err; ++ return; + } + + sz_left -= sz_h4; + p_left += sz_h4; + } +- +- return 0; + } + + static int btmtkuart_receive_buf(struct serdev_device *serdev, const u8 *data, + size_t count) + { + struct btmtkuart_dev *bdev = serdev_device_get_drvdata(serdev); +- int err; + +- err = btmtkuart_recv(bdev->hdev, data, count); +- if (err < 0) +- return err; ++ btmtkuart_recv(bdev->hdev, data, count); + + bdev->hdev->stat.byte_rx += count; + +-- +2.43.0 + diff --git a/queue-6.7/bluetooth-btnxpuart-fix-recv_buf-return-value.patch b/queue-6.7/bluetooth-btnxpuart-fix-recv_buf-return-value.patch new file mode 100644 index 00000000000..4a53e6e7cdd --- /dev/null +++ b/queue-6.7/bluetooth-btnxpuart-fix-recv_buf-return-value.patch @@ -0,0 +1,69 @@ +From bad56bf7bf5677c63cb9182e5370ab3c54f0779e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 17:40:18 +0100 +Subject: Bluetooth: btnxpuart: fix recv_buf() return value + +From: Francesco Dolcini + +[ Upstream commit 94d05394254401e503867c16aff561d3e687dfdc ] + +Serdev recv_buf() callback is supposed to return the amount of bytes +consumed, therefore an int in between 0 and count. + +Do not return a negative number in case of issue, just print an error +and return count. Before this change, in case of error, the returned +negative number was internally converted to 0 in ttyport_receive_buf, +now when the receive buffer is corrupted we return the size of the whole +received data (`count`). This should allow for better recovery in case +receiver/transmitter get out of sync if some data is lost. + +This fixes a WARN in ttyport_receive_buf(). + + Bluetooth: hci0: Frame reassembly failed (-84) + ------------[ cut here ]------------ + serial serial0: receive_buf returns -84 (count = 6) + WARNING: CPU: 0 PID: 37 at drivers/tty/serdev/serdev-ttyport.c:37 ttyport_receive_buf+0xd8/0xf8 + Modules linked in: mwifiex_sdio(+) ... + CPU: 0 PID: 37 Comm: kworker/u4:2 Not tainted 6.7.0-rc2-00147-gf1a09972a45a #1 + Hardware name: Toradex Verdin AM62 WB on Verdin Development Board (DT) + Workqueue: events_unbound flush_to_ldisc + pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : ttyport_receive_buf+0xd8/0xf8 + lr : ttyport_receive_buf+0xd8/0xf8 +... + Call trace: + ttyport_receive_buf+0xd8/0xf8 + flush_to_ldisc+0xbc/0x1a4 + process_scheduled_works+0x16c/0x28c + +Closes: https://lore.kernel.org/all/ZWEIhcUXfutb5SY6@francesco-nb.int.toradex.com/ +Fixes: 689ca16e5232 ("Bluetooth: NXP: Add protocol support for NXP Bluetooth chipsets") +Signed-off-by: Francesco Dolcini +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btnxpuart.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/bluetooth/btnxpuart.c b/drivers/bluetooth/btnxpuart.c +index b7e66b7ac570..951fe3014a3f 100644 +--- a/drivers/bluetooth/btnxpuart.c ++++ b/drivers/bluetooth/btnxpuart.c +@@ -1276,11 +1276,10 @@ static int btnxpuart_receive_buf(struct serdev_device *serdev, const u8 *data, + if (IS_ERR(nxpdev->rx_skb)) { + int err = PTR_ERR(nxpdev->rx_skb); + /* Safe to ignore out-of-sync bootloader signatures */ +- if (is_fw_downloading(nxpdev)) +- return count; +- bt_dev_err(nxpdev->hdev, "Frame reassembly failed (%d)", err); ++ if (!is_fw_downloading(nxpdev)) ++ bt_dev_err(nxpdev->hdev, "Frame reassembly failed (%d)", err); + nxpdev->rx_skb = NULL; +- return err; ++ return count; + } + if (!is_fw_downloading(nxpdev)) + nxpdev->hdev->stat.byte_rx += count; +-- +2.43.0 + diff --git a/queue-6.7/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch b/queue-6.7/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch new file mode 100644 index 00000000000..d2187a8554b --- /dev/null +++ b/queue-6.7/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch @@ -0,0 +1,88 @@ +From fef058f787a1e5cdae0e34dd739b71feaebf6aa1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 14:58:03 +0100 +Subject: Bluetooth: Fix bogus check for re-auth no supported with non-ssp + +From: Luiz Augusto von Dentz + +[ Upstream commit d03376c185926098cb4d668d6458801eb785c0a5 ] + +This reverts 19f8def031bfa50c579149b200bfeeb919727b27 +"Bluetooth: Fix auth_complete_evt for legacy units" which seems to be +working around a bug on a broken controller rather then any limitation +imposed by the Bluetooth spec, in fact if there ws not possible to +re-auth the command shall fail not succeed. + +Fixes: 19f8def031bf ("Bluetooth: Fix auth_complete_evt for legacy units") +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + include/net/bluetooth/hci_core.h | 1 - + net/bluetooth/hci_conn.c | 8 +++----- + net/bluetooth/hci_event.c | 11 ++--------- + 3 files changed, 5 insertions(+), 15 deletions(-) + +diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h +index a3a1ea2696a8..65dd28669352 100644 +--- a/include/net/bluetooth/hci_core.h ++++ b/include/net/bluetooth/hci_core.h +@@ -957,7 +957,6 @@ void hci_inquiry_cache_flush(struct hci_dev *hdev); + /* ----- HCI Connections ----- */ + enum { + HCI_CONN_AUTH_PEND, +- HCI_CONN_REAUTH_PEND, + HCI_CONN_ENCRYPT_PEND, + HCI_CONN_RSWITCH_PEND, + HCI_CONN_MODE_CHANGE_PEND, +diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c +index 2cee330188ce..d01db89fcb46 100644 +--- a/net/bluetooth/hci_conn.c ++++ b/net/bluetooth/hci_conn.c +@@ -2421,12 +2421,10 @@ static int hci_conn_auth(struct hci_conn *conn, __u8 sec_level, __u8 auth_type) + hci_send_cmd(conn->hdev, HCI_OP_AUTH_REQUESTED, + sizeof(cp), &cp); + +- /* If we're already encrypted set the REAUTH_PEND flag, +- * otherwise set the ENCRYPT_PEND. ++ /* Set the ENCRYPT_PEND to trigger encryption after ++ * authentication. + */ +- if (test_bit(HCI_CONN_ENCRYPT, &conn->flags)) +- set_bit(HCI_CONN_REAUTH_PEND, &conn->flags); +- else ++ if (!test_bit(HCI_CONN_ENCRYPT, &conn->flags)) + set_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags); + } + +diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c +index ebf17b51072f..ef8c3bed7361 100644 +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -3500,14 +3500,8 @@ static void hci_auth_complete_evt(struct hci_dev *hdev, void *data, + + if (!ev->status) { + clear_bit(HCI_CONN_AUTH_FAILURE, &conn->flags); +- +- if (!hci_conn_ssp_enabled(conn) && +- test_bit(HCI_CONN_REAUTH_PEND, &conn->flags)) { +- bt_dev_info(hdev, "re-auth of legacy device is not possible."); +- } else { +- set_bit(HCI_CONN_AUTH, &conn->flags); +- conn->sec_level = conn->pending_sec_level; +- } ++ set_bit(HCI_CONN_AUTH, &conn->flags); ++ conn->sec_level = conn->pending_sec_level; + } else { + if (ev->status == HCI_ERROR_PIN_OR_KEY_MISSING) + set_bit(HCI_CONN_AUTH_FAILURE, &conn->flags); +@@ -3516,7 +3510,6 @@ static void hci_auth_complete_evt(struct hci_dev *hdev, void *data, + } + + clear_bit(HCI_CONN_AUTH_PEND, &conn->flags); +- clear_bit(HCI_CONN_REAUTH_PEND, &conn->flags); + + if (conn->state == BT_CONFIG) { + if (!ev->status && hci_conn_ssp_enabled(conn)) { +-- +2.43.0 + diff --git a/queue-6.7/bpf-add-crosstask-check-to-__bpf_get_stack.patch b/queue-6.7/bpf-add-crosstask-check-to-__bpf_get_stack.patch new file mode 100644 index 00000000000..e51daf51dba --- /dev/null +++ b/queue-6.7/bpf-add-crosstask-check-to-__bpf_get_stack.patch @@ -0,0 +1,121 @@ +From 9202009cc89aa25d6a82abc22f391d1e82397061 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Nov 2023 03:23:34 -0800 +Subject: bpf: Add crosstask check to __bpf_get_stack + +From: Jordan Rome + +[ Upstream commit b8e3a87a627b575896e448021e5c2f8a3bc19931 ] + +Currently get_perf_callchain only supports user stack walking for +the current task. Passing the correct *crosstask* param will return +0 frames if the task passed to __bpf_get_stack isn't the current +one instead of a single incorrect frame/address. This change +passes the correct *crosstask* param but also does a preemptive +check in __bpf_get_stack if the task is current and returns +-EOPNOTSUPP if it is not. + +This issue was found using bpf_get_task_stack inside a BPF +iterator ("iter/task"), which iterates over all tasks. +bpf_get_task_stack works fine for fetching kernel stacks +but because get_perf_callchain relies on the caller to know +if the requested *task* is the current one (via *crosstask*) +it was failing in a confusing way. + +It might be possible to get user stacks for all tasks utilizing +something like access_process_vm but that requires the bpf +program calling bpf_get_task_stack to be sleepable and would +therefore be a breaking change. + +Fixes: fa28dcb82a38 ("bpf: Introduce helper bpf_get_task_stack()") +Signed-off-by: Jordan Rome +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231108112334.3433136-1-jordalgo@meta.com +Signed-off-by: Sasha Levin +--- + include/uapi/linux/bpf.h | 3 +++ + kernel/bpf/stackmap.c | 11 ++++++++++- + tools/include/uapi/linux/bpf.h | 3 +++ + 3 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h +index 0f6cdf52b1da..bda948a685e5 100644 +--- a/include/uapi/linux/bpf.h ++++ b/include/uapi/linux/bpf.h +@@ -4517,6 +4517,8 @@ union bpf_attr { + * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) + * Description + * Return a user or a kernel stack in bpf program provided buffer. ++ * Note: the user stack will only be populated if the *task* is ++ * the current task; all other tasks will return -EOPNOTSUPP. + * To achieve this, the helper needs *task*, which is a valid + * pointer to **struct task_struct**. To store the stacktrace, the + * bpf program provides *buf* with a nonnegative *size*. +@@ -4528,6 +4530,7 @@ union bpf_attr { + * + * **BPF_F_USER_STACK** + * Collect a user space stack instead of a kernel stack. ++ * The *task* must be the current task. + * **BPF_F_USER_BUILD_ID** + * Collect buildid+offset instead of ips for user stack, + * only valid if **BPF_F_USER_STACK** is also specified. +diff --git a/kernel/bpf/stackmap.c b/kernel/bpf/stackmap.c +index d6b277482085..dff7ba539701 100644 +--- a/kernel/bpf/stackmap.c ++++ b/kernel/bpf/stackmap.c +@@ -388,6 +388,7 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + { + u32 trace_nr, copy_len, elem_size, num_elem, max_depth; + bool user_build_id = flags & BPF_F_USER_BUILD_ID; ++ bool crosstask = task && task != current; + u32 skip = flags & BPF_F_SKIP_FIELD_MASK; + bool user = flags & BPF_F_USER_STACK; + struct perf_callchain_entry *trace; +@@ -410,6 +411,14 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + if (task && user && !user_mode(regs)) + goto err_fault; + ++ /* get_perf_callchain does not support crosstask user stack walking ++ * but returns an empty stack instead of NULL. ++ */ ++ if (crosstask && user) { ++ err = -EOPNOTSUPP; ++ goto clear; ++ } ++ + num_elem = size / elem_size; + max_depth = num_elem + skip; + if (sysctl_perf_event_max_stack < max_depth) +@@ -421,7 +430,7 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + trace = get_callchain_entry_for_task(task, max_depth); + else + trace = get_perf_callchain(regs, 0, kernel, user, max_depth, +- false, false); ++ crosstask, false); + if (unlikely(!trace)) + goto err_fault; + +diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h +index 0f6cdf52b1da..bda948a685e5 100644 +--- a/tools/include/uapi/linux/bpf.h ++++ b/tools/include/uapi/linux/bpf.h +@@ -4517,6 +4517,8 @@ union bpf_attr { + * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) + * Description + * Return a user or a kernel stack in bpf program provided buffer. ++ * Note: the user stack will only be populated if the *task* is ++ * the current task; all other tasks will return -EOPNOTSUPP. + * To achieve this, the helper needs *task*, which is a valid + * pointer to **struct task_struct**. To store the stacktrace, the + * bpf program provides *buf* with a nonnegative *size*. +@@ -4528,6 +4530,7 @@ union bpf_attr { + * + * **BPF_F_USER_STACK** + * Collect a user space stack instead of a kernel stack. ++ * The *task* must be the current task. + * **BPF_F_USER_BUILD_ID** + * Collect buildid+offset instead of ips for user stack, + * only valid if **BPF_F_USER_STACK** is also specified. +-- +2.43.0 + diff --git a/queue-6.7/bpf-add-kf_rcu-flag-to-bpf_refcount_acquire_impl.patch b/queue-6.7/bpf-add-kf_rcu-flag-to-bpf_refcount_acquire_impl.patch new file mode 100644 index 00000000000..62b44a21528 --- /dev/null +++ b/queue-6.7/bpf-add-kf_rcu-flag-to-bpf_refcount_acquire_impl.patch @@ -0,0 +1,56 @@ +From 471695d031497bd6f13a01ed6a8a70cdda25b714 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Nov 2023 00:56:34 -0800 +Subject: bpf: Add KF_RCU flag to bpf_refcount_acquire_impl + +From: Dave Marchevsky + +[ Upstream commit 1500a5d9f49cb66906d3ea1c9158df25cc41dd40 ] + +Refcounted local kptrs are kptrs to user-defined types with a +bpf_refcount field. Recent commits ([0], [1]) modified the lifetime of +refcounted local kptrs such that the underlying memory is not reused +until RCU grace period has elapsed. + +Separately, verification of bpf_refcount_acquire calls currently +succeeds for MAYBE_NULL non-owning reference input, which is a problem +as bpf_refcount_acquire_impl has no handling for this case. + +This patch takes advantage of aforementioned lifetime changes to tag +bpf_refcount_acquire_impl kfunc KF_RCU, thereby preventing MAYBE_NULL +input to the kfunc. The KF_RCU flag applies to all kfunc params; it's +fine for it to apply to the void *meta__ign param as that's populated by +the verifier and is tagged __ign regardless. + + [0]: commit 7e26cd12ad1c ("bpf: Use bpf_mem_free_rcu when + bpf_obj_dropping refcounted nodes") is the actual change to + allocation behaivor + [1]: commit 0816b8c6bf7f ("bpf: Consider non-owning refs to refcounted + nodes RCU protected") modified verifier understanding of + refcounted local kptrs to match [0]'s changes + +Signed-off-by: Dave Marchevsky +Fixes: 7c50b1cb76ac ("bpf: Add bpf_refcount_acquire kfunc") +Link: https://lore.kernel.org/r/20231107085639.3016113-2-davemarchevsky@fb.com +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/helpers.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c +index 56b0c1f678ee..6950f0461634 100644 +--- a/kernel/bpf/helpers.c ++++ b/kernel/bpf/helpers.c +@@ -2520,7 +2520,7 @@ BTF_ID_FLAGS(func, bpf_obj_new_impl, KF_ACQUIRE | KF_RET_NULL) + BTF_ID_FLAGS(func, bpf_percpu_obj_new_impl, KF_ACQUIRE | KF_RET_NULL) + BTF_ID_FLAGS(func, bpf_obj_drop_impl, KF_RELEASE) + BTF_ID_FLAGS(func, bpf_percpu_obj_drop_impl, KF_RELEASE) +-BTF_ID_FLAGS(func, bpf_refcount_acquire_impl, KF_ACQUIRE | KF_RET_NULL) ++BTF_ID_FLAGS(func, bpf_refcount_acquire_impl, KF_ACQUIRE | KF_RET_NULL | KF_RCU) + BTF_ID_FLAGS(func, bpf_list_push_front_impl) + BTF_ID_FLAGS(func, bpf_list_push_back_impl) + BTF_ID_FLAGS(func, bpf_list_pop_front, KF_ACQUIRE | KF_RET_NULL) +-- +2.43.0 + diff --git a/queue-6.7/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch b/queue-6.7/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch new file mode 100644 index 00000000000..f2dc1c36aa6 --- /dev/null +++ b/queue-6.7/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch @@ -0,0 +1,174 @@ +From a993fc145f6047809d6218e902d217432a6f87ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 22:04:20 +0800 +Subject: bpf: Add map and need_defer parameters to .map_fd_put_ptr() + +From: Hou Tao + +[ Upstream commit 20c20bd11a0702ce4dc9300c3da58acf551d9725 ] + +map is the pointer of outer map, and need_defer needs some explanation. +need_defer tells the implementation to defer the reference release of +the passed element and ensure that the element is still alive before +the bpf program, which may manipulate it, exits. + +The following three cases will invoke map_fd_put_ptr() and different +need_defer values will be passed to these callers: + +1) release the reference of the old element in the map during map update + or map deletion. The release must be deferred, otherwise the bpf + program may incur use-after-free problem, so need_defer needs to be + true. +2) release the reference of the to-be-added element in the error path of + map update. The to-be-added element is not visible to any bpf + program, so it is OK to pass false for need_defer parameter. +3) release the references of all elements in the map during map release. + Any bpf program which has access to the map must have been exited and + released, so need_defer=false will be OK. + +These two parameters will be used by the following patches to fix the +potential use-after-free problem for map-in-map. + +Signed-off-by: Hou Tao +Link: https://lore.kernel.org/r/20231204140425.1480317-3-houtao@huaweicloud.com +Signed-off-by: Alexei Starovoitov +Stable-dep-of: 876673364161 ("bpf: Defer the free of inner map when necessary") +Signed-off-by: Sasha Levin +--- + include/linux/bpf.h | 6 +++++- + kernel/bpf/arraymap.c | 12 +++++++----- + kernel/bpf/hashtab.c | 6 +++--- + kernel/bpf/map_in_map.c | 2 +- + kernel/bpf/map_in_map.h | 2 +- + 5 files changed, 17 insertions(+), 11 deletions(-) + +diff --git a/include/linux/bpf.h b/include/linux/bpf.h +index cff5bb08820e..741af9e5cb9d 100644 +--- a/include/linux/bpf.h ++++ b/include/linux/bpf.h +@@ -106,7 +106,11 @@ struct bpf_map_ops { + /* funcs called by prog_array and perf_event_array map */ + void *(*map_fd_get_ptr)(struct bpf_map *map, struct file *map_file, + int fd); +- void (*map_fd_put_ptr)(void *ptr); ++ /* If need_defer is true, the implementation should guarantee that ++ * the to-be-put element is still alive before the bpf program, which ++ * may manipulate it, exists. ++ */ ++ void (*map_fd_put_ptr)(struct bpf_map *map, void *ptr, bool need_defer); + int (*map_gen_lookup)(struct bpf_map *map, struct bpf_insn *insn_buf); + u32 (*map_fd_sys_lookup_elem)(void *ptr); + void (*map_seq_show_elem)(struct bpf_map *map, void *key, +diff --git a/kernel/bpf/arraymap.c b/kernel/bpf/arraymap.c +index c85ff9162a5c..9bfad7e96913 100644 +--- a/kernel/bpf/arraymap.c ++++ b/kernel/bpf/arraymap.c +@@ -867,7 +867,7 @@ int bpf_fd_array_map_update_elem(struct bpf_map *map, struct file *map_file, + } + + if (old_ptr) +- map->ops->map_fd_put_ptr(old_ptr); ++ map->ops->map_fd_put_ptr(map, old_ptr, true); + return 0; + } + +@@ -890,7 +890,7 @@ static long fd_array_map_delete_elem(struct bpf_map *map, void *key) + } + + if (old_ptr) { +- map->ops->map_fd_put_ptr(old_ptr); ++ map->ops->map_fd_put_ptr(map, old_ptr, true); + return 0; + } else { + return -ENOENT; +@@ -913,8 +913,9 @@ static void *prog_fd_array_get_ptr(struct bpf_map *map, + return prog; + } + +-static void prog_fd_array_put_ptr(void *ptr) ++static void prog_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { ++ /* bpf_prog is freed after one RCU or tasks trace grace period */ + bpf_prog_put(ptr); + } + +@@ -1201,8 +1202,9 @@ static void *perf_event_fd_array_get_ptr(struct bpf_map *map, + return ee; + } + +-static void perf_event_fd_array_put_ptr(void *ptr) ++static void perf_event_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { ++ /* bpf_perf_event is freed after one RCU grace period */ + bpf_event_entry_free_rcu(ptr); + } + +@@ -1256,7 +1258,7 @@ static void *cgroup_fd_array_get_ptr(struct bpf_map *map, + return cgroup_get_from_fd(fd); + } + +-static void cgroup_fd_array_put_ptr(void *ptr) ++static void cgroup_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { + /* cgroup_put free cgrp after a rcu grace period */ + cgroup_put(ptr); +diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c +index fd8d4b0addfc..5b9146fa825f 100644 +--- a/kernel/bpf/hashtab.c ++++ b/kernel/bpf/hashtab.c +@@ -897,7 +897,7 @@ static void htab_put_fd_value(struct bpf_htab *htab, struct htab_elem *l) + + if (map->ops->map_fd_put_ptr) { + ptr = fd_htab_map_get_ptr(map, l); +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, true); + } + } + +@@ -2484,7 +2484,7 @@ static void fd_htab_map_free(struct bpf_map *map) + hlist_nulls_for_each_entry_safe(l, n, head, hash_node) { + void *ptr = fd_htab_map_get_ptr(map, l); + +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, false); + } + } + +@@ -2525,7 +2525,7 @@ int bpf_fd_htab_map_update_elem(struct bpf_map *map, struct file *map_file, + + ret = htab_map_update_elem(map, key, &ptr, map_flags); + if (ret) +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, false); + + return ret; + } +diff --git a/kernel/bpf/map_in_map.c b/kernel/bpf/map_in_map.c +index cd5eafaba97e..2dfeb5835e16 100644 +--- a/kernel/bpf/map_in_map.c ++++ b/kernel/bpf/map_in_map.c +@@ -127,7 +127,7 @@ void *bpf_map_fd_get_ptr(struct bpf_map *map, + return inner_map; + } + +-void bpf_map_fd_put_ptr(void *ptr) ++void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { + /* ptr->ops->map_free() has to go through one + * rcu grace period by itself. +diff --git a/kernel/bpf/map_in_map.h b/kernel/bpf/map_in_map.h +index bcb7534afb3c..7d61602354de 100644 +--- a/kernel/bpf/map_in_map.h ++++ b/kernel/bpf/map_in_map.h +@@ -13,7 +13,7 @@ struct bpf_map *bpf_map_meta_alloc(int inner_map_ufd); + void bpf_map_meta_free(struct bpf_map *map_meta); + void *bpf_map_fd_get_ptr(struct bpf_map *map, struct file *map_file, + int ufd); +-void bpf_map_fd_put_ptr(void *ptr); ++void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer); + u32 bpf_map_fd_sys_lookup_elem(void *ptr); + + #endif +-- +2.43.0 + diff --git a/queue-6.7/bpf-defer-the-free-of-inner-map-when-necessary.patch b/queue-6.7/bpf-defer-the-free-of-inner-map-when-necessary.patch new file mode 100644 index 00000000000..8d28a26bcb9 --- /dev/null +++ b/queue-6.7/bpf-defer-the-free-of-inner-map-when-necessary.patch @@ -0,0 +1,141 @@ +From e613ce91a6ad0a8b9fe435c18e78a602d1585b2c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 22:04:22 +0800 +Subject: bpf: Defer the free of inner map when necessary + +From: Hou Tao + +[ Upstream commit 876673364161da50eed6b472d746ef88242b2368 ] + +When updating or deleting an inner map in map array or map htab, the map +may still be accessed by non-sleepable program or sleepable program. +However bpf_map_fd_put_ptr() decreases the ref-counter of the inner map +directly through bpf_map_put(), if the ref-counter is the last one +(which is true for most cases), the inner map will be freed by +ops->map_free() in a kworker. But for now, most .map_free() callbacks +don't use synchronize_rcu() or its variants to wait for the elapse of a +RCU grace period, so after the invocation of ops->map_free completes, +the bpf program which is accessing the inner map may incur +use-after-free problem. + +Fix the free of inner map by invoking bpf_map_free_deferred() after both +one RCU grace period and one tasks trace RCU grace period if the inner +map has been removed from the outer map before. The deferment is +accomplished by using call_rcu() or call_rcu_tasks_trace() when +releasing the last ref-counter of bpf map. The newly-added rcu_head +field in bpf_map shares the same storage space with work field to +reduce the size of bpf_map. + +Fixes: bba1dc0b55ac ("bpf: Remove redundant synchronize_rcu.") +Fixes: 638e4b825d52 ("bpf: Allows per-cpu maps and map-in-map in sleepable programs") +Signed-off-by: Hou Tao +Link: https://lore.kernel.org/r/20231204140425.1480317-5-houtao@huaweicloud.com +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + include/linux/bpf.h | 7 ++++++- + kernel/bpf/map_in_map.c | 11 ++++++++--- + kernel/bpf/syscall.c | 32 +++++++++++++++++++++++++++----- + 3 files changed, 41 insertions(+), 9 deletions(-) + +diff --git a/include/linux/bpf.h b/include/linux/bpf.h +index 741af9e5cb9d..7a7859a5cce4 100644 +--- a/include/linux/bpf.h ++++ b/include/linux/bpf.h +@@ -276,7 +276,11 @@ struct bpf_map { + */ + atomic64_t refcnt ____cacheline_aligned; + atomic64_t usercnt; +- struct work_struct work; ++ /* rcu is used before freeing and work is only used during freeing */ ++ union { ++ struct work_struct work; ++ struct rcu_head rcu; ++ }; + struct mutex freeze_mutex; + atomic64_t writecnt; + /* 'Ownership' of program-containing map is claimed by the first program +@@ -292,6 +296,7 @@ struct bpf_map { + } owner; + bool bypass_spec_v1; + bool frozen; /* write-once; write-protected by freeze_mutex */ ++ bool free_after_mult_rcu_gp; + s64 __percpu *elem_count; + }; + +diff --git a/kernel/bpf/map_in_map.c b/kernel/bpf/map_in_map.c +index 2dfeb5835e16..3248ff5d8161 100644 +--- a/kernel/bpf/map_in_map.c ++++ b/kernel/bpf/map_in_map.c +@@ -129,10 +129,15 @@ void *bpf_map_fd_get_ptr(struct bpf_map *map, + + void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { +- /* ptr->ops->map_free() has to go through one +- * rcu grace period by itself. ++ struct bpf_map *inner_map = ptr; ++ ++ /* The inner map may still be used by both non-sleepable and sleepable ++ * bpf program, so free it after one RCU grace period and one tasks ++ * trace RCU grace period. + */ +- bpf_map_put(ptr); ++ if (need_defer) ++ WRITE_ONCE(inner_map->free_after_mult_rcu_gp, true); ++ bpf_map_put(inner_map); + } + + u32 bpf_map_fd_sys_lookup_elem(void *ptr) +diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c +index 0ed286b8a0f0..c6579067eeea 100644 +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -719,6 +719,28 @@ static void bpf_map_put_uref(struct bpf_map *map) + } + } + ++static void bpf_map_free_in_work(struct bpf_map *map) ++{ ++ INIT_WORK(&map->work, bpf_map_free_deferred); ++ /* Avoid spawning kworkers, since they all might contend ++ * for the same mutex like slab_mutex. ++ */ ++ queue_work(system_unbound_wq, &map->work); ++} ++ ++static void bpf_map_free_rcu_gp(struct rcu_head *rcu) ++{ ++ bpf_map_free_in_work(container_of(rcu, struct bpf_map, rcu)); ++} ++ ++static void bpf_map_free_mult_rcu_gp(struct rcu_head *rcu) ++{ ++ if (rcu_trace_implies_rcu_gp()) ++ bpf_map_free_rcu_gp(rcu); ++ else ++ call_rcu(rcu, bpf_map_free_rcu_gp); ++} ++ + /* decrement map refcnt and schedule it for freeing via workqueue + * (underlying map implementation ops->map_free() might sleep) + */ +@@ -728,11 +750,11 @@ void bpf_map_put(struct bpf_map *map) + /* bpf_map_free_id() must be called first */ + bpf_map_free_id(map); + btf_put(map->btf); +- INIT_WORK(&map->work, bpf_map_free_deferred); +- /* Avoid spawning kworkers, since they all might contend +- * for the same mutex like slab_mutex. +- */ +- queue_work(system_unbound_wq, &map->work); ++ ++ if (READ_ONCE(map->free_after_mult_rcu_gp)) ++ call_rcu_tasks_trace(&map->rcu, bpf_map_free_mult_rcu_gp); ++ else ++ bpf_map_free_in_work(map); + } + } + EXPORT_SYMBOL_GPL(bpf_map_put); +-- +2.43.0 + diff --git a/queue-6.7/bpf-enforce-precision-of-r0-on-callback-return.patch b/queue-6.7/bpf-enforce-precision-of-r0-on-callback-return.patch new file mode 100644 index 00000000000..986d00555f9 --- /dev/null +++ b/queue-6.7/bpf-enforce-precision-of-r0-on-callback-return.patch @@ -0,0 +1,46 @@ +From afa32f21c2d00dd6bac0993a250fc1b1fb8a364f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 09:56:57 -0800 +Subject: bpf: enforce precision of R0 on callback return + +From: Andrii Nakryiko + +[ Upstream commit 0acd03a5bd188b0c501d285d938439618bd855c4 ] + +Given verifier checks actual value, r0 has to be precise, so we need to +propagate precision properly. r0 also has to be marked as read, +otherwise subsequent state comparisons will ignore such register as +unimportant and precision won't really help here. + +Fixes: 69c087ba6225 ("bpf: Add bpf_for_each_map_elem() helper") +Acked-by: Eduard Zingerman +Acked-by: Shung-Hsi Yu +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/r/20231202175705.885270-4-andrii@kernel.org +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index af2819d5c8ee..4d59b200e898 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -9829,6 +9829,13 @@ static int prepare_func_exit(struct bpf_verifier_env *env, int *insn_idx) + verbose(env, "R0 not a scalar value\n"); + return -EACCES; + } ++ ++ /* we are going to rely on register's precise value */ ++ err = mark_reg_read(env, r0, r0->parent, REG_LIVE_READ64); ++ err = err ?: mark_chain_precision(env, BPF_REG_0); ++ if (err) ++ return err; ++ + if (!tnum_in(range, r0->var_off)) { + verbose_invalid_scalar(env, r0, &range, "callback return", "R0"); + return -EINVAL; +-- +2.43.0 + diff --git a/queue-6.7/bpf-fix-a-race-condition-between-btf_put-and-map_fre.patch b/queue-6.7/bpf-fix-a-race-condition-between-btf_put-and-map_fre.patch new file mode 100644 index 00000000000..d1c3d4e5dd3 --- /dev/null +++ b/queue-6.7/bpf-fix-a-race-condition-between-btf_put-and-map_fre.patch @@ -0,0 +1,211 @@ +From 5da5fd42dafc31b578835cd93e37d17cc2e2951a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 12:38:15 -0800 +Subject: bpf: Fix a race condition between btf_put() and map_free() + +From: Yonghong Song + +[ Upstream commit 59e5791f59dd83e8aa72a4e74217eabb6e8cfd90 ] + +When running `./test_progs -j` in my local vm with latest kernel, +I once hit a kasan error like below: + + [ 1887.184724] BUG: KASAN: slab-use-after-free in bpf_rb_root_free+0x1f8/0x2b0 + [ 1887.185599] Read of size 4 at addr ffff888106806910 by task kworker/u12:2/2830 + [ 1887.186498] + [ 1887.186712] CPU: 3 PID: 2830 Comm: kworker/u12:2 Tainted: G OEL 6.7.0-rc3-00699-g90679706d486-dirty #494 + [ 1887.188034] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014 + [ 1887.189618] Workqueue: events_unbound bpf_map_free_deferred + [ 1887.190341] Call Trace: + [ 1887.190666] + [ 1887.190949] dump_stack_lvl+0xac/0xe0 + [ 1887.191423] ? nf_tcp_handle_invalid+0x1b0/0x1b0 + [ 1887.192019] ? panic+0x3c0/0x3c0 + [ 1887.192449] print_report+0x14f/0x720 + [ 1887.192930] ? preempt_count_sub+0x1c/0xd0 + [ 1887.193459] ? __virt_addr_valid+0xac/0x120 + [ 1887.194004] ? bpf_rb_root_free+0x1f8/0x2b0 + [ 1887.194572] kasan_report+0xc3/0x100 + [ 1887.195085] ? bpf_rb_root_free+0x1f8/0x2b0 + [ 1887.195668] bpf_rb_root_free+0x1f8/0x2b0 + [ 1887.196183] ? __bpf_obj_drop_impl+0xb0/0xb0 + [ 1887.196736] ? preempt_count_sub+0x1c/0xd0 + [ 1887.197270] ? preempt_count_sub+0x1c/0xd0 + [ 1887.197802] ? _raw_spin_unlock+0x1f/0x40 + [ 1887.198319] bpf_obj_free_fields+0x1d4/0x260 + [ 1887.198883] array_map_free+0x1a3/0x260 + [ 1887.199380] bpf_map_free_deferred+0x7b/0xe0 + [ 1887.199943] process_scheduled_works+0x3a2/0x6c0 + [ 1887.200549] worker_thread+0x633/0x890 + [ 1887.201047] ? __kthread_parkme+0xd7/0xf0 + [ 1887.201574] ? kthread+0x102/0x1d0 + [ 1887.202020] kthread+0x1ab/0x1d0 + [ 1887.202447] ? pr_cont_work+0x270/0x270 + [ 1887.202954] ? kthread_blkcg+0x50/0x50 + [ 1887.203444] ret_from_fork+0x34/0x50 + [ 1887.203914] ? kthread_blkcg+0x50/0x50 + [ 1887.204397] ret_from_fork_asm+0x11/0x20 + [ 1887.204913] + [ 1887.204913] + [ 1887.205209] + [ 1887.205416] Allocated by task 2197: + [ 1887.205881] kasan_set_track+0x3f/0x60 + [ 1887.206366] __kasan_kmalloc+0x6e/0x80 + [ 1887.206856] __kmalloc+0xac/0x1a0 + [ 1887.207293] btf_parse_fields+0xa15/0x1480 + [ 1887.207836] btf_parse_struct_metas+0x566/0x670 + [ 1887.208387] btf_new_fd+0x294/0x4d0 + [ 1887.208851] __sys_bpf+0x4ba/0x600 + [ 1887.209292] __x64_sys_bpf+0x41/0x50 + [ 1887.209762] do_syscall_64+0x4c/0xf0 + [ 1887.210222] entry_SYSCALL_64_after_hwframe+0x63/0x6b + [ 1887.210868] + [ 1887.211074] Freed by task 36: + [ 1887.211460] kasan_set_track+0x3f/0x60 + [ 1887.211951] kasan_save_free_info+0x28/0x40 + [ 1887.212485] ____kasan_slab_free+0x101/0x180 + [ 1887.213027] __kmem_cache_free+0xe4/0x210 + [ 1887.213514] btf_free+0x5b/0x130 + [ 1887.213918] rcu_core+0x638/0xcc0 + [ 1887.214347] __do_softirq+0x114/0x37e + +The error happens at bpf_rb_root_free+0x1f8/0x2b0: + + 00000000000034c0 : + ; { + 34c0: f3 0f 1e fa endbr64 + 34c4: e8 00 00 00 00 callq 0x34c9 + 34c9: 55 pushq %rbp + 34ca: 48 89 e5 movq %rsp, %rbp + ... + ; if (rec && rec->refcount_off >= 0 && + 36aa: 4d 85 ed testq %r13, %r13 + 36ad: 74 a9 je 0x3658 + 36af: 49 8d 7d 10 leaq 0x10(%r13), %rdi + 36b3: e8 00 00 00 00 callq 0x36b8 + <==== kasan function + 36b8: 45 8b 7d 10 movl 0x10(%r13), %r15d + <==== use-after-free load + 36bc: 45 85 ff testl %r15d, %r15d + 36bf: 78 8c js 0x364d + +So the problem is at rec->refcount_off in the above. + +I did some source code analysis and find the reason. + CPU A CPU B + bpf_map_put: + ... + btf_put with rcu callback + ... + bpf_map_free_deferred + with system_unbound_wq + ... ... ... + ... btf_free_rcu: ... + ... ... bpf_map_free_deferred: + ... ... + ... ---------> btf_struct_metas_free() + ... | race condition ... + ... ---------> map->ops->map_free() + ... + ... btf->struct_meta_tab = NULL + +In the above, map_free() corresponds to array_map_free() and eventually +calling bpf_rb_root_free() which calls: + ... + __bpf_obj_drop_impl(obj, field->graph_root.value_rec, false); + ... + +Here, 'value_rec' is assigned in btf_check_and_fixup_fields() with following code: + + meta = btf_find_struct_meta(btf, btf_id); + if (!meta) + return -EFAULT; + rec->fields[i].graph_root.value_rec = meta->record; + +So basically, 'value_rec' is a pointer to the record in struct_metas_tab. +And it is possible that that particular record has been freed by +btf_struct_metas_free() and hence we have a kasan error here. + +Actually it is very hard to reproduce the failure with current bpf/bpf-next +code, I only got the above error once. To increase reproducibility, I added +a delay in bpf_map_free_deferred() to delay map->ops->map_free(), which +significantly increased reproducibility. + + diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c + index 5e43ddd1b83f..aae5b5213e93 100644 + --- a/kernel/bpf/syscall.c + +++ b/kernel/bpf/syscall.c + @@ -695,6 +695,7 @@ static void bpf_map_free_deferred(struct work_struct *work) + struct bpf_map *map = container_of(work, struct bpf_map, work); + struct btf_record *rec = map->record; + + + mdelay(100); + security_bpf_map_free(map); + bpf_map_release_memcg(map); + /* implementation dependent freeing */ + +Hao also provided test cases ([1]) for easily reproducing the above issue. + +There are two ways to fix the issue, the v1 of the patch ([2]) moving +btf_put() after map_free callback, and the v5 of the patch ([3]) using +a kptr style fix which tries to get a btf reference during +map_check_btf(). Each approach has its pro and cons. The first approach +delays freeing btf while the second approach needs to acquire reference +depending on context which makes logic not very elegant and may +complicate things with future new data structures. Alexei +suggested in [4] going back to v1 which is what this patch +tries to do. + +Rerun './test_progs -j' with the above mdelay() hack for a couple +of times and didn't observe the error for the above rb_root test cases. +Running Hou's test ([1]) is also successful. + + [1] https://lore.kernel.org/bpf/20231207141500.917136-1-houtao@huaweicloud.com/ + [2] v1: https://lore.kernel.org/bpf/20231204173946.3066377-1-yonghong.song@linux.dev/ + [3] v5: https://lore.kernel.org/bpf/20231208041621.2968241-1-yonghong.song@linux.dev/ + [4] v4: https://lore.kernel.org/bpf/CAADnVQJ3FiXUhZJwX_81sjZvSYYKCFB3BT6P8D59RS2Gu+0Z7g@mail.gmail.com/ + +Cc: Hou Tao +Fixes: 958cf2e273f0 ("bpf: Introduce bpf_obj_new") +Signed-off-by: Yonghong Song +Link: https://lore.kernel.org/r/20231214203815.1469107-1-yonghong.song@linux.dev +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/syscall.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c +index c6579067eeea..6e7e57360b81 100644 +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -694,6 +694,7 @@ static void bpf_map_free_deferred(struct work_struct *work) + { + struct bpf_map *map = container_of(work, struct bpf_map, work); + struct btf_record *rec = map->record; ++ struct btf *btf = map->btf; + + security_bpf_map_free(map); + bpf_map_release_memcg(map); +@@ -709,6 +710,10 @@ static void bpf_map_free_deferred(struct work_struct *work) + * template bpf_map struct used during verification. + */ + btf_record_free(rec); ++ /* Delay freeing of btf for maps, as map_free callback may need ++ * struct_meta info which will be freed with btf_put(). ++ */ ++ btf_put(btf); + } + + static void bpf_map_put_uref(struct bpf_map *map) +@@ -749,7 +754,6 @@ void bpf_map_put(struct bpf_map *map) + if (atomic64_dec_and_test(&map->refcnt)) { + /* bpf_map_free_id() must be called first */ + bpf_map_free_id(map); +- btf_put(map->btf); + + if (READ_ONCE(map->free_after_mult_rcu_gp)) + call_rcu_tasks_trace(&map->rcu, bpf_map_free_mult_rcu_gp); +-- +2.43.0 + diff --git a/queue-6.7/bpf-fix-accesses-to-uninit-stack-slots.patch b/queue-6.7/bpf-fix-accesses-to-uninit-stack-slots.patch new file mode 100644 index 00000000000..03228e9b11e --- /dev/null +++ b/queue-6.7/bpf-fix-accesses-to-uninit-stack-slots.patch @@ -0,0 +1,470 @@ +From 7c46217ca064428b4423a3b9a0cb0cf24be1657f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Dec 2023 22:25:18 -0500 +Subject: bpf: Fix accesses to uninit stack slots + +From: Andrei Matei + +[ Upstream commit 6b4a64bafd107e521c01eec3453ce94a3fb38529 ] + +Privileged programs are supposed to be able to read uninitialized stack +memory (ever since 6715df8d5) but, before this patch, these accesses +were permitted inconsistently. In particular, accesses were permitted +above state->allocated_stack, but not below it. In other words, if the +stack was already "large enough", the access was permitted, but +otherwise the access was rejected instead of being allowed to "grow the +stack". This undesired rejection was happening in two places: +- in check_stack_slot_within_bounds() +- in check_stack_range_initialized() +This patch arranges for these accesses to be permitted. A bunch of tests +that were relying on the old rejection had to change; all of them were +changed to add also run unprivileged, in which case the old behavior +persists. One tests couldn't be updated - global_func16 - because it +can't run unprivileged for other reasons. + +This patch also fixes the tracking of the stack size for variable-offset +reads. This second fix is bundled in the same commit as the first one +because they're inter-related. Before this patch, writes to the stack +using registers containing a variable offset (as opposed to registers +with fixed, known values) were not properly contributing to the +function's needed stack size. As a result, it was possible for a program +to verify, but then to attempt to read out-of-bounds data at runtime +because a too small stack had been allocated for it. + +Each function tracks the size of the stack it needs in +bpf_subprog_info.stack_depth, which is maintained by +update_stack_depth(). For regular memory accesses, check_mem_access() +was calling update_state_depth() but it was passing in only the fixed +part of the offset register, ignoring the variable offset. This was +incorrect; the minimum possible value of that register should be used +instead. + +This tracking is now fixed by centralizing the tracking of stack size in +grow_stack_state(), and by lifting the calls to grow_stack_state() to +check_stack_access_within_bounds() as suggested by Andrii. The code is +now simpler and more convincingly tracks the correct maximum stack size. +check_stack_range_initialized() can now rely on enough stack having been +allocated for the access; this helps with the fix for the first issue. + +A few tests were changed to also check the stack depth computation. The +one that fails without this patch is verifier_var_off:stack_write_priv_vs_unpriv. + +Fixes: 01f810ace9ed3 ("bpf: Allow variable-offset stack access") +Reported-by: Hao Sun +Signed-off-by: Andrei Matei +Signed-off-by: Andrii Nakryiko +Acked-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231208032519.260451-3-andreimatei1@gmail.com + +Closes: https://lore.kernel.org/bpf/CABWLsev9g8UP_c3a=1qbuZUi20tGoUXoU07FPf-5FLvhOKOY+Q@mail.gmail.com/ +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 65 ++++++++----------- + tools/testing/selftests/bpf/progs/iters.c | 2 +- + .../selftests/bpf/progs/test_global_func16.c | 2 +- + .../bpf/progs/verifier_basic_stack.c | 8 +-- + .../selftests/bpf/progs/verifier_int_ptr.c | 5 +- + .../selftests/bpf/progs/verifier_raw_stack.c | 5 +- + .../selftests/bpf/progs/verifier_var_off.c | 62 ++++++++++++++---- + .../selftests/bpf/verifier/atomic_cmpxchg.c | 11 ---- + tools/testing/selftests/bpf/verifier/calls.c | 4 +- + 9 files changed, 92 insertions(+), 72 deletions(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index 4d91df312b99..2b8fbdc1a113 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -1685,7 +1685,10 @@ static int resize_reference_state(struct bpf_func_state *state, size_t n) + return 0; + } + +-static int grow_stack_state(struct bpf_func_state *state, int size) ++/* Possibly update state->allocated_stack to be at least size bytes. Also ++ * possibly update the function's high-water mark in its bpf_subprog_info. ++ */ ++static int grow_stack_state(struct bpf_verifier_env *env, struct bpf_func_state *state, int size) + { + size_t old_n = state->allocated_stack / BPF_REG_SIZE, n = size / BPF_REG_SIZE; + +@@ -1697,6 +1700,11 @@ static int grow_stack_state(struct bpf_func_state *state, int size) + return -ENOMEM; + + state->allocated_stack = size; ++ ++ /* update known max for given subprogram */ ++ if (env->subprog_info[state->subprogno].stack_depth < size) ++ env->subprog_info[state->subprogno].stack_depth = size; ++ + return 0; + } + +@@ -4669,9 +4677,6 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, + struct bpf_reg_state *reg = NULL; + u32 dst_reg = insn->dst_reg; + +- err = grow_stack_state(state, round_up(slot + 1, BPF_REG_SIZE)); +- if (err) +- return err; + /* caller checked that off % size == 0 and -MAX_BPF_STACK <= off < 0, + * so it's aligned access and [off, off + size) are within stack limits + */ +@@ -4827,10 +4832,6 @@ static int check_stack_write_var_off(struct bpf_verifier_env *env, + (!value_reg && is_bpf_st_mem(insn) && insn->imm == 0)) + writing_zero = true; + +- err = grow_stack_state(state, round_up(-min_off, BPF_REG_SIZE)); +- if (err) +- return err; +- + for (i = min_off; i < max_off; i++) { + int spi; + +@@ -5959,20 +5960,6 @@ static int check_ptr_alignment(struct bpf_verifier_env *env, + strict); + } + +-static int update_stack_depth(struct bpf_verifier_env *env, +- const struct bpf_func_state *func, +- int off) +-{ +- u16 stack = env->subprog_info[func->subprogno].stack_depth; +- +- if (stack >= -off) +- return 0; +- +- /* update known max for given subprogram */ +- env->subprog_info[func->subprogno].stack_depth = -off; +- return 0; +-} +- + /* starting from main bpf function walk all instructions of the function + * and recursively walk all callees that given function can call. + * Ignore jump and exit insns. +@@ -6761,13 +6748,14 @@ static int check_ptr_to_map_access(struct bpf_verifier_env *env, + * The minimum valid offset is -MAX_BPF_STACK for writes, and + * -state->allocated_stack for reads. + */ +-static int check_stack_slot_within_bounds(s64 off, +- struct bpf_func_state *state, +- enum bpf_access_type t) ++static int check_stack_slot_within_bounds(struct bpf_verifier_env *env, ++ s64 off, ++ struct bpf_func_state *state, ++ enum bpf_access_type t) + { + int min_valid_off; + +- if (t == BPF_WRITE) ++ if (t == BPF_WRITE || env->allow_uninit_stack) + min_valid_off = -MAX_BPF_STACK; + else + min_valid_off = -state->allocated_stack; +@@ -6816,7 +6804,7 @@ static int check_stack_access_within_bounds( + max_off = reg->smax_value + off + access_size; + } + +- err = check_stack_slot_within_bounds(min_off, state, type); ++ err = check_stack_slot_within_bounds(env, min_off, state, type); + if (!err && max_off > 0) + err = -EINVAL; /* out of stack access into non-negative offsets */ + +@@ -6831,8 +6819,10 @@ static int check_stack_access_within_bounds( + verbose(env, "invalid variable-offset%s stack R%d var_off=%s size=%d\n", + err_extra, regno, tn_buf, access_size); + } ++ return err; + } +- return err; ++ ++ return grow_stack_state(env, state, round_up(-min_off, BPF_REG_SIZE)); + } + + /* check whether memory at (regno + off) is accessible for t = (read | write) +@@ -6847,7 +6837,6 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn + { + struct bpf_reg_state *regs = cur_regs(env); + struct bpf_reg_state *reg = regs + regno; +- struct bpf_func_state *state; + int size, err = 0; + + size = bpf_size_to_bytes(bpf_size); +@@ -6990,11 +6979,6 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn + if (err) + return err; + +- state = func(env, reg); +- err = update_stack_depth(env, state, off); +- if (err) +- return err; +- + if (t == BPF_READ) + err = check_stack_read(env, regno, off, size, + value_regno); +@@ -7189,7 +7173,8 @@ static int check_atomic(struct bpf_verifier_env *env, int insn_idx, struct bpf_i + + /* When register 'regno' is used to read the stack (either directly or through + * a helper function) make sure that it's within stack boundary and, depending +- * on the access type, that all elements of the stack are initialized. ++ * on the access type and privileges, that all elements of the stack are ++ * initialized. + * + * 'off' includes 'regno->off', but not its dynamic part (if any). + * +@@ -7297,8 +7282,11 @@ static int check_stack_range_initialized( + + slot = -i - 1; + spi = slot / BPF_REG_SIZE; +- if (state->allocated_stack <= slot) +- goto err; ++ if (state->allocated_stack <= slot) { ++ verbose(env, "verifier bug: allocated_stack too small"); ++ return -EFAULT; ++ } ++ + stype = &state->stack[spi].slot_type[slot % BPF_REG_SIZE]; + if (*stype == STACK_MISC) + goto mark; +@@ -7322,7 +7310,6 @@ static int check_stack_range_initialized( + goto mark; + } + +-err: + if (tnum_is_const(reg->var_off)) { + verbose(env, "invalid%s read from stack R%d off %d+%d size %d\n", + err_extra, regno, min_off, i - min_off, access_size); +@@ -7347,7 +7334,7 @@ static int check_stack_range_initialized( + * helper may write to the entire memory range. + */ + } +- return update_stack_depth(env, state, min_off); ++ return 0; + } + + static int check_helper_mem_access(struct bpf_verifier_env *env, int regno, +diff --git a/tools/testing/selftests/bpf/progs/iters.c b/tools/testing/selftests/bpf/progs/iters.c +index c20c4e38b71c..844d968c27d6 100644 +--- a/tools/testing/selftests/bpf/progs/iters.c ++++ b/tools/testing/selftests/bpf/progs/iters.c +@@ -846,7 +846,7 @@ __naked int delayed_precision_mark(void) + "call %[bpf_iter_num_next];" + "if r0 == 0 goto 2f;" + "if r6 != 42 goto 3f;" +- "r7 = -32;" ++ "r7 = -33;" + "call %[bpf_get_prandom_u32];" + "r6 = r0;" + "goto 1b;\n" +diff --git a/tools/testing/selftests/bpf/progs/test_global_func16.c b/tools/testing/selftests/bpf/progs/test_global_func16.c +index e7206304632e..e3e64bc472cd 100644 +--- a/tools/testing/selftests/bpf/progs/test_global_func16.c ++++ b/tools/testing/selftests/bpf/progs/test_global_func16.c +@@ -13,7 +13,7 @@ __noinline int foo(int (*arr)[10]) + } + + SEC("cgroup_skb/ingress") +-__failure __msg("invalid indirect read from stack") ++__success + int global_func16(struct __sk_buff *skb) + { + int array[10]; +diff --git a/tools/testing/selftests/bpf/progs/verifier_basic_stack.c b/tools/testing/selftests/bpf/progs/verifier_basic_stack.c +index 359df865a8f3..8d77cc5323d3 100644 +--- a/tools/testing/selftests/bpf/progs/verifier_basic_stack.c ++++ b/tools/testing/selftests/bpf/progs/verifier_basic_stack.c +@@ -27,8 +27,8 @@ __naked void stack_out_of_bounds(void) + + SEC("socket") + __description("uninitialized stack1") +-__failure __msg("invalid indirect read from stack") +-__failure_unpriv ++__success __log_level(4) __msg("stack depth 8") ++__failure_unpriv __msg_unpriv("invalid indirect read from stack") + __naked void uninitialized_stack1(void) + { + asm volatile (" \ +@@ -45,8 +45,8 @@ __naked void uninitialized_stack1(void) + + SEC("socket") + __description("uninitialized stack2") +-__failure __msg("invalid read from stack") +-__failure_unpriv ++__success __log_level(4) __msg("stack depth 8") ++__failure_unpriv __msg_unpriv("invalid read from stack") + __naked void uninitialized_stack2(void) + { + asm volatile (" \ +diff --git a/tools/testing/selftests/bpf/progs/verifier_int_ptr.c b/tools/testing/selftests/bpf/progs/verifier_int_ptr.c +index b054f9c48143..589e8270de46 100644 +--- a/tools/testing/selftests/bpf/progs/verifier_int_ptr.c ++++ b/tools/testing/selftests/bpf/progs/verifier_int_ptr.c +@@ -5,9 +5,10 @@ + #include + #include "bpf_misc.h" + +-SEC("cgroup/sysctl") ++SEC("socket") + __description("ARG_PTR_TO_LONG uninitialized") +-__failure __msg("invalid indirect read from stack R4 off -16+0 size 8") ++__success ++__failure_unpriv __msg_unpriv("invalid indirect read from stack R4 off -16+0 size 8") + __naked void arg_ptr_to_long_uninitialized(void) + { + asm volatile (" \ +diff --git a/tools/testing/selftests/bpf/progs/verifier_raw_stack.c b/tools/testing/selftests/bpf/progs/verifier_raw_stack.c +index efbfc3a4ad6a..f67390224a9c 100644 +--- a/tools/testing/selftests/bpf/progs/verifier_raw_stack.c ++++ b/tools/testing/selftests/bpf/progs/verifier_raw_stack.c +@@ -5,9 +5,10 @@ + #include + #include "bpf_misc.h" + +-SEC("tc") ++SEC("socket") + __description("raw_stack: no skb_load_bytes") +-__failure __msg("invalid read from stack R6 off=-8 size=8") ++__success ++__failure_unpriv __msg_unpriv("invalid read from stack R6 off=-8 size=8") + __naked void stack_no_skb_load_bytes(void) + { + asm volatile (" \ +diff --git a/tools/testing/selftests/bpf/progs/verifier_var_off.c b/tools/testing/selftests/bpf/progs/verifier_var_off.c +index 83a90afba785..d1f23c1a7c5b 100644 +--- a/tools/testing/selftests/bpf/progs/verifier_var_off.c ++++ b/tools/testing/selftests/bpf/progs/verifier_var_off.c +@@ -59,9 +59,10 @@ __naked void stack_read_priv_vs_unpriv(void) + " ::: __clobber_all); + } + +-SEC("lwt_in") ++SEC("cgroup/skb") + __description("variable-offset stack read, uninitialized") +-__failure __msg("invalid variable-offset read from stack R2") ++__success ++__failure_unpriv __msg_unpriv("R2 variable stack access prohibited for !root") + __naked void variable_offset_stack_read_uninitialized(void) + { + asm volatile (" \ +@@ -83,12 +84,55 @@ __naked void variable_offset_stack_read_uninitialized(void) + + SEC("socket") + __description("variable-offset stack write, priv vs unpriv") +-__success __failure_unpriv ++__success ++/* Check that the maximum stack depth is correctly maintained according to the ++ * maximum possible variable offset. ++ */ ++__log_level(4) __msg("stack depth 16") ++__failure_unpriv + /* Variable stack access is rejected for unprivileged. + */ + __msg_unpriv("R2 variable stack access prohibited for !root") + __retval(0) + __naked void stack_write_priv_vs_unpriv(void) ++{ ++ asm volatile (" \ ++ /* Get an unknown value */ \ ++ r2 = *(u32*)(r1 + 0); \ ++ /* Make it small and 8-byte aligned */ \ ++ r2 &= 8; \ ++ r2 -= 16; \ ++ /* Add it to fp. We now have either fp-8 or \ ++ * fp-16, but we don't know which \ ++ */ \ ++ r2 += r10; \ ++ /* Dereference it for a stack write */ \ ++ r0 = 0; \ ++ *(u64*)(r2 + 0) = r0; \ ++ exit; \ ++" ::: __clobber_all); ++} ++ ++/* Similar to the previous test, but this time also perform a read from the ++ * address written to with a variable offset. The read is allowed, showing that, ++ * after a variable-offset write, a priviledged program can read the slots that ++ * were in the range of that write (even if the verifier doesn't actually know if ++ * the slot being read was really written to or not. ++ * ++ * Despite this test being mostly a superset, the previous test is also kept for ++ * the sake of it checking the stack depth in the case where there is no read. ++ */ ++SEC("socket") ++__description("variable-offset stack write followed by read") ++__success ++/* Check that the maximum stack depth is correctly maintained according to the ++ * maximum possible variable offset. ++ */ ++__log_level(4) __msg("stack depth 16") ++__failure_unpriv ++__msg_unpriv("R2 variable stack access prohibited for !root") ++__retval(0) ++__naked void stack_write_followed_by_read(void) + { + asm volatile (" \ + /* Get an unknown value */ \ +@@ -103,12 +147,7 @@ __naked void stack_write_priv_vs_unpriv(void) + /* Dereference it for a stack write */ \ + r0 = 0; \ + *(u64*)(r2 + 0) = r0; \ +- /* Now read from the address we just wrote. This shows\ +- * that, after a variable-offset write, a priviledged\ +- * program can read the slots that were in the range of\ +- * that write (even if the verifier doesn't actually know\ +- * if the slot being read was really written to or not.\ +- */ \ ++ /* Now read from the address we just wrote. */ \ + r3 = *(u64*)(r2 + 0); \ + r0 = 0; \ + exit; \ +@@ -253,9 +292,10 @@ __naked void access_min_out_of_bound(void) + : __clobber_all); + } + +-SEC("lwt_in") ++SEC("cgroup/skb") + __description("indirect variable-offset stack access, min_off < min_initialized") +-__failure __msg("invalid indirect read from stack R2 var_off") ++__success ++__failure_unpriv __msg_unpriv("R2 variable stack access prohibited for !root") + __naked void access_min_off_min_initialized(void) + { + asm volatile (" \ +diff --git a/tools/testing/selftests/bpf/verifier/atomic_cmpxchg.c b/tools/testing/selftests/bpf/verifier/atomic_cmpxchg.c +index 319337bdcfc8..9a7b1106fda8 100644 +--- a/tools/testing/selftests/bpf/verifier/atomic_cmpxchg.c ++++ b/tools/testing/selftests/bpf/verifier/atomic_cmpxchg.c +@@ -83,17 +83,6 @@ + .result = REJECT, + .errstr = "!read_ok", + }, +-{ +- "Can't use cmpxchg on uninit memory", +- .insns = { +- BPF_MOV64_IMM(BPF_REG_0, 3), +- BPF_MOV64_IMM(BPF_REG_2, 4), +- BPF_ATOMIC_OP(BPF_DW, BPF_CMPXCHG, BPF_REG_10, BPF_REG_2, -8), +- BPF_EXIT_INSN(), +- }, +- .result = REJECT, +- .errstr = "invalid read from stack", +-}, + { + "BPF_W cmpxchg should zero top 32 bits", + .insns = { +diff --git a/tools/testing/selftests/bpf/verifier/calls.c b/tools/testing/selftests/bpf/verifier/calls.c +index 3d5cd51071f0..ab25a81fd3a1 100644 +--- a/tools/testing/selftests/bpf/verifier/calls.c ++++ b/tools/testing/selftests/bpf/verifier/calls.c +@@ -1505,7 +1505,9 @@ + .prog_type = BPF_PROG_TYPE_XDP, + .fixup_map_hash_8b = { 23 }, + .result = REJECT, +- .errstr = "invalid read from stack R7 off=-16 size=8", ++ .errstr = "R0 invalid mem access 'scalar'", ++ .result_unpriv = REJECT, ++ .errstr_unpriv = "invalid read from stack R7 off=-16 size=8", + }, + { + "calls: two calls that receive map_value via arg=ptr_stack_of_caller. test1", +-- +2.43.0 + diff --git a/queue-6.7/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch b/queue-6.7/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch new file mode 100644 index 00000000000..e70667dd201 --- /dev/null +++ b/queue-6.7/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch @@ -0,0 +1,42 @@ +From a9538650a754acd07357a8d48e74264f420b77e1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 10:42:41 -0800 +Subject: bpf: fix check for attempt to corrupt spilled pointer + +From: Andrii Nakryiko + +[ Upstream commit ab125ed3ec1c10ccc36bc98c7a4256ad114a3dae ] + +When register is spilled onto a stack as a 1/2/4-byte register, we set +slot_type[BPF_REG_SIZE - 1] (plus potentially few more below it, +depending on actual spill size). So to check if some stack slot has +spilled register we need to consult slot_type[7], not slot_type[0]. + +To avoid the need to remember and double-check this in the future, just +use is_spilled_reg() helper. + +Fixes: 27113c59b6d0 ("bpf: Check the other end of slot_type for STACK_SPILL") +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/r/20231205184248.1502704-4-andrii@kernel.org +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index 4d59b200e898..c4fbfe499475 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -4676,7 +4676,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, + * so it's aligned access and [off, off + size) are within stack limits + */ + if (!env->allow_ptr_leaks && +- state->stack[spi].slot_type[0] == STACK_SPILL && ++ is_spilled_reg(&state->stack[spi]) && + size != BPF_REG_SIZE) { + verbose(env, "attempt to corrupt spilled pointer on stack\n"); + return -EACCES; +-- +2.43.0 + diff --git a/queue-6.7/bpf-fix-verification-of-indirect-var-off-stack-acces.patch b/queue-6.7/bpf-fix-verification-of-indirect-var-off-stack-acces.patch new file mode 100644 index 00000000000..cbab6933456 --- /dev/null +++ b/queue-6.7/bpf-fix-verification-of-indirect-var-off-stack-acces.patch @@ -0,0 +1,83 @@ +From 5149fd1ce8567a0f734bd2eb961442295903d0f5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Dec 2023 23:11:48 -0500 +Subject: bpf: Fix verification of indirect var-off stack access + +From: Andrei Matei + +[ Upstream commit a833a17aeac73b33f79433d7cee68d5cafd71e4f ] + +This patch fixes a bug around the verification of possibly-zero-sized +stack accesses. When the access was done through a var-offset stack +pointer, check_stack_access_within_bounds was incorrectly computing the +maximum-offset of a zero-sized read to be the same as the register's min +offset. Instead, we have to take in account the register's maximum +possible value. The patch also simplifies how the max offset is checked; +the check is now simpler than for min offset. + +The bug was allowing accesses to erroneously pass the +check_stack_access_within_bounds() checks, only to later crash in +check_stack_range_initialized() when all the possibly-affected stack +slots are iterated (this time with a correct max offset). +check_stack_range_initialized() is relying on +check_stack_access_within_bounds() for its accesses to the +stack-tracking vector to be within bounds; in the case of zero-sized +accesses, we were essentially only verifying that the lowest possible +slot was within bounds. We would crash when the max-offset of the stack +pointer was >= 0 (which shouldn't pass verification, and hopefully is +not something anyone's code attempts to do in practice). + +Thanks Hao for reporting! + +Fixes: 01f810ace9ed3 ("bpf: Allow variable-offset stack access") +Reported-by: Hao Sun +Signed-off-by: Andrei Matei +Signed-off-by: Andrii Nakryiko +Acked-by: Eduard Zingerman +Acked-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231207041150.229139-2-andreimatei1@gmail.com + +Closes: https://lore.kernel.org/bpf/CACkBjsZGEUaRCHsmaX=h-efVogsRfK1FPxmkgb0Os_frnHiNdw@mail.gmail.com/ +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 14 ++++---------- + 1 file changed, 4 insertions(+), 10 deletions(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index c4fbfe499475..acc1f3b7b183 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -6804,10 +6804,7 @@ static int check_stack_access_within_bounds( + + if (tnum_is_const(reg->var_off)) { + min_off = reg->var_off.value + off; +- if (access_size > 0) +- max_off = min_off + access_size - 1; +- else +- max_off = min_off; ++ max_off = min_off + access_size; + } else { + if (reg->smax_value >= BPF_MAX_VAR_OFF || + reg->smin_value <= -BPF_MAX_VAR_OFF) { +@@ -6816,15 +6813,12 @@ static int check_stack_access_within_bounds( + return -EACCES; + } + min_off = reg->smin_value + off; +- if (access_size > 0) +- max_off = reg->smax_value + off + access_size - 1; +- else +- max_off = min_off; ++ max_off = reg->smax_value + off + access_size; + } + + err = check_stack_slot_within_bounds(min_off, state, type); +- if (!err) +- err = check_stack_slot_within_bounds(max_off, state, type); ++ if (!err && max_off > 0) ++ err = -EINVAL; /* out of stack access into non-negative offsets */ + + if (err) { + if (tnum_is_const(reg->var_off)) { +-- +2.43.0 + diff --git a/queue-6.7/bpf-guard-stack-limits-against-32bit-overflow.patch b/queue-6.7/bpf-guard-stack-limits-against-32bit-overflow.patch new file mode 100644 index 00000000000..34e708380ab --- /dev/null +++ b/queue-6.7/bpf-guard-stack-limits-against-32bit-overflow.patch @@ -0,0 +1,69 @@ +From 5be67d9932c2ca93d7236b004f8c04306dcb7382 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Dec 2023 23:11:50 -0500 +Subject: bpf: Guard stack limits against 32bit overflow + +From: Andrei Matei + +[ Upstream commit 1d38a9ee81570c4bd61f557832dead4d6f816760 ] + +This patch promotes the arithmetic around checking stack bounds to be +done in the 64-bit domain, instead of the current 32bit. The arithmetic +implies adding together a 64-bit register with a int offset. The +register was checked to be below 1<<29 when it was variable, but not +when it was fixed. The offset either comes from an instruction (in which +case it is 16 bit), from another register (in which case the caller +checked it to be below 1<<29 [1]), or from the size of an argument to a +kfunc (in which case it can be a u32 [2]). Between the register being +inconsistently checked to be below 1<<29, and the offset being up to an +u32, it appears that we were open to overflowing the `int`s which were +currently used for arithmetic. + +[1] https://github.com/torvalds/linux/blob/815fb87b753055df2d9e50f6cd80eb10235fe3e9/kernel/bpf/verifier.c#L7494-L7498 +[2] https://github.com/torvalds/linux/blob/815fb87b753055df2d9e50f6cd80eb10235fe3e9/kernel/bpf/verifier.c#L11904 + +Reported-by: Andrii Nakryiko +Signed-off-by: Andrei Matei +Signed-off-by: Andrii Nakryiko +Acked-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231207041150.229139-4-andreimatei1@gmail.com +Stable-dep-of: 6b4a64bafd10 ("bpf: Fix accesses to uninit stack slots") +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index acc1f3b7b183..4d91df312b99 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -6761,7 +6761,7 @@ static int check_ptr_to_map_access(struct bpf_verifier_env *env, + * The minimum valid offset is -MAX_BPF_STACK for writes, and + * -state->allocated_stack for reads. + */ +-static int check_stack_slot_within_bounds(int off, ++static int check_stack_slot_within_bounds(s64 off, + struct bpf_func_state *state, + enum bpf_access_type t) + { +@@ -6790,7 +6790,7 @@ static int check_stack_access_within_bounds( + struct bpf_reg_state *regs = cur_regs(env); + struct bpf_reg_state *reg = regs + regno; + struct bpf_func_state *state = func(env, reg); +- int min_off, max_off; ++ s64 min_off, max_off; + int err; + char *err_extra; + +@@ -6803,7 +6803,7 @@ static int check_stack_access_within_bounds( + err_extra = " write to"; + + if (tnum_is_const(reg->var_off)) { +- min_off = reg->var_off.value + off; ++ min_off = (s64)reg->var_off.value + off; + max_off = min_off + access_size; + } else { + if (reg->smax_value >= BPF_MAX_VAR_OFF || +-- +2.43.0 + diff --git a/queue-6.7/bpf-limit-the-number-of-kprobes-when-attaching-progr.patch b/queue-6.7/bpf-limit-the-number-of-kprobes-when-attaching-progr.patch new file mode 100644 index 00000000000..4c0f6ba7e73 --- /dev/null +++ b/queue-6.7/bpf-limit-the-number-of-kprobes-when-attaching-progr.patch @@ -0,0 +1,58 @@ +From 0b8f106d824b660e8e373ee6942346b5cff9e846 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 18:07:05 +0800 +Subject: bpf: Limit the number of kprobes when attaching program to multiple + kprobes + +From: Hou Tao + +[ Upstream commit d6d1e6c17cab2dcb7b8530c599f00e7de906d380 ] + +An abnormally big cnt may also be assigned to kprobe_multi.cnt when +attaching multiple kprobes. It will trigger the following warning in +kvmalloc_node(): + + if (unlikely(size > INT_MAX)) { + WARN_ON_ONCE(!(flags & __GFP_NOWARN)); + return NULL; + } + +Fix the warning by limiting the maximal number of kprobes in +bpf_kprobe_multi_link_attach(). If the number of kprobes is greater than +MAX_KPROBE_MULTI_CNT, the attachment will fail and return -E2BIG. + +Fixes: 0dcac2725406 ("bpf: Add multi kprobe link") +Signed-off-by: Hou Tao +Signed-off-by: Daniel Borkmann +Acked-by: Jiri Olsa +Acked-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231215100708.2265609-3-houtao@huaweicloud.com +Signed-off-by: Sasha Levin +--- + kernel/trace/bpf_trace.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c +index 640b08818afa..652c40a14d0d 100644 +--- a/kernel/trace/bpf_trace.c ++++ b/kernel/trace/bpf_trace.c +@@ -42,6 +42,7 @@ + rcu_dereference_protected(p, lockdep_is_held(&bpf_event_mutex)) + + #define MAX_UPROBE_MULTI_CNT (1U << 20) ++#define MAX_KPROBE_MULTI_CNT (1U << 20) + + #ifdef CONFIG_MODULES + struct bpf_trace_module { +@@ -2901,6 +2902,8 @@ int bpf_kprobe_multi_link_attach(const union bpf_attr *attr, struct bpf_prog *pr + cnt = attr->link_create.kprobe_multi.cnt; + if (!cnt) + return -EINVAL; ++ if (cnt > MAX_KPROBE_MULTI_CNT) ++ return -E2BIG; + + size = cnt * sizeof(*addrs); + addrs = kvmalloc_array(cnt, sizeof(*addrs), GFP_KERNEL); +-- +2.43.0 + diff --git a/queue-6.7/bpf-limit-the-number-of-uprobes-when-attaching-progr.patch b/queue-6.7/bpf-limit-the-number-of-uprobes-when-attaching-progr.patch new file mode 100644 index 00000000000..e0b3f904815 --- /dev/null +++ b/queue-6.7/bpf-limit-the-number-of-uprobes-when-attaching-progr.patch @@ -0,0 +1,60 @@ +From 713a78dde5041277db8cf3058782f1183d602631 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 18:07:04 +0800 +Subject: bpf: Limit the number of uprobes when attaching program to multiple + uprobes + +From: Hou Tao + +[ Upstream commit 8b2efe51ba85ca83460941672afac6fca4199df6 ] + +An abnormally big cnt may be passed to link_create.uprobe_multi.cnt, +and it will trigger the following warning in kvmalloc_node(): + + if (unlikely(size > INT_MAX)) { + WARN_ON_ONCE(!(flags & __GFP_NOWARN)); + return NULL; + } + +Fix the warning by limiting the maximal number of uprobes in +bpf_uprobe_multi_link_attach(). If the number of uprobes is greater than +MAX_UPROBE_MULTI_CNT, the attachment will return -E2BIG. + +Fixes: 89ae89f53d20 ("bpf: Add multi uprobe link") +Reported-by: Xingwei Lee +Signed-off-by: Hou Tao +Signed-off-by: Daniel Borkmann +Acked-by: Jiri Olsa +Acked-by: Andrii Nakryiko +Closes: https://lore.kernel.org/bpf/CABOYnLwwJY=yFAGie59LFsUsBAgHfroVqbzZ5edAXbFE3YiNVA@mail.gmail.com +Link: https://lore.kernel.org/bpf/20231215100708.2265609-2-houtao@huaweicloud.com +Signed-off-by: Sasha Levin +--- + kernel/trace/bpf_trace.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c +index 84e8a0f6e4e0..640b08818afa 100644 +--- a/kernel/trace/bpf_trace.c ++++ b/kernel/trace/bpf_trace.c +@@ -41,6 +41,8 @@ + #define bpf_event_rcu_dereference(p) \ + rcu_dereference_protected(p, lockdep_is_held(&bpf_event_mutex)) + ++#define MAX_UPROBE_MULTI_CNT (1U << 20) ++ + #ifdef CONFIG_MODULES + struct bpf_trace_module { + struct module *module; +@@ -3202,6 +3204,8 @@ int bpf_uprobe_multi_link_attach(const union bpf_attr *attr, struct bpf_prog *pr + + if (!upath || !uoffsets || !cnt) + return -EINVAL; ++ if (cnt > MAX_UPROBE_MULTI_CNT) ++ return -E2BIG; + + uref_ctr_offsets = u64_to_user_ptr(attr->link_create.uprobe_multi.ref_ctr_offsets); + ucookies = u64_to_user_ptr(attr->link_create.uprobe_multi.cookies); +-- +2.43.0 + diff --git a/queue-6.7/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch b/queue-6.7/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch new file mode 100644 index 00000000000..64fd5fe1df6 --- /dev/null +++ b/queue-6.7/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch @@ -0,0 +1,43 @@ +From e16c52ec6d8cdf8be0d5a066fe8313f4ca71ceca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 5 Nov 2023 09:58:01 +0100 +Subject: bpf, lpm: Fix check prefixlen before walking trie + +From: Florian Lehner + +[ Upstream commit 9b75dbeb36fcd9fc7ed51d370310d0518a387769 ] + +When looking up an element in LPM trie, the condition 'matchlen == +trie->max_prefixlen' will never return true, if key->prefixlen is larger +than trie->max_prefixlen. Consequently all elements in the LPM trie will +be visited and no element is returned in the end. + +To resolve this, check key->prefixlen first before walking the LPM trie. + +Fixes: b95a5c4db09b ("bpf: add a longest prefix match trie map implementation") +Signed-off-by: Florian Lehner +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231105085801.3742-1-dev@der-flo.net +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/lpm_trie.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/kernel/bpf/lpm_trie.c b/kernel/bpf/lpm_trie.c +index 17c7e7782a1f..b32be680da6c 100644 +--- a/kernel/bpf/lpm_trie.c ++++ b/kernel/bpf/lpm_trie.c +@@ -231,6 +231,9 @@ static void *trie_lookup_elem(struct bpf_map *map, void *_key) + struct lpm_trie_node *node, *found = NULL; + struct bpf_lpm_trie_key *key = _key; + ++ if (key->prefixlen > trie->max_prefixlen) ++ return NULL; ++ + /* Start walking the trie from the root node ... */ + + for (node = rcu_dereference_check(trie->root, rcu_read_lock_bh_held()); +-- +2.43.0 + diff --git a/queue-6.7/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch b/queue-6.7/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch new file mode 100644 index 00000000000..0b59a35e735 --- /dev/null +++ b/queue-6.7/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch @@ -0,0 +1,81 @@ +From a7ecb3c82627c38caf99f79a7c8ea36bd843bd19 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Dec 2023 15:23:23 -0800 +Subject: bpf: sockmap, fix proto update hook to avoid dup calls + +From: John Fastabend + +[ Upstream commit 16b2f264983dc264c1560cc0170e760dec1bf54f ] + +When sockets are added to a sockmap or sockhash we allocate and init a +psock. Then update the proto ops with sock_map_init_proto the flow is + + sock_hash_update_common + sock_map_link + psock = sock_map_psock_get_checked() <-returns existing psock + sock_map_init_proto(sk, psock) <- updates sk_proto + +If the socket is already in a map this results in the sock_map_init_proto +being called multiple times on the same socket. We do this because when +a socket is added to multiple maps this might result in a new set of BPF +programs being attached to the socket requiring an updated ops struct. + +This creates a rule where it must be safe to call psock_update_sk_prot +multiple times. When we added a fix for UAF through unix sockets in patch +4dd9a38a753fc we broke this rule by adding a sock_hold in that path +to ensure the sock is not released. The result is if a af_unix stream sock +is placed in multiple maps it results in a memory leak because we call +sock_hold multiple times with only a single sock_put on it. + +Fixes: 8866730aed51 ("bpf, sockmap: af_unix stream sockets need to hold ref for pair sock") +Reported-by: Xingwei Lee +Signed-off-by: John Fastabend +Signed-off-by: Martin KaFai Lau +Reviewed-by: Jakub Sitnicki +Link: https://lore.kernel.org/r/20231221232327.43678-2-john.fastabend@gmail.com +Signed-off-by: Sasha Levin +--- + net/unix/unix_bpf.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/net/unix/unix_bpf.c b/net/unix/unix_bpf.c +index 7ea7c3a0d0d0..bd84785bf8d6 100644 +--- a/net/unix/unix_bpf.c ++++ b/net/unix/unix_bpf.c +@@ -161,15 +161,30 @@ int unix_stream_bpf_update_proto(struct sock *sk, struct sk_psock *psock, bool r + { + struct sock *sk_pair; + ++ /* Restore does not decrement the sk_pair reference yet because we must ++ * keep the a reference to the socket until after an RCU grace period ++ * and any pending sends have completed. ++ */ + if (restore) { + sk->sk_write_space = psock->saved_write_space; + sock_replace_proto(sk, psock->sk_proto); + return 0; + } + +- sk_pair = unix_peer(sk); +- sock_hold(sk_pair); +- psock->sk_pair = sk_pair; ++ /* psock_update_sk_prot can be called multiple times if psock is ++ * added to multiple maps and/or slots in the same map. There is ++ * also an edge case where replacing a psock with itself can trigger ++ * an extra psock_update_sk_prot during the insert process. So it ++ * must be safe to do multiple calls. Here we need to ensure we don't ++ * increment the refcnt through sock_hold many times. There will only ++ * be a single matching destroy operation. ++ */ ++ if (!psock->sk_pair) { ++ sk_pair = unix_peer(sk); ++ sock_hold(sk_pair); ++ psock->sk_pair = sk_pair; ++ } ++ + unix_stream_bpf_check_needs_rebuild(psock->sk_proto); + sock_replace_proto(sk, &unix_stream_bpf_prot); + return 0; +-- +2.43.0 + diff --git a/queue-6.7/bpf-use-c-unit_size-to-select-target-cache-during-fr.patch b/queue-6.7/bpf-use-c-unit_size-to-select-target-cache-during-fr.patch new file mode 100644 index 00000000000..d7f375b82fc --- /dev/null +++ b/queue-6.7/bpf-use-c-unit_size-to-select-target-cache-during-fr.patch @@ -0,0 +1,271 @@ +From e186113263b589e9c4e78dd122963e58d2dc26db Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 16 Dec 2023 21:10:51 +0800 +Subject: bpf: Use c->unit_size to select target cache during free +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Hou Tao + +[ Upstream commit 7ac5c53e00735d183a0f5e2cfce5eeb6c16319f2 ] + +At present, bpf memory allocator uses check_obj_size() to ensure that +ksize() of allocated pointer is equal with the unit_size of used +bpf_mem_cache. Its purpose is to prevent bpf_mem_free() from selecting +a bpf_mem_cache which has different unit_size compared with the +bpf_mem_cache used for allocation. But as reported by lkp, the return +value of ksize() or kmalloc_size_roundup() may change due to slab merge +and it will lead to the warning report in check_obj_size(). + +The reported warning happened as follows: +(1) in bpf_mem_cache_adjust_size(), kmalloc_size_roundup(96) returns the +object_size of kmalloc-96 instead of kmalloc-cg-96. The object_size of +kmalloc-96 is 96, so size_index for 96 is not adjusted accordingly. +(2) the object_size of kmalloc-cg-96 is adjust from 96 to 128 due to +slab merge in __kmem_cache_alias(). For SLAB, SLAB_HWCACHE_ALIGN is +enabled by default for kmalloc slab, so align is 64 and size is 128 for +kmalloc-cg-96. SLUB has a similar merge logic, but its object_size will +not be changed, because its align is 8 under x86-64. +(3) when unit_alloc() does kmalloc_node(96, __GFP_ACCOUNT, node), +ksize() returns 128 instead of 96 for the returned pointer. +(4) the warning in check_obj_size() is triggered. + +Considering the slab merge can happen in anytime (e.g, a slab created in +a new module), the following case is also possible: during the +initialization of bpf_global_ma, there is no slab merge and ksize() for +a 96-bytes object returns 96. But after that a new slab created by a +kernel module is merged to kmalloc-cg-96 and the object_size of +kmalloc-cg-96 is adjust from 96 to 128 (which is possible for x86-64 + +CONFIG_SLAB, because its alignment requirement is 64 for 96-bytes slab). +So soon or later, when bpf_global_ma frees a 96-byte-sized pointer +which is allocated from bpf_mem_cache with unit_size=96, bpf_mem_free() +will free the pointer through a bpf_mem_cache in which unit_size is 128, +because the return value of ksize() changes. The warning for the +mismatch will be triggered again. + +A feasible fix is introducing similar APIs compared with ksize() and +kmalloc_size_roundup() to return the actually-allocated size instead of +size which may change due to slab merge, but it will introduce +unnecessary dependency on the implementation details of mm subsystem. + +As for now the pointer of bpf_mem_cache is saved in the 8-bytes area +(or 4-bytes under 32-bit host) above the returned pointer, using +unit_size in the saved bpf_mem_cache to select the target cache instead +of inferring the size from the pointer itself. Beside no extra +dependency on mm subsystem, the performance for bpf_mem_free_rcu() is +also improved as shown below. + +Before applying the patch, the performances of bpf_mem_alloc() and +bpf_mem_free_rcu() on 8-CPUs VM with one producer are as follows: + +kmalloc : alloc 11.69 ± 0.28M/s free 29.58 ± 0.93M/s +percpu : alloc 14.11 ± 0.52M/s free 14.29 ± 0.99M/s + +After apply the patch, the performance for bpf_mem_free_rcu() increases +9% and 146% for kmalloc memory and per-cpu memory respectively: + +kmalloc: alloc 11.01 ± 0.03M/s free 32.42 ± 0.48M/s +percpu: alloc 12.84 ± 0.12M/s free 35.24 ± 0.23M/s + +After the fixes, there is no need to adjust size_index to fix the +mismatch between allocation and free, so remove it as well. Also return +NULL instead of ZERO_SIZE_PTR for zero-sized alloc in bpf_mem_alloc(), +because there is no bpf_mem_cache pointer saved above ZERO_SIZE_PTR. + +Fixes: 9077fc228f09 ("bpf: Use kmalloc_size_roundup() to adjust size_index") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/bpf/202310302113.9f8fe705-oliver.sang@intel.com +Signed-off-by: Hou Tao +Link: https://lore.kernel.org/r/20231216131052.27621-2-houtao@huaweicloud.com +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/memalloc.c | 105 +++++------------------------------------- + 1 file changed, 11 insertions(+), 94 deletions(-) + +diff --git a/kernel/bpf/memalloc.c b/kernel/bpf/memalloc.c +index 6a51cfe4c2d6..aa0fbf000a12 100644 +--- a/kernel/bpf/memalloc.c ++++ b/kernel/bpf/memalloc.c +@@ -490,27 +490,6 @@ static void prefill_mem_cache(struct bpf_mem_cache *c, int cpu) + alloc_bulk(c, c->unit_size <= 256 ? 4 : 1, cpu_to_node(cpu), false); + } + +-static int check_obj_size(struct bpf_mem_cache *c, unsigned int idx) +-{ +- struct llist_node *first; +- unsigned int obj_size; +- +- first = c->free_llist.first; +- if (!first) +- return 0; +- +- if (c->percpu_size) +- obj_size = pcpu_alloc_size(((void **)first)[1]); +- else +- obj_size = ksize(first); +- if (obj_size != c->unit_size) { +- WARN_ONCE(1, "bpf_mem_cache[%u]: percpu %d, unexpected object size %u, expect %u\n", +- idx, c->percpu_size, obj_size, c->unit_size); +- return -EINVAL; +- } +- return 0; +-} +- + /* When size != 0 bpf_mem_cache for each cpu. + * This is typical bpf hash map use case when all elements have equal size. + * +@@ -521,10 +500,10 @@ static int check_obj_size(struct bpf_mem_cache *c, unsigned int idx) + int bpf_mem_alloc_init(struct bpf_mem_alloc *ma, int size, bool percpu) + { + static u16 sizes[NUM_CACHES] = {96, 192, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096}; +- int cpu, i, err, unit_size, percpu_size = 0; + struct bpf_mem_caches *cc, __percpu *pcc; + struct bpf_mem_cache *c, __percpu *pc; + struct obj_cgroup *objcg = NULL; ++ int cpu, i, unit_size, percpu_size = 0; + + /* room for llist_node and per-cpu pointer */ + if (percpu) +@@ -560,7 +539,6 @@ int bpf_mem_alloc_init(struct bpf_mem_alloc *ma, int size, bool percpu) + pcc = __alloc_percpu_gfp(sizeof(*cc), 8, GFP_KERNEL); + if (!pcc) + return -ENOMEM; +- err = 0; + #ifdef CONFIG_MEMCG_KMEM + objcg = get_obj_cgroup_from_current(); + #endif +@@ -574,28 +552,12 @@ int bpf_mem_alloc_init(struct bpf_mem_alloc *ma, int size, bool percpu) + c->tgt = c; + + init_refill_work(c); +- /* Another bpf_mem_cache will be used when allocating +- * c->unit_size in bpf_mem_alloc(), so doesn't prefill +- * for the bpf_mem_cache because these free objects will +- * never be used. +- */ +- if (i != bpf_mem_cache_idx(c->unit_size)) +- continue; + prefill_mem_cache(c, cpu); +- err = check_obj_size(c, i); +- if (err) +- goto out; + } + } + +-out: + ma->caches = pcc; +- /* refill_work is either zeroed or initialized, so it is safe to +- * call irq_work_sync(). +- */ +- if (err) +- bpf_mem_alloc_destroy(ma); +- return err; ++ return 0; + } + + static void drain_mem_cache(struct bpf_mem_cache *c) +@@ -869,7 +831,7 @@ void notrace *bpf_mem_alloc(struct bpf_mem_alloc *ma, size_t size) + void *ret; + + if (!size) +- return ZERO_SIZE_PTR; ++ return NULL; + + idx = bpf_mem_cache_idx(size + LLIST_NODE_SZ); + if (idx < 0) +@@ -879,26 +841,17 @@ void notrace *bpf_mem_alloc(struct bpf_mem_alloc *ma, size_t size) + return !ret ? NULL : ret + LLIST_NODE_SZ; + } + +-static notrace int bpf_mem_free_idx(void *ptr, bool percpu) +-{ +- size_t size; +- +- if (percpu) +- size = pcpu_alloc_size(*((void **)ptr)); +- else +- size = ksize(ptr - LLIST_NODE_SZ); +- return bpf_mem_cache_idx(size); +-} +- + void notrace bpf_mem_free(struct bpf_mem_alloc *ma, void *ptr) + { ++ struct bpf_mem_cache *c; + int idx; + + if (!ptr) + return; + +- idx = bpf_mem_free_idx(ptr, ma->percpu); +- if (idx < 0) ++ c = *(void **)(ptr - LLIST_NODE_SZ); ++ idx = bpf_mem_cache_idx(c->unit_size); ++ if (WARN_ON_ONCE(idx < 0)) + return; + + unit_free(this_cpu_ptr(ma->caches)->cache + idx, ptr); +@@ -906,13 +859,15 @@ void notrace bpf_mem_free(struct bpf_mem_alloc *ma, void *ptr) + + void notrace bpf_mem_free_rcu(struct bpf_mem_alloc *ma, void *ptr) + { ++ struct bpf_mem_cache *c; + int idx; + + if (!ptr) + return; + +- idx = bpf_mem_free_idx(ptr, ma->percpu); +- if (idx < 0) ++ c = *(void **)(ptr - LLIST_NODE_SZ); ++ idx = bpf_mem_cache_idx(c->unit_size); ++ if (WARN_ON_ONCE(idx < 0)) + return; + + unit_free_rcu(this_cpu_ptr(ma->caches)->cache + idx, ptr); +@@ -986,41 +941,3 @@ void notrace *bpf_mem_cache_alloc_flags(struct bpf_mem_alloc *ma, gfp_t flags) + + return !ret ? NULL : ret + LLIST_NODE_SZ; + } +- +-/* The alignment of dynamic per-cpu area is 8, so c->unit_size and the +- * actual size of dynamic per-cpu area will always be matched and there is +- * no need to adjust size_index for per-cpu allocation. However for the +- * simplicity of the implementation, use an unified size_index for both +- * kmalloc and per-cpu allocation. +- */ +-static __init int bpf_mem_cache_adjust_size(void) +-{ +- unsigned int size; +- +- /* Adjusting the indexes in size_index() according to the object_size +- * of underlying slab cache, so bpf_mem_alloc() will select a +- * bpf_mem_cache with unit_size equal to the object_size of +- * the underlying slab cache. +- * +- * The maximal value of KMALLOC_MIN_SIZE and __kmalloc_minalign() is +- * 256-bytes, so only do adjustment for [8-bytes, 192-bytes]. +- */ +- for (size = 192; size >= 8; size -= 8) { +- unsigned int kmalloc_size, index; +- +- kmalloc_size = kmalloc_size_roundup(size); +- if (kmalloc_size == size) +- continue; +- +- if (kmalloc_size <= 192) +- index = size_index[(kmalloc_size - 1) / 8]; +- else +- index = fls(kmalloc_size - 1) - 1; +- /* Only overwrite if necessary */ +- if (size_index[(size - 1) / 8] != index) +- size_index[(size - 1) / 8] = index; +- } +- +- return 0; +-} +-subsys_initcall(bpf_mem_cache_adjust_size); +-- +2.43.0 + diff --git a/queue-6.7/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch b/queue-6.7/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch new file mode 100644 index 00000000000..fe7be651ab8 --- /dev/null +++ b/queue-6.7/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch @@ -0,0 +1,138 @@ +From 27e11fe8a97a23bbbebaaddf6b8fd0bfeec6e4b1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Nov 2023 09:25:54 +0000 +Subject: calipso: fix memory leak in netlbl_calipso_add_pass() + +From: Gavrilov Ilia + +[ Upstream commit ec4e9d630a64df500641892f4e259e8149594a99 ] + +If IPv6 support is disabled at boot (ipv6.disable=1), +the calipso_init() -> netlbl_calipso_ops_register() function isn't called, +and the netlbl_calipso_ops_get() function always returns NULL. +In this case, the netlbl_calipso_add_pass() function allocates memory +for the doi_def variable but doesn't free it with the calipso_doi_free(). + +BUG: memory leak +unreferenced object 0xffff888011d68180 (size 64): + comm "syz-executor.1", pid 10746, jiffies 4295410986 (age 17.928s) + hex dump (first 32 bytes): + 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 ................ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + backtrace: + [<...>] kmalloc include/linux/slab.h:552 [inline] + [<...>] netlbl_calipso_add_pass net/netlabel/netlabel_calipso.c:76 [inline] + [<...>] netlbl_calipso_add+0x22e/0x4f0 net/netlabel/netlabel_calipso.c:111 + [<...>] genl_family_rcv_msg_doit+0x22f/0x330 net/netlink/genetlink.c:739 + [<...>] genl_family_rcv_msg net/netlink/genetlink.c:783 [inline] + [<...>] genl_rcv_msg+0x341/0x5a0 net/netlink/genetlink.c:800 + [<...>] netlink_rcv_skb+0x14d/0x440 net/netlink/af_netlink.c:2515 + [<...>] genl_rcv+0x29/0x40 net/netlink/genetlink.c:811 + [<...>] netlink_unicast_kernel net/netlink/af_netlink.c:1313 [inline] + [<...>] netlink_unicast+0x54b/0x800 net/netlink/af_netlink.c:1339 + [<...>] netlink_sendmsg+0x90a/0xdf0 net/netlink/af_netlink.c:1934 + [<...>] sock_sendmsg_nosec net/socket.c:651 [inline] + [<...>] sock_sendmsg+0x157/0x190 net/socket.c:671 + [<...>] ____sys_sendmsg+0x712/0x870 net/socket.c:2342 + [<...>] ___sys_sendmsg+0xf8/0x170 net/socket.c:2396 + [<...>] __sys_sendmsg+0xea/0x1b0 net/socket.c:2429 + [<...>] do_syscall_64+0x30/0x40 arch/x86/entry/common.c:46 + [<...>] entry_SYSCALL_64_after_hwframe+0x61/0xc6 + +Found by InfoTeCS on behalf of Linux Verification Center +(linuxtesting.org) with Syzkaller + +Fixes: cb72d38211ea ("netlabel: Initial support for the CALIPSO netlink protocol.") +Signed-off-by: Gavrilov Ilia +[PM: merged via the LSM tree at Jakub Kicinski request] +Signed-off-by: Paul Moore +Signed-off-by: Sasha Levin +--- + net/netlabel/netlabel_calipso.c | 49 +++++++++++++++++---------------- + 1 file changed, 26 insertions(+), 23 deletions(-) + +diff --git a/net/netlabel/netlabel_calipso.c b/net/netlabel/netlabel_calipso.c +index f1d5b8465217..a07c2216d28b 100644 +--- a/net/netlabel/netlabel_calipso.c ++++ b/net/netlabel/netlabel_calipso.c +@@ -54,6 +54,28 @@ static const struct nla_policy calipso_genl_policy[NLBL_CALIPSO_A_MAX + 1] = { + [NLBL_CALIPSO_A_MTYPE] = { .type = NLA_U32 }, + }; + ++static const struct netlbl_calipso_ops *calipso_ops; ++ ++/** ++ * netlbl_calipso_ops_register - Register the CALIPSO operations ++ * @ops: ops to register ++ * ++ * Description: ++ * Register the CALIPSO packet engine operations. ++ * ++ */ ++const struct netlbl_calipso_ops * ++netlbl_calipso_ops_register(const struct netlbl_calipso_ops *ops) ++{ ++ return xchg(&calipso_ops, ops); ++} ++EXPORT_SYMBOL(netlbl_calipso_ops_register); ++ ++static const struct netlbl_calipso_ops *netlbl_calipso_ops_get(void) ++{ ++ return READ_ONCE(calipso_ops); ++} ++ + /* NetLabel Command Handlers + */ + /** +@@ -96,15 +118,18 @@ static int netlbl_calipso_add_pass(struct genl_info *info, + * + */ + static int netlbl_calipso_add(struct sk_buff *skb, struct genl_info *info) +- + { + int ret_val = -EINVAL; + struct netlbl_audit audit_info; ++ const struct netlbl_calipso_ops *ops = netlbl_calipso_ops_get(); + + if (!info->attrs[NLBL_CALIPSO_A_DOI] || + !info->attrs[NLBL_CALIPSO_A_MTYPE]) + return -EINVAL; + ++ if (!ops) ++ return -EOPNOTSUPP; ++ + netlbl_netlink_auditinfo(&audit_info); + switch (nla_get_u32(info->attrs[NLBL_CALIPSO_A_MTYPE])) { + case CALIPSO_MAP_PASS: +@@ -363,28 +388,6 @@ int __init netlbl_calipso_genl_init(void) + return genl_register_family(&netlbl_calipso_gnl_family); + } + +-static const struct netlbl_calipso_ops *calipso_ops; +- +-/** +- * netlbl_calipso_ops_register - Register the CALIPSO operations +- * @ops: ops to register +- * +- * Description: +- * Register the CALIPSO packet engine operations. +- * +- */ +-const struct netlbl_calipso_ops * +-netlbl_calipso_ops_register(const struct netlbl_calipso_ops *ops) +-{ +- return xchg(&calipso_ops, ops); +-} +-EXPORT_SYMBOL(netlbl_calipso_ops_register); +- +-static const struct netlbl_calipso_ops *netlbl_calipso_ops_get(void) +-{ +- return READ_ONCE(calipso_ops); +-} +- + /** + * calipso_doi_add - Add a new DOI to the CALIPSO protocol engine + * @doi_def: the DOI structure +-- +2.43.0 + diff --git a/queue-6.7/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch b/queue-6.7/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch new file mode 100644 index 00000000000..d1f3da4204b --- /dev/null +++ b/queue-6.7/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch @@ -0,0 +1,43 @@ +From 95edbb98a5104a98a357dba229c3d12ef899087b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 18:14:16 +0100 +Subject: clk: fixed-rate: fix + clk_hw_register_fixed_rate_with_accuracy_parent_hw +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Théo Lebrun + +[ Upstream commit ee0cf5e07f44a10fce8f1bfa9db226c0b5ecf880 ] + +Add missing comma and remove extraneous NULL argument. The macro is +currently used by no one which explains why the typo slipped by. + +Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") +Signed-off-by: Théo Lebrun +Link: https://lore.kernel.org/r/20231218-mbly-clk-v1-1-44ce54108f06@bootlin.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + include/linux/clk-provider.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index ace3a4ce2fc9..1293c38ddb7f 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -448,8 +448,8 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + */ + #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ + parent_hw, flags, fixed_rate, fixed_accuracy) \ +- __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ +- NULL, NULL, (flags), (fixed_rate), \ ++ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ ++ NULL, (flags), (fixed_rate), \ + (fixed_accuracy), 0, false) + /** + * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-dispcc-sm8550-update-disp-pll-settings.patch b/queue-6.7/clk-qcom-dispcc-sm8550-update-disp-pll-settings.patch new file mode 100644 index 00000000000..46921f97a30 --- /dev/null +++ b/queue-6.7/clk-qcom-dispcc-sm8550-update-disp-pll-settings.patch @@ -0,0 +1,50 @@ +From ba126b9d9b6c0e1b578a3b264417082788e7e6bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:09 +0100 +Subject: clk: qcom: dispcc-sm8550: Update disp PLL settings + +From: Konrad Dybcio + +[ Upstream commit febd251d8775c4fb6e4acd6b5d7b0ed707f4611f ] + +The settings in the driver seem to have been taken from an older +release. Update them to match the latest values. + +Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/dispcc-sm8550.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c +index aefa19f3c2c5..0b8f0904b339 100644 +--- a/drivers/clk/qcom/dispcc-sm8550.c ++++ b/drivers/clk/qcom/dispcc-sm8550.c +@@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = { + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, ++ .test_ctl_val = 0x00000000, ++ .test_ctl_hi_val = 0x00000003, ++ .test_ctl_hi1_val = 0x00009000, ++ .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, + }; +@@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = { + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, ++ .test_ctl_val = 0x00000000, ++ .test_ctl_hi_val = 0x00000003, ++ .test_ctl_hi1_val = 0x00009000, ++ .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, + }; +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-dispcc-sm8550-use-the-correct-pll-configura.patch b/queue-6.7/clk-qcom-dispcc-sm8550-use-the-correct-pll-configura.patch new file mode 100644 index 00000000000..5ab5ab5f870 --- /dev/null +++ b/queue-6.7/clk-qcom-dispcc-sm8550-use-the-correct-pll-configura.patch @@ -0,0 +1,39 @@ +From 61fdb3f2b316c70bc2523d3ecfca5f0142381ca8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:10 +0100 +Subject: clk: qcom: dispcc-sm8550: Use the correct PLL configuration function + +From: Konrad Dybcio + +[ Upstream commit c559bcb92564cbaedd43c749cf9b6fbb3d53ad5e ] + +To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are +filled properly, use the correct prepare function for OLE PLLs. + +Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/dispcc-sm8550.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c +index 0b8f0904b339..f96d8b81fd9a 100644 +--- a/drivers/clk/qcom/dispcc-sm8550.c ++++ b/drivers/clk/qcom/dispcc-sm8550.c +@@ -1774,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) + goto err_put_rpm; + } + +- clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); +- clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); ++ clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); ++ clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); + + /* Enable clock gating for MDP clocks */ + regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gcc-sm8550-add-the-missing-retain_ff_enable.patch b/queue-6.7/clk-qcom-gcc-sm8550-add-the-missing-retain_ff_enable.patch new file mode 100644 index 00000000000..0dbe8b740f2 --- /dev/null +++ b/queue-6.7/clk-qcom-gcc-sm8550-add-the-missing-retain_ff_enable.patch @@ -0,0 +1,100 @@ +From 534a7c5ad19873bc0a021274c8380b2350dfb303 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:04 +0100 +Subject: clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag + +From: Konrad Dybcio + +[ Upstream commit 1fe8273c8d4088dd68faaab8640ec95f381cbf1e ] + +All of the 8550's GCC GDSCs can and should use the retain registers so +as not to lose their state when entering lower power modes. + +Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8550.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c +index 586126c4dd90..1c3d78500392 100644 +--- a/drivers/clk/qcom/gcc-sm8550.c ++++ b/drivers/clk/qcom/gcc-sm8550.c +@@ -3002,7 +3002,7 @@ static struct gdsc pcie_0_gdsc = { + .name = "pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_0_phy_gdsc = { +@@ -3011,7 +3011,7 @@ static struct gdsc pcie_0_phy_gdsc = { + .name = "pcie_0_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_1_gdsc = { +@@ -3020,7 +3020,7 @@ static struct gdsc pcie_1_gdsc = { + .name = "pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_1_phy_gdsc = { +@@ -3029,7 +3029,7 @@ static struct gdsc pcie_1_phy_gdsc = { + .name = "pcie_1_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc ufs_phy_gdsc = { +@@ -3038,7 +3038,7 @@ static struct gdsc ufs_phy_gdsc = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc ufs_mem_phy_gdsc = { +@@ -3047,7 +3047,7 @@ static struct gdsc ufs_mem_phy_gdsc = { + .name = "ufs_mem_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc usb30_prim_gdsc = { +@@ -3056,7 +3056,7 @@ static struct gdsc usb30_prim_gdsc = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc usb3_phy_gdsc = { +@@ -3065,7 +3065,7 @@ static struct gdsc usb3_phy_gdsc = { + .name = "usb3_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR, ++ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct clk_regmap *gcc_sm8550_clocks[] = { +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gcc-sm8550-mark-rcgs-shared-where-applicabl.patch b/queue-6.7/clk-qcom-gcc-sm8550-mark-rcgs-shared-where-applicabl.patch new file mode 100644 index 00000000000..3dd9ebece5c --- /dev/null +++ b/queue-6.7/clk-qcom-gcc-sm8550-mark-rcgs-shared-where-applicabl.patch @@ -0,0 +1,414 @@ +From 073f569f7d1cbcfc34a11b5ecaf56133ee7106d2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:07 +0100 +Subject: clk: qcom: gcc-sm8550: Mark RCGs shared where applicable + +From: Konrad Dybcio + +[ Upstream commit 929c75d575667af389c8a9e03cebc93d43bb7f31 ] + +The vast majority of shared RCGs were not marked as such. Fix it. + +Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8550.c | 86 +++++++++++++++++------------------ + 1 file changed, 43 insertions(+), 43 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c +index 73bda0d03aa7..b883dffe5f7a 100644 +--- a/drivers/clk/qcom/gcc-sm8550.c ++++ b/drivers/clk/qcom/gcc-sm8550.c +@@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -416,7 +416,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -431,7 +431,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -451,7 +451,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -471,7 +471,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -486,7 +486,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -501,7 +501,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -521,7 +521,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { +@@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { +@@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { +@@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { +@@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { +@@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { +@@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { +@@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { +@@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { +@@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { +@@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { +@@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { +@@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { +@@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { +@@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { +@@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }; + + static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { +@@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1071,7 +1071,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1093,7 +1093,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1114,7 +1114,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +@@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_shared_ops, + }, + }; + +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gcc-sm8550-mark-the-pcie-gdscs-votable.patch b/queue-6.7/clk-qcom-gcc-sm8550-mark-the-pcie-gdscs-votable.patch new file mode 100644 index 00000000000..d8c60a504d5 --- /dev/null +++ b/queue-6.7/clk-qcom-gcc-sm8550-mark-the-pcie-gdscs-votable.patch @@ -0,0 +1,67 @@ +From 3eedede2827b239c30f3fdab6db66d4dff0d9bc4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:05 +0100 +Subject: clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable + +From: Konrad Dybcio + +[ Upstream commit e7fe73fc6b68ee97b1e8f124a66a5ee50d8d5e5b ] + +The PCIe GDSCs on most Qualcomm platforms expect the OS to always +consider collapse requests as successful. This also concerns SM8550. + +Add the VOTABLE flag to the GDSCs in question to comply with these +expectations. + +Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8550.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c +index 1c3d78500392..a16d07426b71 100644 +--- a/drivers/clk/qcom/gcc-sm8550.c ++++ b/drivers/clk/qcom/gcc-sm8550.c +@@ -3002,7 +3002,7 @@ static struct gdsc pcie_0_gdsc = { + .name = "pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, ++ .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_0_phy_gdsc = { +@@ -3011,7 +3011,7 @@ static struct gdsc pcie_0_phy_gdsc = { + .name = "pcie_0_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, ++ .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_1_gdsc = { +@@ -3020,7 +3020,7 @@ static struct gdsc pcie_1_gdsc = { + .name = "pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, ++ .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc pcie_1_phy_gdsc = { +@@ -3029,7 +3029,7 @@ static struct gdsc pcie_1_phy_gdsc = { + .name = "pcie_1_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, ++ .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + + static struct gdsc ufs_phy_gdsc = { +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gcc-sm8550-use-collapse-voting-for-pcie-gds.patch b/queue-6.7/clk-qcom-gcc-sm8550-use-collapse-voting-for-pcie-gds.patch new file mode 100644 index 00000000000..c304d2de1ca --- /dev/null +++ b/queue-6.7/clk-qcom-gcc-sm8550-use-collapse-voting-for-pcie-gds.patch @@ -0,0 +1,70 @@ +From 1de85c5c344e33e7e34f205e8960e59a841d27b7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:06 +0100 +Subject: clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs + +From: Konrad Dybcio + +[ Upstream commit 7e77a39265293ea4f05e20fff180755503c49918 ] + +The PCIe GDSCs can be shared with other masters and should use the APCS +collapse-vote register when updating the power state. + +This is specifically also needed to be able to disable power domains +that have been enabled by boot firmware using the vote register. + +Following other recent Qualcomm platforms, describe this register and +the corresponding mask for the PCIe (and _phy) GDSCs. + +Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sm8550.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c +index a16d07426b71..73bda0d03aa7 100644 +--- a/drivers/clk/qcom/gcc-sm8550.c ++++ b/drivers/clk/qcom/gcc-sm8550.c +@@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = { + + static struct gdsc pcie_0_gdsc = { + .gdscr = 0x6b004, ++ .collapse_ctrl = 0x52020, ++ .collapse_mask = BIT(0), + .pd = { + .name = "pcie_0_gdsc", + }, +@@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = { + + static struct gdsc pcie_0_phy_gdsc = { + .gdscr = 0x6c000, ++ .collapse_ctrl = 0x52020, ++ .collapse_mask = BIT(3), + .pd = { + .name = "pcie_0_phy_gdsc", + }, +@@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = { + + static struct gdsc pcie_1_gdsc = { + .gdscr = 0x8d004, ++ .collapse_ctrl = 0x52020, ++ .collapse_mask = BIT(1), + .pd = { + .name = "pcie_1_gdsc", + }, +@@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = { + + static struct gdsc pcie_1_phy_gdsc = { + .gdscr = 0x8e000, ++ .collapse_ctrl = 0x52020, ++ .collapse_mask = BIT(4), + .pd = { + .name = "pcie_1_phy_gdsc", + }, +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch b/queue-6.7/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch new file mode 100644 index 00000000000..19b64b3f2b2 --- /dev/null +++ b/queue-6.7/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch @@ -0,0 +1,40 @@ +From 30cbcfe152d73de80c8cb37d1669ec85ecca3b5f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 09:58:14 +0530 +Subject: clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 config + +From: Satya Priya Kakitapalli + +[ Upstream commit 6ebd9a4f8b8d2b35cf965a04849c4ba763722f13 ] + +Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 +as per latest HW recommendation. + +Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150") +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gpucc-sm8150.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c +index 8422fd047493..c89a5b59ddb7 100644 +--- a/drivers/clk/qcom/gpucc-sm8150.c ++++ b/drivers/clk/qcom/gpucc-sm8150.c +@@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = { + .config_ctl_hi_val = 0x00002267, + .config_ctl_hi1_val = 0x00000024, + .test_ctl_val = 0x00000000, +- .test_ctl_hi_val = 0x00000002, +- .test_ctl_hi1_val = 0x00000000, ++ .test_ctl_hi_val = 0x00000000, ++ .test_ctl_hi1_val = 0x00000020, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x000000d0, +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-gpucc-sm8550-update-gpu-pll-settings.patch b/queue-6.7/clk-qcom-gpucc-sm8550-update-gpu-pll-settings.patch new file mode 100644 index 00000000000..1adb8301352 --- /dev/null +++ b/queue-6.7/clk-qcom-gpucc-sm8550-update-gpu-pll-settings.patch @@ -0,0 +1,44 @@ +From 4d5431df0137750b3d3913930fe38a4bceac7e08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 17:02:08 +0100 +Subject: clk: qcom: gpucc-sm8550: Update GPU PLL settings + +From: Konrad Dybcio + +[ Upstream commit 1d595972da12b5a78748eeb3ba1ff58bb0283b91 ] + +The settings in the driver seem to have been taken from an older +release. Update them to match the latest values. + +Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gpucc-sm8550.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c +index 420dcb27b47d..2fa8673424d7 100644 +--- a/drivers/clk/qcom/gpucc-sm8550.c ++++ b/drivers/clk/qcom/gpucc-sm8550.c +@@ -35,12 +35,12 @@ enum { + }; + + static const struct pll_vco lucid_ole_vco[] = { +- { 249600000, 2300000000, 0 }, ++ { 249600000, 2000000000, 0 }, + }; + + static const struct alpha_pll_config gpu_cc_pll0_config = { +- .l = 0x0d, +- .alpha = 0x0, ++ .l = 0x1e, ++ .alpha = 0xbaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, +-- +2.43.0 + diff --git a/queue-6.7/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch b/queue-6.7/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch new file mode 100644 index 00000000000..32851721cd3 --- /dev/null +++ b/queue-6.7/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch @@ -0,0 +1,37 @@ +From 32ea3dda2e291b97ba2ce214bb49c9719fe80f5e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 15:20:26 +0530 +Subject: clk: qcom: videocc-sm8150: Add missing PLL config property + +From: Satya Priya Kakitapalli + +[ Upstream commit 71f130c9193f613d497f7245365ed05ffdb0a401 ] + +When the driver was ported upstream, PLL test_ctl_hi1 register value +was omitted. Add it to ensure the PLLs are fully configured. + +Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/videocc-sm8150.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c +index 1afdbe4a249d..5579463f7e46 100644 +--- a/drivers/clk/qcom/videocc-sm8150.c ++++ b/drivers/clk/qcom/videocc-sm8150.c +@@ -33,6 +33,7 @@ static struct alpha_pll_config video_pll0_config = { + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002267, + .config_ctl_hi1_val = 0x00000024, ++ .test_ctl_hi1_val = 0x00000020, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x000000D0, +-- +2.43.0 + diff --git a/queue-6.7/clk-renesas-rzg2l-check-reset-monitor-registers.patch b/queue-6.7/clk-renesas-rzg2l-check-reset-monitor-registers.patch new file mode 100644 index 00000000000..6026a659a55 --- /dev/null +++ b/queue-6.7/clk-renesas-rzg2l-check-reset-monitor-registers.patch @@ -0,0 +1,138 @@ +From 8bc94d9d151e0ddf2ea30f7447ae15d4c4021c26 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Dec 2023 09:06:50 +0200 +Subject: clk: renesas: rzg2l: Check reset monitor registers + +From: Claudiu Beznea + +[ Upstream commit da235d2fac212d0add570e755feb1167a830bc99 ] + +The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset +monitor registers need to be interrogated when the reset signals are +toggled (chapters "Procedures for Supplying and Stopping Reset Signals" +and "Procedure for Activating Modules"). Without this, there is a +chance that different modules (e.g. Ethernet) are not ready after their +reset signal is toggled, leading to failures (on probe or resume from +deep sleep states). + +The same indications are available for RZ/V2M for TYPE-B reset controls. + +Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") +Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") +Signed-off-by: Claudiu Beznea +Reviewed-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Sasha Levin +--- + drivers/clk/renesas/rzg2l-cpg.c | 59 ++++++++++++++++++++++++--------- + 1 file changed, 44 insertions(+), 15 deletions(-) + +diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c +index 3189c3167ba8..3d2daa4ba2a4 100644 +--- a/drivers/clk/renesas/rzg2l-cpg.c ++++ b/drivers/clk/renesas/rzg2l-cpg.c +@@ -1416,12 +1416,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->resets[id].off; +- u32 value = BIT(info->resets[id].bit) << 16; ++ u32 mask = BIT(info->resets[id].bit); ++ s8 monbit = info->resets[id].monbit; ++ u32 value = mask << 16; + + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); +- return 0; ++ ++ if (info->has_clk_mon_regs) { ++ reg = CLK_MRST_R(reg); ++ } else if (monbit >= 0) { ++ reg = CPG_RST_MON; ++ mask = BIT(monbit); ++ } else { ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ return 0; ++ } ++ ++ return readl_poll_timeout_atomic(priv->base + reg, value, ++ value & mask, 10, 200); + } + + static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, +@@ -1430,14 +1445,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->resets[id].off; +- u32 dis = BIT(info->resets[id].bit); +- u32 value = (dis << 16) | dis; ++ u32 mask = BIT(info->resets[id].bit); ++ s8 monbit = info->resets[id].monbit; ++ u32 value = (mask << 16) | mask; + + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, + CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); +- return 0; ++ ++ if (info->has_clk_mon_regs) { ++ reg = CLK_MRST_R(reg); ++ } else if (monbit >= 0) { ++ reg = CPG_RST_MON; ++ mask = BIT(monbit); ++ } else { ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ return 0; ++ } ++ ++ return readl_poll_timeout_atomic(priv->base + reg, value, ++ !(value & mask), 10, 200); + } + + static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, +@@ -1449,9 +1478,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, + if (ret) + return ret; + +- /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ +- udelay(35); +- + return rzg2l_cpg_deassert(rcdev, id); + } + +@@ -1460,18 +1486,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + { + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; +- unsigned int reg = info->resets[id].off; +- u32 bitmask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; ++ unsigned int reg; ++ u32 bitmask; + + if (info->has_clk_mon_regs) { +- return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); ++ reg = CLK_MRST_R(info->resets[id].off); ++ bitmask = BIT(info->resets[id].bit); + } else if (monbit >= 0) { +- u32 monbitmask = BIT(monbit); +- +- return !!(readl(priv->base + CPG_RST_MON) & monbitmask); ++ reg = CPG_RST_MON; ++ bitmask = BIT(monbit); ++ } else { ++ return -ENOTSUPP; + } +- return -ENOTSUPP; ++ ++ return !!(readl(priv->base + reg) & bitmask); + } + + static const struct reset_control_ops rzg2l_cpg_reset_ops = { +-- +2.43.0 + diff --git a/queue-6.7/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch b/queue-6.7/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch new file mode 100644 index 00000000000..a564bfd28f6 --- /dev/null +++ b/queue-6.7/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch @@ -0,0 +1,82 @@ +From 12f9d89d50d5ab6cf1eb288e0c0c30b4db08cb33 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 09:00:11 +0200 +Subject: clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() + +From: Claudiu Beznea + +[ Upstream commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20 ] + +Code in rzg2l_cpg_reset() is equivalent with the combined code of +rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have +different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert(). + +Signed-off-by: Claudiu Beznea +Reviewed-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Geert Uytterhoeven +Stable-dep-of: da235d2fac21 ("clk: renesas: rzg2l: Check reset monitor registers") +Signed-off-by: Sasha Levin +--- + drivers/clk/renesas/rzg2l-cpg.c | 38 +++++++++++++-------------------- + 1 file changed, 15 insertions(+), 23 deletions(-) + +diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c +index 764bd72cf059..3189c3167ba8 100644 +--- a/drivers/clk/renesas/rzg2l-cpg.c ++++ b/drivers/clk/renesas/rzg2l-cpg.c +@@ -1410,29 +1410,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, + + #define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev) + +-static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); +- const struct rzg2l_cpg_info *info = priv->info; +- unsigned int reg = info->resets[id].off; +- u32 dis = BIT(info->resets[id].bit); +- u32 we = dis << 16; +- +- dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); +- +- /* Reset module */ +- writel(we, priv->base + CLK_RST_R(reg)); +- +- /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ +- udelay(35); +- +- /* Release module from reset state */ +- writel(we | dis, priv->base + CLK_RST_R(reg)); +- +- return 0; +-} +- + static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + unsigned long id) + { +@@ -1463,6 +1440,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + return 0; + } + ++static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ int ret; ++ ++ ret = rzg2l_cpg_assert(rcdev, id); ++ if (ret) ++ return ret; ++ ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ ++ return rzg2l_cpg_deassert(rcdev, id); ++} ++ + static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + unsigned long id) + { +-- +2.43.0 + diff --git a/queue-6.7/clk-rs9-fix-dif-oen-bit-placement-on-9fgv0241.patch b/queue-6.7/clk-rs9-fix-dif-oen-bit-placement-on-9fgv0241.patch new file mode 100644 index 00000000000..63331aacb6e --- /dev/null +++ b/queue-6.7/clk-rs9-fix-dif-oen-bit-placement-on-9fgv0241.patch @@ -0,0 +1,40 @@ +From ea394ec47097a5f0b9cb738f521641f4a233f7ef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 5 Nov 2023 21:06:15 +0100 +Subject: clk: rs9: Fix DIF OEn bit placement on 9FGV0241 + +From: Marek Vasut + +[ Upstream commit 29d861b5d29b6c80a887e93ad982cbbf4af2a06b ] + +On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other +chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment +the index in BIT() macro instead of the result of BIT() macro to shift +the bit correctly on 9FGV0241. + +Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") +Signed-off-by: Marek Vasut +Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org +Reviewed-by: Alexander Stein +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-renesas-pcie.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c +index 380245f635d6..6606aba253c5 100644 +--- a/drivers/clk/clk-renesas-pcie.c ++++ b/drivers/clk/clk-renesas-pcie.c +@@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) + enum rs9_model model = rs9->chip_info->model; + + if (model == RENESAS_9FGV0241) +- return BIT(idx) + 1; ++ return BIT(idx + 1); + else if (model == RENESAS_9FGV0441) + return BIT(idx); + +-- +2.43.0 + diff --git a/queue-6.7/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch b/queue-6.7/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch new file mode 100644 index 00000000000..940a1882913 --- /dev/null +++ b/queue-6.7/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch @@ -0,0 +1,41 @@ +From a97ca8480f38709a0f0625a9c7bf36c4efb9431a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Nov 2023 11:16:36 +0800 +Subject: clk: si5341: fix an error code problem in si5341_output_clk_set_rate + +From: Su Hui + +[ Upstream commit 5607068ae5ab02c3ac9cabc6859d36e98004c341 ] + +regmap_bulk_write() return zero or negative error code, return the value +of regmap_bulk_write() rather than '0'. + +Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") +Acked-by: Mike Looijmans +Signed-off-by: Su Hui +Link: https://lore.kernel.org/r/20231101031633.996124-1-suhui@nfschina.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-si5341.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c +index 845b451511d2..6e8dd7387cfd 100644 +--- a/drivers/clk/clk-si5341.c ++++ b/drivers/clk/clk-si5341.c +@@ -895,10 +895,8 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, + r[0] = r_div ? (r_div & 0xff) : 1; + r[1] = (r_div >> 8) & 0xff; + r[2] = (r_div >> 16) & 0xff; +- err = regmap_bulk_write(output->data->regmap, ++ return regmap_bulk_write(output->data->regmap, + SI5341_OUT_R_REG(output), r, 3); +- +- return 0; + } + + static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) +-- +2.43.0 + diff --git a/queue-6.7/clk-sp7021-fix-return-value-check-in-sp7021_clk_prob.patch b/queue-6.7/clk-sp7021-fix-return-value-check-in-sp7021_clk_prob.patch new file mode 100644 index 00000000000..3cdd5fde9dc --- /dev/null +++ b/queue-6.7/clk-sp7021-fix-return-value-check-in-sp7021_clk_prob.patch @@ -0,0 +1,50 @@ +From 5674e4d2c146e8169bb85858bd5b9f8ae0076d83 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 21:30:16 +0800 +Subject: clk: sp7021: fix return value check in sp7021_clk_probe() + +From: Yang Yingliang + +[ Upstream commit 1004c346a2b7393fce37dd1f320555e0a0d71e3f ] + +devm_platform_ioremap_resource() never returns NULL pointer, +it will return ERR_PTR() when it fails, so replace the check +with IS_ERR(). + +Fixes: d54c1fd4a51e ("clk: Add Sunplus SP7021 clock driver") +Signed-off-by: Yang Yingliang +Link: https://lore.kernel.org/r/20231128133016.2494699-1-yangyingliang@huawei.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-sp7021.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c +index 01d3c4c7b0b2..7cb7d501d7a6 100644 +--- a/drivers/clk/clk-sp7021.c ++++ b/drivers/clk/clk-sp7021.c +@@ -604,14 +604,14 @@ static int sp7021_clk_probe(struct platform_device *pdev) + int i; + + clk_base = devm_platform_ioremap_resource(pdev, 0); +- if (!clk_base) +- return -ENXIO; ++ if (IS_ERR(clk_base)) ++ return PTR_ERR(clk_base); + pll_base = devm_platform_ioremap_resource(pdev, 1); +- if (!pll_base) +- return -ENXIO; ++ if (IS_ERR(pll_base)) ++ return PTR_ERR(pll_base); + sys_base = devm_platform_ioremap_resource(pdev, 2); +- if (!sys_base) +- return -ENXIO; ++ if (IS_ERR(sys_base)) ++ return PTR_ERR(sys_base); + + /* enable default clks */ + for (i = 0; i < ARRAY_SIZE(sp_clken); i++) +-- +2.43.0 + diff --git a/queue-6.7/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch b/queue-6.7/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch new file mode 100644 index 00000000000..f3a3c33ffdb --- /dev/null +++ b/queue-6.7/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch @@ -0,0 +1,43 @@ +From ef750d81a0e730368ec173134f478cabb45f7b6c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 18:12:20 +0300 +Subject: cpufreq: scmi: process the result of devm_of_clk_add_hw_provider() + +From: Alexandra Diupina + +[ Upstream commit c4a5118a3ae1eadc687d84eef9431f9e13eb015c ] + +devm_of_clk_add_hw_provider() may return an errno, so +add a return value check + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 8410e7f3b31e ("cpufreq: scmi: Fix OPP addition failure with a dummy clock provider") +Signed-off-by: Alexandra Diupina +Signed-off-by: Viresh Kumar +Signed-off-by: Sasha Levin +--- + drivers/cpufreq/scmi-cpufreq.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c +index c8a7ccc42c16..4ee23f4ebf4a 100644 +--- a/drivers/cpufreq/scmi-cpufreq.c ++++ b/drivers/cpufreq/scmi-cpufreq.c +@@ -334,8 +334,11 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) + + #ifdef CONFIG_COMMON_CLK + /* dummy clock provider as needed by OPP if clocks property is used */ +- if (of_property_present(dev->of_node, "#clock-cells")) +- devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL); ++ if (of_property_present(dev->of_node, "#clock-cells")) { ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL); ++ if (ret) ++ return dev_err_probe(dev, ret, "%s: registering clock provider failed\n", __func__); ++ } + #endif + + ret = cpufreq_register_driver(&scmi_cpufreq_driver); +-- +2.43.0 + diff --git a/queue-6.7/cpuidle-haltpoll-do-not-enable-interrupts-when-enter.patch b/queue-6.7/cpuidle-haltpoll-do-not-enable-interrupts-when-enter.patch new file mode 100644 index 00000000000..4d6dd1667fc --- /dev/null +++ b/queue-6.7/cpuidle-haltpoll-do-not-enable-interrupts-when-enter.patch @@ -0,0 +1,53 @@ +From 7766cb7b9316e3d678848f6a01ae9d01967bd1b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 29 Dec 2023 18:08:18 +0100 +Subject: cpuidle: haltpoll: Do not enable interrupts when entering idle + +From: Borislav Petkov (AMD) + +[ Upstream commit c8f5caec3df84a02b937d6d9cda1f7ffa8dc443f ] + +The cpuidle drivers' ->enter() methods are supposed to be IRQ invariant: + + 5e26aa933911 ("cpuidle/poll: Ensure IRQs stay disabled after cpuidle_state::enter() calls") + bb7b11258561 ("cpuidle: Move IRQ state validation") + +Do that in the haltpoll driver too. + +Fixes: 5e26aa933911 ("cpuidle/poll: Ensure IRQs stay disabled after cpuidle_state::enter() calls") +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218245 +Reported-by: +Tested-by: +Signed-off-by: Borislav Petkov (AMD) +[ rjw: Changelog edits ] +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/cpuidle/cpuidle-haltpoll.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/drivers/cpuidle/cpuidle-haltpoll.c b/drivers/cpuidle/cpuidle-haltpoll.c +index e66df22f9695..d8515d5c0853 100644 +--- a/drivers/cpuidle/cpuidle-haltpoll.c ++++ b/drivers/cpuidle/cpuidle-haltpoll.c +@@ -25,13 +25,12 @@ MODULE_PARM_DESC(force, "Load unconditionally"); + static struct cpuidle_device __percpu *haltpoll_cpuidle_devices; + static enum cpuhp_state haltpoll_hp_state; + +-static int default_enter_idle(struct cpuidle_device *dev, +- struct cpuidle_driver *drv, int index) ++static __cpuidle int default_enter_idle(struct cpuidle_device *dev, ++ struct cpuidle_driver *drv, int index) + { +- if (current_clr_polling_and_test()) { +- local_irq_enable(); ++ if (current_clr_polling_and_test()) + return index; +- } ++ + arch_cpu_idle(); + return index; + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch b/queue-6.7/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch new file mode 100644 index 00000000000..469f3d90106 --- /dev/null +++ b/queue-6.7/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch @@ -0,0 +1,85 @@ +From 289b05f39d5d6768d5a1105f59e1c521800a8de2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 16:25:49 +0800 +Subject: crypto: af_alg - Disallow multiple in-flight AIO requests + +From: Herbert Xu + +[ Upstream commit 67b164a871af1d736f131fd6fe78a610909f06f3 ] + +Having multiple in-flight AIO requests results in unpredictable +output because they all share the same IV. Fix this by only allowing +one request at a time. + +Fixes: 83094e5e9e49 ("crypto: af_alg - add async support to algif_aead") +Fixes: a596999b7ddf ("crypto: algif - change algif_skcipher to be asynchronous") +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/af_alg.c | 14 +++++++++++++- + include/crypto/if_alg.h | 3 +++ + 2 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/crypto/af_alg.c b/crypto/af_alg.c +index ea6fb8e89d06..68cc9290cabe 100644 +--- a/crypto/af_alg.c ++++ b/crypto/af_alg.c +@@ -1116,9 +1116,13 @@ EXPORT_SYMBOL_GPL(af_alg_sendmsg); + void af_alg_free_resources(struct af_alg_async_req *areq) + { + struct sock *sk = areq->sk; ++ struct af_alg_ctx *ctx; + + af_alg_free_areq_sgls(areq); + sock_kfree_s(sk, areq, areq->areqlen); ++ ++ ctx = alg_sk(sk)->private; ++ ctx->inflight = false; + } + EXPORT_SYMBOL_GPL(af_alg_free_resources); + +@@ -1188,11 +1192,19 @@ EXPORT_SYMBOL_GPL(af_alg_poll); + struct af_alg_async_req *af_alg_alloc_areq(struct sock *sk, + unsigned int areqlen) + { +- struct af_alg_async_req *areq = sock_kmalloc(sk, areqlen, GFP_KERNEL); ++ struct af_alg_ctx *ctx = alg_sk(sk)->private; ++ struct af_alg_async_req *areq; ++ ++ /* Only one AIO request can be in flight. */ ++ if (ctx->inflight) ++ return ERR_PTR(-EBUSY); + ++ areq = sock_kmalloc(sk, areqlen, GFP_KERNEL); + if (unlikely(!areq)) + return ERR_PTR(-ENOMEM); + ++ ctx->inflight = true; ++ + areq->areqlen = areqlen; + areq->sk = sk; + areq->first_rsgl.sgl.sgt.sgl = areq->first_rsgl.sgl.sgl; +diff --git a/include/crypto/if_alg.h b/include/crypto/if_alg.h +index ef8ce86b1f78..08b803a4fcde 100644 +--- a/include/crypto/if_alg.h ++++ b/include/crypto/if_alg.h +@@ -136,6 +136,7 @@ struct af_alg_async_req { + * recvmsg is invoked. + * @init: True if metadata has been sent. + * @len: Length of memory allocated for this data structure. ++ * @inflight: Non-zero when AIO requests are in flight. + */ + struct af_alg_ctx { + struct list_head tsgl_list; +@@ -154,6 +155,8 @@ struct af_alg_ctx { + bool init; + + unsigned int len; ++ ++ unsigned int inflight; + }; + + int af_alg_register_type(const struct af_alg_type *type); +-- +2.43.0 + diff --git a/queue-6.7/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch b/queue-6.7/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch new file mode 100644 index 00000000000..9df58f5e1a7 --- /dev/null +++ b/queue-6.7/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch @@ -0,0 +1,45 @@ +From 4a52d8e3d0c8668dea7e0902d2df870a58039a0f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 11:47:10 +0800 +Subject: crypto: ccp - fix memleak in ccp_init_dm_workarea + +From: Dinghao Liu + +[ Upstream commit a1c95dd5bc1d6a5d7a75a376c2107421b7d6240d ] + +When dma_map_single() fails, wa->address is supposed to be freed +by the callers of ccp_init_dm_workarea() through ccp_dm_free(). +However, many of the call spots don't expect to have to call +ccp_dm_free() on failure of ccp_init_dm_workarea(), which may +lead to a memleak. Let's free wa->address in ccp_init_dm_workarea() +when dma_map_single() fails. + +Fixes: 63b945091a07 ("crypto: ccp - CCP device driver and interface support") +Signed-off-by: Dinghao Liu +Acked-by: Tom Lendacky +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/ccp/ccp-ops.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/ccp/ccp-ops.c b/drivers/crypto/ccp/ccp-ops.c +index aa4e1a500691..cb8e99936abb 100644 +--- a/drivers/crypto/ccp/ccp-ops.c ++++ b/drivers/crypto/ccp/ccp-ops.c +@@ -179,8 +179,11 @@ static int ccp_init_dm_workarea(struct ccp_dm_workarea *wa, + + wa->dma.address = dma_map_single(wa->dev, wa->address, len, + dir); +- if (dma_mapping_error(wa->dev, wa->dma.address)) ++ if (dma_mapping_error(wa->dev, wa->dma.address)) { ++ kfree(wa->address); ++ wa->address = NULL; + return -ENOMEM; ++ } + + wa->dma.length = len; + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-hpre-save-capability-registers-in-p.patch b/queue-6.7/crypto-hisilicon-hpre-save-capability-registers-in-p.patch new file mode 100644 index 00000000000..d79ec249a80 --- /dev/null +++ b/queue-6.7/crypto-hisilicon-hpre-save-capability-registers-in-p.patch @@ -0,0 +1,211 @@ +From d175d92dff295760e972e406dcf6528776327979 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:20 +0800 +Subject: crypto: hisilicon/hpre - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit cf8b5156bbc8c9376f699e8d35e9464b739e33ff ] + +Pre-store the valid value of hpre alg support related capability +register in hpre_qm_init(), which will be called by hpre_probe(). +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset +failed and the memory space disabled. + +Fixes: f214d59a0603 ("crypto: hisilicon/hpre - support hpre capability") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/hpre/hpre_main.c | 82 ++++++++++++++++++----- + 1 file changed, 64 insertions(+), 18 deletions(-) + +diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c +index 84c92d85d23d..3255b2a070c7 100644 +--- a/drivers/crypto/hisilicon/hpre/hpre_main.c ++++ b/drivers/crypto/hisilicon/hpre/hpre_main.c +@@ -226,6 +226,20 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { + {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} + }; + ++enum hpre_pre_store_cap_idx { ++ HPRE_CLUSTER_NUM_CAP_IDX = 0x0, ++ HPRE_CORE_ENABLE_BITMAP_CAP_IDX, ++ HPRE_DRV_ALG_BITMAP_CAP_IDX, ++ HPRE_DEV_ALG_BITMAP_CAP_IDX, ++}; ++ ++static const u32 hpre_pre_store_caps[] = { ++ HPRE_CLUSTER_NUM_CAP, ++ HPRE_CORE_ENABLE_BITMAP_CAP, ++ HPRE_DRV_ALG_BITMAP_CAP, ++ HPRE_DEV_ALG_BITMAP_CAP, ++}; ++ + static const struct hpre_hw_error hpre_hw_errors[] = { + { + .int_msk = BIT(0), +@@ -348,7 +362,7 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) + { + u32 cap_val; + +- cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver); ++ cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; + if (alg & cap_val) + return true; + +@@ -424,16 +438,6 @@ static u32 vfs_num; + module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); + MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); + +-static inline int hpre_cluster_num(struct hisi_qm *qm) +-{ +- return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver); +-} +- +-static inline int hpre_cluster_core_mask(struct hisi_qm *qm) +-{ +- return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver); +-} +- + struct hisi_qp *hpre_create_qp(u8 type) + { + int node = cpu_to_node(smp_processor_id()); +@@ -500,13 +504,15 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm) + + static int hpre_set_cluster(struct hisi_qm *qm) + { +- u32 cluster_core_mask = hpre_cluster_core_mask(qm); +- u8 clusters_num = hpre_cluster_num(qm); + struct device *dev = &qm->pdev->dev; + unsigned long offset; ++ u32 cluster_core_mask; ++ u8 clusters_num; + u32 val = 0; + int ret, i; + ++ cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val; ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + offset = i * HPRE_CLSTR_ADDR_INTRVL; + +@@ -701,11 +707,12 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) + + static void hpre_cnt_regs_clear(struct hisi_qm *qm) + { +- u8 clusters_num = hpre_cluster_num(qm); + unsigned long offset; ++ u8 clusters_num; + int i; + + /* clear clusterX/cluster_ctrl */ ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; + writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); +@@ -992,13 +999,14 @@ static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) + + static int hpre_cluster_debugfs_init(struct hisi_qm *qm) + { +- u8 clusters_num = hpre_cluster_num(qm); + struct device *dev = &qm->pdev->dev; + char buf[HPRE_DBGFS_VAL_MAX_LEN]; + struct debugfs_regset32 *regset; + struct dentry *tmp_d; ++ u8 clusters_num; + int i, ret; + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); + if (ret >= HPRE_DBGFS_VAL_MAX_LEN) +@@ -1103,6 +1111,34 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) + debugfs_remove_recursive(qm->debug.debug_root); + } + ++static int hpre_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *hpre_cap; ++ struct device *dev = &qm->pdev->dev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(hpre_pre_store_caps); ++ hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL); ++ if (!hpre_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ hpre_cap[i].type = hpre_pre_store_caps[i]; ++ hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, ++ hpre_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) { ++ dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n", ++ hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX); ++ return -EINVAL; ++ } ++ ++ qm->cap_tables.dev_cap_table = hpre_cap; ++ ++ return 0; ++} ++ + static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1136,7 +1172,15 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); ++ /* Fetch and save the value of capability registers */ ++ ret = hpre_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val; + ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); + if (ret) { + pci_err(pdev, "Failed to set hpre algs!\n"); +@@ -1150,11 +1194,12 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm) + { + int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); + int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); +- u8 clusters_num = hpre_cluster_num(qm); + struct qm_debug *debug = &qm->debug; + void __iomem *io_base; ++ u8 clusters_num; + int i, j, idx; + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + + com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); + if (!debug->last_words) +@@ -1191,10 +1236,10 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm) + { + int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); + int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); +- u8 clusters_num = hpre_cluster_num(qm); + struct qm_debug *debug = &qm->debug; + struct pci_dev *pdev = qm->pdev; + void __iomem *io_base; ++ u8 clusters_num; + int i, j, idx; + u32 val; + +@@ -1209,6 +1254,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm) + hpre_com_dfx_regs[i].name, debug->last_words[i], val); + } + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + io_base = qm->io_base + hpre_cluster_offsets[i]; + for (j = 0; j < cluster_dfx_regs_num; j++) { +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch b/queue-6.7/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch new file mode 100644 index 00000000000..01f2882dd31 --- /dev/null +++ b/queue-6.7/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch @@ -0,0 +1,385 @@ +From eb9617b29c7a762fc39505e62611c994ba9bd20d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:18 +0800 +Subject: crypto: hisilicon/qm - add a function to set qm algs + +From: Wenkai Lin + +[ Upstream commit f76f0d7f20672611974d3cc705996751fc403734 ] + +Extract a public function to set qm algs and remove +the similar code for setting qm algs in each module. + +Signed-off-by: Wenkai Lin +Signed-off-by: Hao Fang +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Stable-dep-of: cf8b5156bbc8 ("crypto: hisilicon/hpre - save capability registers in probe process") +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/hpre/hpre_main.c | 42 ++----------------- + drivers/crypto/hisilicon/qm.c | 36 +++++++++++++++++ + drivers/crypto/hisilicon/sec2/sec_main.c | 47 ++++------------------ + drivers/crypto/hisilicon/zip/zip_main.c | 49 ++++------------------- + include/linux/hisi_acc_qm.h | 8 +++- + 5 files changed, 62 insertions(+), 120 deletions(-) + +diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c +index 56777099ef69..84c92d85d23d 100644 +--- a/drivers/crypto/hisilicon/hpre/hpre_main.c ++++ b/drivers/crypto/hisilicon/hpre/hpre_main.c +@@ -118,8 +118,6 @@ + #define HPRE_DFX_COMMON2_LEN 0xE + #define HPRE_DFX_CORE_LEN 0x43 + +-#define HPRE_DEV_ALG_MAX_LEN 256 +- + static const char hpre_name[] = "hisi_hpre"; + static struct dentry *hpre_debugfs_root; + static const struct pci_device_id hpre_dev_ids[] = { +@@ -135,12 +133,7 @@ struct hpre_hw_error { + const char *msg; + }; + +-struct hpre_dev_alg { +- u32 alg_msk; +- const char *alg; +-}; +- +-static const struct hpre_dev_alg hpre_dev_algs[] = { ++static const struct qm_dev_alg hpre_dev_algs[] = { + { + .alg_msk = BIT(0), + .alg = "rsa\n" +@@ -362,35 +355,6 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) + return false; + } + +-static int hpre_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u32 alg_msk; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); +- +- for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) +- if (alg_msk & hpre_dev_algs[i].alg_msk) +- strcat(algs, hpre_dev_algs[i].alg); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static int hpre_diff_regs_show(struct seq_file *s, void *unused) + { + struct hisi_qm *qm = s->private; +@@ -1141,6 +1105,7 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) + + static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + if (pdev->revision == QM_HW_V1) { +@@ -1171,7 +1136,8 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = hpre_set_qm_algs(qm); ++ alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); ++ ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); + if (ret) { + pci_err(pdev, "Failed to set hpre algs!\n"); + hisi_qm_uninit(qm); +diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c +index 30b43006d1db..40da95dbab25 100644 +--- a/drivers/crypto/hisilicon/qm.c ++++ b/drivers/crypto/hisilicon/qm.c +@@ -229,6 +229,8 @@ + #define QM_QOS_MAX_CIR_U 6 + #define QM_AUTOSUSPEND_DELAY 3000 + ++#define QM_DEV_ALG_MAX_LEN 256 ++ + #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ + (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \ + ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \ +@@ -842,6 +844,40 @@ static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits, + *high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK; + } + ++int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, ++ u32 dev_algs_size) ++{ ++ struct device *dev = &qm->pdev->dev; ++ char *algs, *ptr; ++ int i; ++ ++ if (!qm->uacce) ++ return 0; ++ ++ if (dev_algs_size >= QM_DEV_ALG_MAX_LEN) { ++ dev_err(dev, "algs size %u is equal or larger than %d.\n", ++ dev_algs_size, QM_DEV_ALG_MAX_LEN); ++ return -EINVAL; ++ } ++ ++ algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); ++ if (!algs) ++ return -ENOMEM; ++ ++ for (i = 0; i < dev_algs_size; i++) ++ if (alg_msk & dev_algs[i].alg_msk) ++ strcat(algs, dev_algs[i].alg); ++ ++ ptr = strrchr(algs, '\n'); ++ if (ptr) { ++ *ptr = '\0'; ++ qm->uacce->algs = algs; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(hisi_qm_set_algs); ++ + static u32 qm_get_irq_num(struct hisi_qm *qm) + { + if (qm->fun_type == QM_HW_PF) +diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c +index 0e56a47eb862..2eceab7600ca 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_main.c ++++ b/drivers/crypto/hisilicon/sec2/sec_main.c +@@ -120,7 +120,6 @@ + GENMASK_ULL(42, 25)) + #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ + GENMASK_ULL(45, 43)) +-#define SEC_DEV_ALG_MAX_LEN 256 + + struct sec_hw_error { + u32 int_msk; +@@ -132,11 +131,6 @@ struct sec_dfx_item { + u32 offset; + }; + +-struct sec_dev_alg { +- u64 alg_msk; +- const char *algs; +-}; +- + static const char sec_name[] = "hisi_sec2"; + static struct dentry *sec_debugfs_root; + +@@ -173,15 +167,15 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { + {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, + }; + +-static const struct sec_dev_alg sec_dev_algs[] = { { ++static const struct qm_dev_alg sec_dev_algs[] = { { + .alg_msk = SEC_CIPHER_BITMAP, +- .algs = "cipher\n", ++ .alg = "cipher\n", + }, { + .alg_msk = SEC_DIGEST_BITMAP, +- .algs = "digest\n", ++ .alg = "digest\n", + }, { + .alg_msk = SEC_AEAD_BITMAP, +- .algs = "aead\n", ++ .alg = "aead\n", + }, + }; + +@@ -1077,37 +1071,9 @@ static int sec_pf_probe_init(struct sec_dev *sec) + return ret; + } + +-static int sec_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u64 alg_mask; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); +- +- for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) +- if (alg_mask & sec_dev_algs[i].alg_msk) +- strcat(algs, sec_dev_algs[i].algs); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + qm->pdev = pdev; +@@ -1142,7 +1108,8 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = sec_set_qm_algs(qm); ++ alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); ++ ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set sec algs!\n"); + hisi_qm_uninit(qm); +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index 85576f818278..f7cf54f02dd7 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -74,7 +74,6 @@ + #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) + #define HZIP_WR_PORT BIT(11) + +-#define HZIP_DEV_ALG_MAX_LEN 256 + #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) + #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) + #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) +@@ -128,23 +127,18 @@ struct zip_dfx_item { + u32 offset; + }; + +-struct zip_dev_alg { +- u32 alg_msk; +- const char *algs; +-}; +- +-static const struct zip_dev_alg zip_dev_algs[] = { { ++static const struct qm_dev_alg zip_dev_algs[] = { { + .alg_msk = HZIP_ALG_ZLIB_BIT, +- .algs = "zlib\n", ++ .alg = "zlib\n", + }, { + .alg_msk = HZIP_ALG_GZIP_BIT, +- .algs = "gzip\n", ++ .alg = "gzip\n", + }, { + .alg_msk = HZIP_ALG_DEFLATE_BIT, +- .algs = "deflate\n", ++ .alg = "deflate\n", + }, { + .alg_msk = HZIP_ALG_LZ77_BIT, +- .algs = "lz77_zstd\n", ++ .alg = "lz77_zstd\n", + }, + }; + +@@ -478,35 +472,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm) + return ret; + } + +-static int hisi_zip_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u32 alg_mask; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); +- +- for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) +- if (alg_mask & zip_dev_algs[i].alg_msk) +- strcat(algs, zip_dev_algs[i].algs); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) + { + u32 val; +@@ -1193,6 +1158,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + + static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + qm->pdev = pdev; +@@ -1228,7 +1194,8 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = hisi_zip_set_qm_algs(qm); ++ alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); ++ ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set zip algs!\n"); + hisi_qm_uninit(qm); +diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h +index b8da977711a7..4c5611d99c42 100644 +--- a/include/linux/hisi_acc_qm.h ++++ b/include/linux/hisi_acc_qm.h +@@ -160,6 +160,11 @@ enum qm_cap_bits { + QM_SUPPORT_RPM, + }; + ++struct qm_dev_alg { ++ u64 alg_msk; ++ const char *alg; ++}; ++ + struct dfx_diff_registers { + u32 *regs; + u32 reg_offset; +@@ -375,7 +380,6 @@ struct hisi_qm { + struct work_struct rst_work; + struct work_struct cmd_process; + +- const char *algs; + bool use_sva; + + resource_size_t phys_base; +@@ -575,6 +579,8 @@ void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset); + u32 hisi_qm_get_hw_info(struct hisi_qm *qm, + const struct hisi_qm_cap_info *info_table, + u32 index, bool is_read); ++int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, ++ u32 dev_algs_size); + + /* Used by VFIO ACC live migration driver */ + struct pci_driver *hisi_sec_get_pf_driver(void); +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch b/queue-6.7/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch new file mode 100644 index 00000000000..275ae9ebfb9 --- /dev/null +++ b/queue-6.7/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch @@ -0,0 +1,257 @@ +From 1702fe54719ed53f949cfbf643d982d395ed5f3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:19 +0800 +Subject: crypto: hisilicon/qm - save capability registers in qm init process + +From: Zhiqi Song + +[ Upstream commit cabe13d0bd2efb8dd50ed2310f57b33e1a69a0d4 ] + +In previous capability register implementation, qm irq related values +were read from capability registers dynamically when needed. But in +abnormal scenario, e.g. the core is timeout and the device needs to +soft reset and reset failed after disabling the MSE, the device can +not be removed normally, causing the following call trace: + + | Call trace: + | pci_irq_vector+0xfc/0x140 + | hisi_qm_uninit+0x278/0x3b0 [hisi_qm] + | hpre_remove+0x16c/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + | device_release_driver_internal+0x1ec/0x3e0 + | device_release_driver+0x3c/0x60 + | pci_stop_bus_device+0xfc/0x22c + | pci_stop_and_remove_bus_device+0x38/0x70 + | pci_iov_remove_virtfn+0x108/0x1c0 + | sriov_disable+0x7c/0x1e4 + | pci_disable_sriov+0x4c/0x6c + | hisi_qm_sriov_disable+0x90/0x160 [hisi_qm] + | hpre_remove+0x1a8/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + | device_release_driver_internal+0x1ec/0x3e0 + | driver_detach+0x168/0x2d0 + | bus_remove_driver+0xc0/0x230 + | driver_unregister+0x58/0xdc + | pci_unregister_driver+0x40/0x220 + | hpre_exit+0x34/0x64 [hisi_hpre] + | __arm64_sys_delete_module+0x374/0x620 + [...] + + | Call trace: + | free_msi_irqs+0x25c/0x300 + | pci_disable_msi+0x19c/0x264 + | pci_free_irq_vectors+0x4c/0x70 + | hisi_qm_pci_uninit+0x44/0x90 [hisi_qm] + | hisi_qm_uninit+0x28c/0x3b0 [hisi_qm] + | hpre_remove+0x16c/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + [...] + +The reason for this call trace is that when the MSE is disabled, the value +of capability registers in the BAR space become invalid. This will make the +subsequent unregister process get the wrong irq vector through capability +registers and get the wrong irq number by pci_irq_vector(). + +So add a capability table structure to pre-store the valid value of the irq +information capability register in qm init process, avoid obtaining invalid +capability register value after the MSE is disabled. + +Fixes: 3536cc55cada ("crypto: hisilicon/qm - support get device irq information from hardware registers") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/qm.c | 62 +++++++++++++++++++++++++++++------ + include/linux/hisi_acc_qm.h | 12 +++++++ + 2 files changed, 64 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c +index 18599f3634c3..30b43006d1db 100644 +--- a/drivers/crypto/hisilicon/qm.c ++++ b/drivers/crypto/hisilicon/qm.c +@@ -294,6 +294,13 @@ enum qm_basic_type { + QM_VF_IRQ_NUM_CAP, + }; + ++enum qm_pre_store_cap_idx { ++ QM_EQ_IRQ_TYPE_CAP_IDX = 0x0, ++ QM_AEQ_IRQ_TYPE_CAP_IDX, ++ QM_ABN_IRQ_TYPE_CAP_IDX, ++ QM_PF2VF_IRQ_TYPE_CAP_IDX, ++}; ++ + static const struct hisi_qm_cap_info qm_cap_info_comm[] = { + {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0}, + {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1}, +@@ -323,6 +330,13 @@ static const struct hisi_qm_cap_info qm_basic_info[] = { + {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3}, + }; + ++static const u32 qm_pre_store_caps[] = { ++ QM_EQ_IRQ_TYPE_CAP, ++ QM_AEQ_IRQ_TYPE_CAP, ++ QM_ABN_IRQ_TYPE_CAP, ++ QM_PF2VF_IRQ_TYPE_CAP, ++}; ++ + struct qm_mailbox { + __le16 w0; + __le16 queue_num; +@@ -4816,7 +4830,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm *qm) + if (qm->fun_type == QM_HW_VF) + return; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) + return; + +@@ -4833,7 +4847,7 @@ static int qm_register_abnormal_irq(struct hisi_qm *qm) + if (qm->fun_type == QM_HW_VF) + return 0; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) + return 0; + +@@ -4850,7 +4864,7 @@ static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4864,7 +4878,7 @@ static int qm_register_mb_cmd_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -4881,7 +4895,7 @@ static void qm_unregister_aeq_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4895,7 +4909,7 @@ static int qm_register_aeq_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -4913,7 +4927,7 @@ static void qm_unregister_eq_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4927,7 +4941,7 @@ static int qm_register_eq_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -5015,7 +5029,29 @@ static int qm_get_qp_num(struct hisi_qm *qm) + return 0; + } + +-static void qm_get_hw_caps(struct hisi_qm *qm) ++static int qm_pre_store_irq_type_caps(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *qm_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(qm_pre_store_caps); ++ qm_cap = devm_kzalloc(&pdev->dev, sizeof(*qm_cap) * size, GFP_KERNEL); ++ if (!qm_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ qm_cap[i].type = qm_pre_store_caps[i]; ++ qm_cap[i].cap_val = hisi_qm_get_hw_info(qm, qm_basic_info, ++ qm_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.qm_cap_table = qm_cap; ++ ++ return 0; ++} ++ ++static int qm_get_hw_caps(struct hisi_qm *qm) + { + const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ? + qm_cap_info_pf : qm_cap_info_vf; +@@ -5046,6 +5082,9 @@ static void qm_get_hw_caps(struct hisi_qm *qm) + if (val) + set_bit(cap_info[i].type, &qm->caps); + } ++ ++ /* Fetch and save the value of irq type related capability registers */ ++ return qm_pre_store_irq_type_caps(qm); + } + + static int qm_get_pci_res(struct hisi_qm *qm) +@@ -5067,7 +5106,10 @@ static int qm_get_pci_res(struct hisi_qm *qm) + goto err_request_mem_regions; + } + +- qm_get_hw_caps(qm); ++ ret = qm_get_hw_caps(qm); ++ if (ret) ++ goto err_ioremap; ++ + if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) { + qm->db_interval = QM_QP_DB_INTERVAL; + qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4); +diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h +index ddc7ebb70523..b8da977711a7 100644 +--- a/include/linux/hisi_acc_qm.h ++++ b/include/linux/hisi_acc_qm.h +@@ -265,6 +265,16 @@ struct hisi_qm_cap_info { + u32 v3_val; + }; + ++struct hisi_qm_cap_record { ++ u32 type; ++ u32 cap_val; ++}; ++ ++struct hisi_qm_cap_tables { ++ struct hisi_qm_cap_record *qm_cap_table; ++ struct hisi_qm_cap_record *dev_cap_table; ++}; ++ + struct hisi_qm_list { + struct mutex lock; + struct list_head list; +@@ -376,6 +386,8 @@ struct hisi_qm { + u32 mb_qos; + u32 type_rate; + struct qm_err_isolate isolate_data; ++ ++ struct hisi_qm_cap_tables cap_tables; + }; + + struct hisi_qp_status { +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-sec2-save-capability-registers-in-p.patch b/queue-6.7/crypto-hisilicon-sec2-save-capability-registers-in-p.patch new file mode 100644 index 00000000000..c3f8ca4c8ea --- /dev/null +++ b/queue-6.7/crypto-hisilicon-sec2-save-capability-registers-in-p.patch @@ -0,0 +1,151 @@ +From a514a140866202f4119af7b520387d5496d4704d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:21 +0800 +Subject: crypto: hisilicon/sec2 - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit f1115b0096c3163592e04e74f5a7548c25bda957 ] + +Pre-store the valid value of the sec alg support related capability +register in sec_qm_init(), which will be called by probe process. +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset +failed and the memory space disabled. + +Fixes: 921715b6b782 ("crypto: hisilicon/sec - get algorithm bitmap from registers") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/sec2/sec.h | 7 ++++ + drivers/crypto/hisilicon/sec2/sec_crypto.c | 10 ++++- + drivers/crypto/hisilicon/sec2/sec_main.c | 43 ++++++++++++++++++++-- + 3 files changed, 55 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h +index 3e57fc04b377..410c83712e28 100644 +--- a/drivers/crypto/hisilicon/sec2/sec.h ++++ b/drivers/crypto/hisilicon/sec2/sec.h +@@ -220,6 +220,13 @@ enum sec_cap_type { + SEC_CORE4_ALG_BITMAP_HIGH, + }; + ++enum sec_cap_reg_record_idx { ++ SEC_DRV_ALG_BITMAP_LOW_IDX = 0x0, ++ SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DEV_ALG_BITMAP_LOW_IDX, ++ SEC_DEV_ALG_BITMAP_HIGH_IDX, ++}; ++ + void sec_destroy_qps(struct hisi_qp **qps, int qp_num); + struct hisi_qp **sec_create_qps(void); + int sec_register_to_crypto(struct hisi_qm *qm); +diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c +index 6fcabbc87860..ba7f305d43c1 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_crypto.c ++++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c +@@ -2547,9 +2547,12 @@ static int sec_register_aead(u64 alg_mask) + + int sec_register_to_crypto(struct hisi_qm *qm) + { +- u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW); ++ u64 alg_mask; + int ret = 0; + ++ alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DRV_ALG_BITMAP_LOW_IDX); ++ + mutex_lock(&sec_algs_lock); + if (sec_available_devs) { + sec_available_devs++; +@@ -2578,7 +2581,10 @@ int sec_register_to_crypto(struct hisi_qm *qm) + + void sec_unregister_from_crypto(struct hisi_qm *qm) + { +- u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW); ++ u64 alg_mask; ++ ++ alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DRV_ALG_BITMAP_LOW_IDX); + + mutex_lock(&sec_algs_lock); + if (--sec_available_devs) +diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c +index 2eceab7600ca..878d94ab5d6d 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_main.c ++++ b/drivers/crypto/hisilicon/sec2/sec_main.c +@@ -167,6 +167,13 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { + {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, + }; + ++static const u32 sec_pre_store_caps[] = { ++ SEC_DRV_ALG_BITMAP_LOW, ++ SEC_DRV_ALG_BITMAP_HIGH, ++ SEC_DEV_ALG_BITMAP_LOW, ++ SEC_DEV_ALG_BITMAP_HIGH, ++}; ++ + static const struct qm_dev_alg sec_dev_algs[] = { { + .alg_msk = SEC_CIPHER_BITMAP, + .alg = "cipher\n", +@@ -388,8 +395,8 @@ u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) + { + u32 cap_val_h, cap_val_l; + +- cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver); +- cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver); ++ cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; ++ cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; + + return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l; + } +@@ -1071,6 +1078,28 @@ static int sec_pf_probe_init(struct sec_dev *sec) + return ret; + } + ++static int sec_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *sec_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(sec_pre_store_caps); ++ sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL); ++ if (!sec_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ sec_cap[i].type = sec_pre_store_caps[i]; ++ sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info, ++ sec_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.dev_cap_table = sec_cap; ++ ++ return 0; ++} ++ + static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1108,7 +1137,15 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); ++ /* Fetch and save the value of capability registers */ ++ ret = sec_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX); + ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set sec algs!\n"); +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch b/queue-6.7/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch new file mode 100644 index 00000000000..70de2412d5a --- /dev/null +++ b/queue-6.7/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch @@ -0,0 +1,125 @@ +From 98eff14939a5e9bda6788534a64f0acb80a3ed6c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 13:49:24 +0800 +Subject: crypto: hisilicon/zip - add zip comp high perf mode configuration + +From: Chenghai Huang + +[ Upstream commit a9864bae1806499ebf3757a9e71dddde5b9c48c6 ] + +To meet specific application scenarios, the function of switching between +the high performance mode and the high compression mode is added. + +Use the perf_mode=0/1 configuration to set the compression high perf mode, +0(default, high compression mode), 1(high performance mode). These two +modes only apply to the compression direction and are compatible with +software algorithm in both directions. + +Signed-off-by: Chenghai Huang +Signed-off-by: Herbert Xu +Stable-dep-of: cf8b5156bbc8 ("crypto: hisilicon/hpre - save capability registers in probe process") +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/zip/zip_main.c | 65 +++++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index db4c964cd649..85576f818278 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -107,6 +107,14 @@ + #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ + HZIP_CORE_GATED_OOO_EN) + ++/* zip comp high performance */ ++#define HZIP_HIGH_PERF_OFFSET 0x301208 ++ ++enum { ++ HZIP_HIGH_COMP_RATE, ++ HZIP_HIGH_COMP_PERF, ++}; ++ + static const char hisi_zip_name[] = "hisi_zip"; + static struct dentry *hzip_debugfs_root; + +@@ -352,6 +360,37 @@ static int hzip_diff_regs_show(struct seq_file *s, void *unused) + return 0; + } + DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); ++ ++static int perf_mode_set(const char *val, const struct kernel_param *kp) ++{ ++ int ret; ++ u32 n; ++ ++ if (!val) ++ return -EINVAL; ++ ++ ret = kstrtou32(val, 10, &n); ++ if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && ++ n != HZIP_HIGH_COMP_RATE)) ++ return -EINVAL; ++ ++ return param_set_int(val, kp); ++} ++ ++static const struct kernel_param_ops zip_com_perf_ops = { ++ .set = perf_mode_set, ++ .get = param_get_int, ++}; ++ ++/* ++ * perf_mode = 0 means enable high compression rate mode, ++ * perf_mode = 1 means enable high compression performance mode. ++ * These two modes only apply to the compression direction. ++ */ ++static u32 perf_mode = HZIP_HIGH_COMP_RATE; ++module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); ++MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); ++ + static const struct kernel_param_ops zip_uacce_mode_ops = { + .set = uacce_mode_set, + .get = param_get_int, +@@ -417,6 +456,28 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) + return false; + } + ++static int hisi_zip_set_high_perf(struct hisi_qm *qm) ++{ ++ u32 val; ++ int ret; ++ ++ val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); ++ if (perf_mode == HZIP_HIGH_COMP_PERF) ++ val |= HZIP_HIGH_COMP_PERF; ++ else ++ val &= ~HZIP_HIGH_COMP_PERF; ++ ++ /* Set perf mode */ ++ writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); ++ ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, ++ val, val == perf_mode, HZIP_DELAY_1_US, ++ HZIP_POLL_TIMEOUT_US); ++ if (ret) ++ pci_err(qm->pdev, "failed to set perf mode\n"); ++ ++ return ret; ++} ++ + static int hisi_zip_set_qm_algs(struct hisi_qm *qm) + { + struct device *dev = &qm->pdev->dev; +@@ -1115,6 +1176,10 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + if (ret) + return ret; + ++ ret = hisi_zip_set_high_perf(qm); ++ if (ret) ++ return ret; ++ + hisi_zip_open_sva_prefetch(qm); + hisi_qm_dev_err_init(qm); + hisi_zip_debug_regs_clear(qm); +-- +2.43.0 + diff --git a/queue-6.7/crypto-hisilicon-zip-save-capability-registers-in-pr.patch b/queue-6.7/crypto-hisilicon-zip-save-capability-registers-in-pr.patch new file mode 100644 index 00000000000..cd3fa1aa29c --- /dev/null +++ b/queue-6.7/crypto-hisilicon-zip-save-capability-registers-in-pr.patch @@ -0,0 +1,159 @@ +From 3715b4f8f09a0b5fd75898070dec988448cced86 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:22 +0800 +Subject: crypto: hisilicon/zip - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit 2ff0ad847951d61c2d8b309e1ccefb26c57dcc7b ] + +Pre-store the valid value of the zip alg support related capability +register in hisi_zip_qm_init(), which will be called by hisi_zip_probe(). +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset failed +and the memory space disabled. + +Fixes: db700974b69d ("crypto: hisilicon/zip - support zip capability") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/zip/zip_main.c | 73 ++++++++++++++++++++----- + 1 file changed, 60 insertions(+), 13 deletions(-) + +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index f7cf54f02dd7..403b07468841 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -249,6 +249,26 @@ static struct hisi_qm_cap_info zip_basic_cap_info[] = { + {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} + }; + ++enum zip_pre_store_cap_idx { ++ ZIP_CORE_NUM_CAP_IDX = 0x0, ++ ZIP_CLUSTER_COMP_NUM_CAP_IDX, ++ ZIP_CLUSTER_DECOMP_NUM_CAP_IDX, ++ ZIP_DECOMP_ENABLE_BITMAP_IDX, ++ ZIP_COMP_ENABLE_BITMAP_IDX, ++ ZIP_DRV_ALG_BITMAP_IDX, ++ ZIP_DEV_ALG_BITMAP_IDX, ++}; ++ ++static const u32 zip_pre_store_caps[] = { ++ ZIP_CORE_NUM_CAP, ++ ZIP_CLUSTER_COMP_NUM_CAP, ++ ZIP_CLUSTER_DECOMP_NUM_CAP, ++ ZIP_DECOMP_ENABLE_BITMAP, ++ ZIP_COMP_ENABLE_BITMAP, ++ ZIP_DRV_ALG_BITMAP, ++ ZIP_DEV_ALG_BITMAP, ++}; ++ + enum { + HZIP_COMP_CORE0, + HZIP_COMP_CORE1, +@@ -443,7 +463,7 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) + { + u32 cap_val; + +- cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); ++ cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; + if ((alg & cap_val) == alg) + return true; + +@@ -568,10 +588,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) + } + + /* let's open all compression/decompression cores */ +- dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, +- ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); +- comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, +- ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); ++ dcomp_bm = qm->cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val; ++ comp_bm = qm->cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val; + writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); + + /* enable sqc,cqc writeback */ +@@ -798,9 +816,8 @@ static int hisi_zip_core_debug_init(struct hisi_qm *qm) + char buf[HZIP_BUF_SIZE]; + int i; + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); +- zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, +- qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; ++ zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; + + for (i = 0; i < zip_core_num; i++) { + if (i < zip_comp_core_num) +@@ -942,7 +959,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) + u32 zip_core_num; + int i, j, idx; + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; + + debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, + sizeof(unsigned int), GFP_KERNEL); +@@ -998,9 +1015,9 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) + hzip_com_dfx_regs[i].name, debug->last_words[i], val); + } + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); +- zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, +- qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; ++ zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; ++ + for (i = 0; i < zip_core_num; i++) { + if (i < zip_comp_core_num) + scnprintf(buf, sizeof(buf), "Comp_core-%d", i); +@@ -1156,6 +1173,28 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + return ret; + } + ++static int zip_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *zip_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(zip_pre_store_caps); ++ zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL); ++ if (!zip_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ zip_cap[i].type = zip_pre_store_caps[i]; ++ zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ++ zip_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.dev_cap_table = zip_cap; ++ ++ return 0; ++} ++ + static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1194,7 +1233,15 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); ++ /* Fetch and save the value of capability registers */ ++ ret = zip_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = qm->cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val; + ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set zip algs!\n"); +-- +2.43.0 + diff --git a/queue-6.7/crypto-jh7110-correct-deferred-probe-return.patch b/queue-6.7/crypto-jh7110-correct-deferred-probe-return.patch new file mode 100644 index 00000000000..b3491bb1fa4 --- /dev/null +++ b/queue-6.7/crypto-jh7110-correct-deferred-probe-return.patch @@ -0,0 +1,54 @@ +From cec92c477ee3b1ab16e6f8bc22993898914e4d13 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 15:32:59 +0900 +Subject: crypto: jh7110 - Correct deferred probe return + +From: Chanho Park + +[ Upstream commit d57343022b71b9f41e731282dbe0baf0cff6ada8 ] + +This fixes list_add corruption error when the driver is returned +with -EPROBE_DEFER. It is also required to roll back the previous +probe sequences in case of deferred_probe. So, this removes +'err_probe_defer" goto label and just use err_dma_init instead. + +Fixes: 42ef0e944b01 ("crypto: starfive - Add crypto engine support") +Signed-off-by: Chanho Park +Reviewed-by: Jia Jie Ho +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/starfive/jh7110-cryp.c | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c +index 08e974e0dd12..3a67ddc4d936 100644 +--- a/drivers/crypto/starfive/jh7110-cryp.c ++++ b/drivers/crypto/starfive/jh7110-cryp.c +@@ -180,12 +180,8 @@ static int starfive_cryp_probe(struct platform_device *pdev) + spin_unlock(&dev_list.lock); + + ret = starfive_dma_init(cryp); +- if (ret) { +- if (ret == -EPROBE_DEFER) +- goto err_probe_defer; +- else +- goto err_dma_init; +- } ++ if (ret) ++ goto err_dma_init; + + /* Initialize crypto engine */ + cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1); +@@ -233,7 +229,7 @@ static int starfive_cryp_probe(struct platform_device *pdev) + + tasklet_kill(&cryp->aes_done); + tasklet_kill(&cryp->hash_done); +-err_probe_defer: ++ + return ret; + } + +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-add-null-pointer-check.patch b/queue-6.7/crypto-qat-add-null-pointer-check.patch new file mode 100644 index 00000000000..d167fe09a48 --- /dev/null +++ b/queue-6.7/crypto-qat-add-null-pointer-check.patch @@ -0,0 +1,40 @@ +From 6a3c9b7c48349f5a7f32b3b46a38c1eca6305b33 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 19:17:25 +0000 +Subject: crypto: qat - add NULL pointer check + +From: Giovanni Cabiddu + +[ Upstream commit a643212c9f28d09225c3792c316bc4aaf6be4a68 ] + +There is a possibility that the function adf_devmgr_pci_to_accel_dev() +might return a NULL pointer. +Add a NULL pointer check in the function rp2srv_show(). + +Fixes: dbc8876dd873 ("crypto: qat - add rp2svc sysfs attribute") +Signed-off-by: Giovanni Cabiddu +Reviewed-by: Ahsan Atta +Reviewed-by: David Guckian +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_sysfs.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c +index 6f0b3629da13..d450dad32c9e 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c +@@ -215,6 +215,9 @@ static ssize_t rp2srv_show(struct device *dev, struct device_attribute *attr, + enum adf_cfg_service_type svc; + + accel_dev = adf_devmgr_pci_to_accel_dev(to_pci_dev(dev)); ++ if (!accel_dev) ++ return -EINVAL; ++ + hw_data = GET_HW_DATA(accel_dev); + + if (accel_dev->sysfs.ring_num == UNSET_RING_NUM) +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-add-sysfs_added-flag-for-ras.patch b/queue-6.7/crypto-qat-add-sysfs_added-flag-for-ras.patch new file mode 100644 index 00000000000..e0bfacbc4eb --- /dev/null +++ b/queue-6.7/crypto-qat-add-sysfs_added-flag-for-ras.patch @@ -0,0 +1,89 @@ +From 7bcbc82c31ecce1599d08c5d22bc09e701ae6ef1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Nov 2023 17:59:45 +0100 +Subject: crypto: qat - add sysfs_added flag for ras + +From: Damian Muszynski + +[ Upstream commit 65089000ba8c2ae713ccac6603319143f3e1c08b ] + +The qat_ras sysfs attribute group is registered within the +adf_dev_start() function, alongside other driver components. +If any of the functions preceding the group registration fails, +the adf_dev_start() function returns, and the caller, to undo the +operation, invokes adf_dev_stop() followed by adf_dev_shutdown(). +However, the current flow lacks information about whether the +registration of the qat_ras attribute group was successful or not. + +In cases where this condition is encountered, an error similar to +the following might be reported: + + 4xxx 0000:6b:00.0: Starting device qat_dev0 + 4xxx 0000:6b:00.0: qat_dev0 started 9 acceleration engines + 4xxx 0000:6b:00.0: Failed to send init message + 4xxx 0000:6b:00.0: Failed to start device qat_dev0 + sysfs group 'qat_ras' not found for kobject '0000:6b:00.0' + ... + sysfs_remove_groups+0x29/0x50 + adf_sysfs_stop_ras+0x4b/0x80 [intel_qat] + adf_dev_stop+0x43/0x1d0 [intel_qat] + adf_dev_down+0x4b/0x150 [intel_qat] + ... + 4xxx 0000:6b:00.0: qat_dev0 stopped 9 acceleration engines + 4xxx 0000:6b:00.0: Resetting device qat_dev0 + +To prevent attempting to remove attributes from a group that has not +been added yet, a flag named 'sysfs_added' is introduced. This flag +is set to true upon the successful registration of the attribute group. + +Fixes: 532d7f6bc458 ("crypto: qat - add error counters") +Signed-off-by: Damian Muszynski +Reviewed-by: Giovanni Cabiddu +Reviewed-by: Ahsan Atta +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_accel_devices.h | 1 + + .../crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c | 7 ++++++- + 2 files changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h +index 4ff5729a3496..9d5fdd529a2e 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h ++++ b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h +@@ -92,6 +92,7 @@ enum ras_errors { + + struct adf_error_counters { + atomic_t counter[ADF_RAS_ERRORS]; ++ bool sysfs_added; + bool enabled; + }; + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c +index cffe2d722995..e97c67c87b3c 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c +@@ -99,6 +99,8 @@ void adf_sysfs_start_ras(struct adf_accel_dev *accel_dev) + if (device_add_group(&GET_DEV(accel_dev), &qat_ras_group)) + dev_err(&GET_DEV(accel_dev), + "Failed to create qat_ras attribute group.\n"); ++ ++ accel_dev->ras_errors.sysfs_added = true; + } + + void adf_sysfs_stop_ras(struct adf_accel_dev *accel_dev) +@@ -106,7 +108,10 @@ void adf_sysfs_stop_ras(struct adf_accel_dev *accel_dev) + if (!accel_dev->ras_errors.enabled) + return; + +- device_remove_group(&GET_DEV(accel_dev), &qat_ras_group); ++ if (accel_dev->ras_errors.sysfs_added) { ++ device_remove_group(&GET_DEV(accel_dev), &qat_ras_group); ++ accel_dev->ras_errors.sysfs_added = false; ++ } + + ADF_RAS_ERR_CTR_CLEAR(accel_dev->ras_errors); + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-add-sysfs_added-flag-for-rate-limiting.patch b/queue-6.7/crypto-qat-add-sysfs_added-flag-for-rate-limiting.patch new file mode 100644 index 00000000000..13c2efc7c97 --- /dev/null +++ b/queue-6.7/crypto-qat-add-sysfs_added-flag-for-rate-limiting.patch @@ -0,0 +1,89 @@ +From 98ea4356492445865ce63b08cf692800ec45a333 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Nov 2023 18:02:23 +0100 +Subject: crypto: qat - add sysfs_added flag for rate limiting + +From: Damian Muszynski + +[ Upstream commit d71fdd0f3c278c7f132c3a522645ebf9157edd6d ] + +The qat_rl sysfs attribute group is registered within the adf_dev_start() +function, alongside other driver components. +If any of the functions preceding the group registration fails, +the adf_dev_start() function returns, and the caller, to undo the +operation, invokes adf_dev_stop() followed by adf_dev_shutdown(). +However, the current flow lacks information about whether the +registration of the qat_rl attribute group was successful or not. + +In cases where this condition is encountered, an error similar to +the following might be reported: + + 4xxx 0000:6b:00.0: Starting device qat_dev0 + 4xxx 0000:6b:00.0: qat_dev0 started 9 acceleration engines + 4xxx 0000:6b:00.0: Failed to send init message + 4xxx 0000:6b:00.0: Failed to start device qat_dev0 + sysfs group 'qat_rl' not found for kobject '0000:6b:00.0' + ... + sysfs_remove_groups+0x2d/0x50 + adf_sysfs_rl_rm+0x44/0x70 [intel_qat] + adf_rl_stop+0x2d/0xb0 [intel_qat] + adf_dev_stop+0x33/0x1d0 [intel_qat] + adf_dev_down+0xf1/0x150 [intel_qat] + ... + 4xxx 0000:6b:00.0: qat_dev0 stopped 9 acceleration engines + 4xxx 0000:6b:00.0: Resetting device qat_dev0 + +To prevent attempting to remove attributes from a group that has not +been added yet, a flag named 'sysfs_added' is introduced. This flag +is set to true upon the successful registration of the attribute group. + +Fixes: d9fb8408376e ("crypto: qat - add rate limiting feature to qat_4xxx") +Signed-off-by: Damian Muszynski +Reviewed-by: Giovanni Cabiddu +Reviewed-by: Ahsan Atta +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_rl.h | 1 + + drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c | 8 ++++++++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.h b/drivers/crypto/intel/qat/qat_common/adf_rl.h +index eb5a330f8543..269c6656fb90 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_rl.h ++++ b/drivers/crypto/intel/qat/qat_common/adf_rl.h +@@ -79,6 +79,7 @@ struct adf_rl_interface_data { + struct adf_rl_sla_input_data input; + enum adf_base_services cap_rem_srv; + struct rw_semaphore lock; ++ bool sysfs_added; + }; + + struct adf_rl_hw_data { +diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c +index abf9c52474ec..bedb514d4e30 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c +@@ -441,11 +441,19 @@ int adf_sysfs_rl_add(struct adf_accel_dev *accel_dev) + + data->cap_rem_srv = ADF_SVC_NONE; + data->input.srv = ADF_SVC_NONE; ++ data->sysfs_added = true; + + return ret; + } + + void adf_sysfs_rl_rm(struct adf_accel_dev *accel_dev) + { ++ struct adf_rl_interface_data *data; ++ ++ data = &GET_RL_STRUCT(accel_dev); ++ if (!data->sysfs_added) ++ return; ++ + device_remove_group(&GET_DEV(accel_dev), &qat_rl_group); ++ data->sysfs_added = false; + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-fix-error-path-in-add_update_sla.patch b/queue-6.7/crypto-qat-fix-error-path-in-add_update_sla.patch new file mode 100644 index 00000000000..76dce6be0bd --- /dev/null +++ b/queue-6.7/crypto-qat-fix-error-path-in-add_update_sla.patch @@ -0,0 +1,58 @@ +From 0fadbb8f9b7dd850c19cd3a20131b9c75a03afb1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 18:37:32 +0100 +Subject: crypto: qat - fix error path in add_update_sla() + +From: Damian Muszynski + +[ Upstream commit 6627f03c21cb7001ae4dbbfb7a8514516d02331c ] + +The input argument `sla_in` is a pointer to a structure that contains +the parameters of the SLA which is being added or updated. +If this pointer is NULL, the function should return an error as +the data required for the algorithm is not available. +By mistake, the logic jumps to the error path which dereferences +the pointer. + +This results in a warnings reported by the static analyzer Smatch when +executed without a database: + + drivers/crypto/intel/qat/qat_common/adf_rl.c:871 add_update_sla() + error: we previously assumed 'sla_in' could be null (see line 812) + +This issue was not found in internal testing as the pointer cannot be +NULL. The function add_update_sla() is only called (indirectly) by +the rate limiting sysfs interface implementation in adf_sysfs_rl.c +which ensures that the data structure is allocated and valid. This is +also proven by the fact that Smatch executed with a database does not +report such error. + +Fix it by returning with error if the pointer `sla_in` is NULL. + +Fixes: d9fb8408376e ("crypto: qat - add rate limiting feature to qat_4xxx") +Reported-by: Dan Carpenter +Signed-off-by: Damian Muszynski +Reviewed-by: Giovanni Cabiddu +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_rl.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.c b/drivers/crypto/intel/qat/qat_common/adf_rl.c +index 86e3e2152b1b..f2de3cd7d05d 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_rl.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_rl.c +@@ -812,8 +812,7 @@ static int add_update_sla(struct adf_accel_dev *accel_dev, + if (!sla_in) { + dev_warn(&GET_DEV(accel_dev), + "SLA input data pointer is missing\n"); +- ret = -EFAULT; +- goto ret_err; ++ return -EFAULT; + } + + /* Input validation */ +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-fix-mutex-ordering-in-adf_rl.patch b/queue-6.7/crypto-qat-fix-mutex-ordering-in-adf_rl.patch new file mode 100644 index 00000000000..98b9c67b2d8 --- /dev/null +++ b/queue-6.7/crypto-qat-fix-mutex-ordering-in-adf_rl.patch @@ -0,0 +1,46 @@ +From 0d05a889cc181f44207cab27bca39ed857fdb11f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 18:39:30 +0100 +Subject: crypto: qat - fix mutex ordering in adf_rl + +From: Damian Muszynski + +[ Upstream commit 487caa8d5ef9a9a27b092c5790d529a7a0c24f8b ] + +If the function validate_user_input() returns an error, the error path +attempts to unlock an unacquired mutex. +Acquire the mutex before calling validate_user_input(). This is not +strictly necessary but simplifies the code. + +Fixes: d9fb8408376e ("crypto: qat - add rate limiting feature to qat_4xxx") +Signed-off-by: Damian Muszynski +Reviewed-by: Giovanni Cabiddu +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_rl.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.c b/drivers/crypto/intel/qat/qat_common/adf_rl.c +index f2de3cd7d05d..de1b214dba1f 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_rl.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_rl.c +@@ -815,13 +815,13 @@ static int add_update_sla(struct adf_accel_dev *accel_dev, + return -EFAULT; + } + ++ mutex_lock(&rl_data->rl_lock); ++ + /* Input validation */ + ret = validate_user_input(accel_dev, sla_in, is_update); + if (ret) + goto ret_err; + +- mutex_lock(&rl_data->rl_lock); +- + if (is_update) { + ret = validate_sla_id(accel_dev, sla_in->sla_id); + if (ret) +-- +2.43.0 + diff --git a/queue-6.7/crypto-qat-prevent-underflow-in-rp2srv_store.patch b/queue-6.7/crypto-qat-prevent-underflow-in-rp2srv_store.patch new file mode 100644 index 00000000000..8485a39e07b --- /dev/null +++ b/queue-6.7/crypto-qat-prevent-underflow-in-rp2srv_store.patch @@ -0,0 +1,39 @@ +From 35d6df5eabc3bc7c061d4349e3a724f73662385b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 Oct 2023 11:58:32 +0300 +Subject: crypto: qat - prevent underflow in rp2srv_store() + +From: Dan Carpenter + +[ Upstream commit e53c741303a59ee1682e11f61b7772863e02526d ] + +The "ring" variable has an upper bounds check but nothing checks for +negatives. This code uses kstrtouint() already and it was obviously +intended to be declared as unsigned int. Make it so. + +Fixes: dbc8876dd873 ("crypto: qat - add rp2svc sysfs attribute") +Signed-off-by: Dan Carpenter +Acked-by: Giovanni Cabiddu +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/intel/qat/qat_common/adf_sysfs.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c +index ddffc98119c6..6f0b3629da13 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c +@@ -242,7 +242,8 @@ static ssize_t rp2srv_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) + { + struct adf_accel_dev *accel_dev; +- int ring, num_rings, ret; ++ int num_rings, ret; ++ unsigned int ring; + + accel_dev = adf_devmgr_pci_to_accel_dev(to_pci_dev(dev)); + if (!accel_dev) +-- +2.43.0 + diff --git a/queue-6.7/crypto-rsa-add-a-check-for-allocation-failure.patch b/queue-6.7/crypto-rsa-add-a-check-for-allocation-failure.patch new file mode 100644 index 00000000000..daf9bbff0f0 --- /dev/null +++ b/queue-6.7/crypto-rsa-add-a-check-for-allocation-failure.patch @@ -0,0 +1,38 @@ +From 60dce805e02c466df53513d152c752f31972ef31 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Oct 2023 12:02:59 +0300 +Subject: crypto: rsa - add a check for allocation failure + +From: Dan Carpenter + +[ Upstream commit d872ca165cb67112f2841ef9c37d51ef7e63d1e4 ] + +Static checkers insist that the mpi_alloc() allocation can fail so add +a check to prevent a NULL dereference. Small allocations like this +can't actually fail in current kernels, but adding a check is very +simple and makes the static checkers happy. + +Fixes: 6637e11e4ad2 ("crypto: rsa - allow only odd e and restrict value in FIPS mode") +Signed-off-by: Dan Carpenter +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/rsa.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/crypto/rsa.c b/crypto/rsa.c +index c79613cdce6e..b9cd11fb7d36 100644 +--- a/crypto/rsa.c ++++ b/crypto/rsa.c +@@ -220,6 +220,8 @@ static int rsa_check_exponent_fips(MPI e) + } + + e_max = mpi_alloc(0); ++ if (!e_max) ++ return -ENOMEM; + mpi_set_bit(e_max, 256); + + if (mpi_cmp(e, e_max) >= 0) { +-- +2.43.0 + diff --git a/queue-6.7/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch b/queue-6.7/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch new file mode 100644 index 00000000000..c1e8b75bd90 --- /dev/null +++ b/queue-6.7/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch @@ -0,0 +1,38 @@ +From 1e725cd40fba2fece742942c440978f74fb51caa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 02:03:01 +0000 +Subject: crypto: sa2ul - Return crypto_aead_setkey to transfer the error + +From: Chen Ni + +[ Upstream commit ce852f1308ac738e61c5b2502517deea593a1554 ] + +Return crypto_aead_setkey() in order to transfer the error if +it fails. + +Fixes: d2c8ac187fc9 ("crypto: sa2ul - Add AEAD algorithm support") +Signed-off-by: Chen Ni +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sa2ul.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c +index 6846a8429574..78a4930c6480 100644 +--- a/drivers/crypto/sa2ul.c ++++ b/drivers/crypto/sa2ul.c +@@ -1869,9 +1869,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, + crypto_aead_set_flags(ctx->fallback.aead, + crypto_aead_get_flags(authenc) & + CRYPTO_TFM_REQ_MASK); +- crypto_aead_setkey(ctx->fallback.aead, key, keylen); + +- return 0; ++ return crypto_aead_setkey(ctx->fallback.aead, key, keylen); + } + + static int sa_aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize) +-- +2.43.0 + diff --git a/queue-6.7/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch b/queue-6.7/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch new file mode 100644 index 00000000000..adcb733c084 --- /dev/null +++ b/queue-6.7/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch @@ -0,0 +1,72 @@ +From ef559ab3c3178a50f67e292d52b418099760eacd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 04:49:29 -0800 +Subject: crypto: safexcel - Add error handling for dma_map_sg() calls + +From: Nikita Zhandarovich + +[ Upstream commit 87e02063d07708cac5bfe9fd3a6a242898758ac8 ] + +Macro dma_map_sg() may return 0 on error. This patch enables +checks in case of the macro failure and ensures unmapping of +previously mapped buffers with dma_unmap_sg(). + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 49186a7d9e46 ("crypto: inside_secure - Avoid dma map if size is zero") +Signed-off-by: Nikita Zhandarovich +Reviewed-by: Antoine Tenart +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + .../crypto/inside-secure/safexcel_cipher.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/drivers/crypto/inside-secure/safexcel_cipher.c b/drivers/crypto/inside-secure/safexcel_cipher.c +index 272c28b5a088..b83818634ae4 100644 +--- a/drivers/crypto/inside-secure/safexcel_cipher.c ++++ b/drivers/crypto/inside-secure/safexcel_cipher.c +@@ -742,9 +742,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + max(totlen_src, totlen_dst)); + return -EINVAL; + } +- if (sreq->nr_src > 0) +- dma_map_sg(priv->dev, src, sreq->nr_src, +- DMA_BIDIRECTIONAL); ++ if (sreq->nr_src > 0 && ++ !dma_map_sg(priv->dev, src, sreq->nr_src, DMA_BIDIRECTIONAL)) ++ return -EIO; + } else { + if (unlikely(totlen_src && (sreq->nr_src <= 0))) { + dev_err(priv->dev, "Source buffer not large enough (need %d bytes)!", +@@ -752,8 +752,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + return -EINVAL; + } + +- if (sreq->nr_src > 0) +- dma_map_sg(priv->dev, src, sreq->nr_src, DMA_TO_DEVICE); ++ if (sreq->nr_src > 0 && ++ !dma_map_sg(priv->dev, src, sreq->nr_src, DMA_TO_DEVICE)) ++ return -EIO; + + if (unlikely(totlen_dst && (sreq->nr_dst <= 0))) { + dev_err(priv->dev, "Dest buffer not large enough (need %d bytes)!", +@@ -762,9 +763,11 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + goto unmap; + } + +- if (sreq->nr_dst > 0) +- dma_map_sg(priv->dev, dst, sreq->nr_dst, +- DMA_FROM_DEVICE); ++ if (sreq->nr_dst > 0 && ++ !dma_map_sg(priv->dev, dst, sreq->nr_dst, DMA_FROM_DEVICE)) { ++ ret = -EIO; ++ goto unmap; ++ } + } + + memcpy(ctx->base.ctxr->data, ctx->key, ctx->key_len); +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch b/queue-6.7/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch new file mode 100644 index 00000000000..e82ee3f719a --- /dev/null +++ b/queue-6.7/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch @@ -0,0 +1,148 @@ +From cc55b833609f4248514a9552cee5164b4f8fa6dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:25 +0200 +Subject: crypto: sahara - avoid skcipher fallback code duplication + +From: Ovidiu Panait + +[ Upstream commit 01d70a4bbff20ea05cadb4c208841985a7cc6596 ] + +Factor out duplicated skcipher fallback handling code to a helper function +sahara_aes_fallback(). Also, keep a single check if fallback is required in +sahara_aes_crypt(). + +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Stable-dep-of: d1d6351e37aa ("crypto: sahara - handle zero-length aes requests") +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 85 ++++++++++++----------------------------- + 1 file changed, 25 insertions(+), 60 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index c4eb66d2e08d..0771c7160c47 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -648,12 +648,37 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + return crypto_skcipher_setkey(ctx->fallback, key, keylen); + } + ++static int sahara_aes_fallback(struct skcipher_request *req, unsigned long mode) ++{ ++ struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ struct sahara_ctx *ctx = crypto_skcipher_ctx( ++ crypto_skcipher_reqtfm(req)); ++ ++ skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); ++ skcipher_request_set_callback(&rctx->fallback_req, ++ req->base.flags, ++ req->base.complete, ++ req->base.data); ++ skcipher_request_set_crypt(&rctx->fallback_req, req->src, ++ req->dst, req->cryptlen, req->iv); ++ ++ if (mode & FLAGS_ENCRYPT) ++ return crypto_skcipher_encrypt(&rctx->fallback_req); ++ ++ return crypto_skcipher_decrypt(&rctx->fallback_req); ++} ++ + static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + { + struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ struct sahara_ctx *ctx = crypto_skcipher_ctx( ++ crypto_skcipher_reqtfm(req)); + struct sahara_dev *dev = dev_ptr; + int err = 0; + ++ if (unlikely(ctx->keylen != AES_KEYSIZE_128)) ++ return sahara_aes_fallback(req, mode); ++ + dev_dbg(dev->device, "nbytes: %d, enc: %d, cbc: %d\n", + req->cryptlen, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC)); + +@@ -676,81 +701,21 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + + static int sahara_aes_ecb_encrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_encrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_ENCRYPT); + } + + static int sahara_aes_ecb_decrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_decrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, 0); + } + + static int sahara_aes_cbc_encrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_encrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); + } + + static int sahara_aes_cbc_decrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_decrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_CBC); + } + +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch b/queue-6.7/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch new file mode 100644 index 00000000000..c2c42e80076 --- /dev/null +++ b/queue-6.7/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch @@ -0,0 +1,99 @@ +From 9f654beebf77fe7eed943d1d32a8c9c520829808 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:36 +0200 +Subject: crypto: sahara - do not resize req->src when doing hash operations + +From: Ovidiu Panait + +[ Upstream commit a3c6f4f4d249cecaf2f34471aadbfb4f4ef57298 ] + +When testing sahara sha256 speed performance with tcrypt (mode=404) on +imx53-qsrb board, multiple "Invalid numbers of src SG." errors are +reported. This was traced to sahara_walk_and_recalc() resizing req->src +and causing the subsequent dma_map_sg() call to fail. + +Now that the previous commit fixed sahara_sha_hw_links_create() to take +into account the actual request size, rather than relying on sg->length +values, the resize operation is no longer necessary. + +Therefore, remove sahara_walk_and_recalc() and simplify associated logic. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 38 ++------------------------------------ + 1 file changed, 2 insertions(+), 36 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index dd8291a4442c..fabe4f381fb6 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -886,24 +886,6 @@ static int sahara_sha_hw_context_descriptor_create(struct sahara_dev *dev, + return 0; + } + +-static int sahara_walk_and_recalc(struct scatterlist *sg, unsigned int nbytes) +-{ +- if (!sg || !sg->length) +- return nbytes; +- +- while (nbytes && sg) { +- if (nbytes <= sg->length) { +- sg->length = nbytes; +- sg_mark_end(sg); +- break; +- } +- nbytes -= sg->length; +- sg = sg_next(sg); +- } +- +- return nbytes; +-} +- + static int sahara_sha_prepare_request(struct ahash_request *req) + { + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); +@@ -940,36 +922,20 @@ static int sahara_sha_prepare_request(struct ahash_request *req) + hash_later, 0); + } + +- /* nbytes should now be multiple of blocksize */ +- req->nbytes = req->nbytes - hash_later; +- +- sahara_walk_and_recalc(req->src, req->nbytes); +- ++ rctx->total = len - hash_later; + /* have data from previous operation and current */ + if (rctx->buf_cnt && req->nbytes) { + sg_init_table(rctx->in_sg_chain, 2); + sg_set_buf(rctx->in_sg_chain, rctx->rembuf, rctx->buf_cnt); +- + sg_chain(rctx->in_sg_chain, 2, req->src); +- +- rctx->total = req->nbytes + rctx->buf_cnt; + rctx->in_sg = rctx->in_sg_chain; +- +- req->src = rctx->in_sg_chain; + /* only data from previous operation */ + } else if (rctx->buf_cnt) { +- if (req->src) +- rctx->in_sg = req->src; +- else +- rctx->in_sg = rctx->in_sg_chain; +- /* buf was copied into rembuf above */ ++ rctx->in_sg = rctx->in_sg_chain; + sg_init_one(rctx->in_sg, rctx->rembuf, rctx->buf_cnt); +- rctx->total = rctx->buf_cnt; + /* no data from previous operation */ + } else { + rctx->in_sg = req->src; +- rctx->total = req->nbytes; +- req->src = rctx->in_sg; + } + + /* on next call, we only have the remaining data in the buffer */ +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-ahash-reqsize.patch b/queue-6.7/crypto-sahara-fix-ahash-reqsize.patch new file mode 100644 index 00000000000..e1fdba9fbfd --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-ahash-reqsize.patch @@ -0,0 +1,37 @@ +From bca7cda50827eef52d1c7f7111967a0066bffac9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:32 +0200 +Subject: crypto: sahara - fix ahash reqsize + +From: Ovidiu Panait + +[ Upstream commit efcb50f41740ac55e6ccc4986c1a7740e21c62b4 ] + +Set the reqsize for sha algorithms to sizeof(struct sahara_sha_reqctx), the +extra space is not needed. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 78666b82ac80..31973e6ce520 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -1162,8 +1162,7 @@ static int sahara_sha_import(struct ahash_request *req, const void *in) + static int sahara_sha_cra_init(struct crypto_tfm *tfm) + { + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), +- sizeof(struct sahara_sha_reqctx) + +- SHA_BUFFER_LEN + SHA256_BLOCK_SIZE); ++ sizeof(struct sahara_sha_reqctx)); + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-ahash-selftest-failure.patch b/queue-6.7/crypto-sahara-fix-ahash-selftest-failure.patch new file mode 100644 index 00000000000..d15a18a3a0f --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-ahash-selftest-failure.patch @@ -0,0 +1,41 @@ +From 99ad45eb354d831bea5f440cd76bd4d9998c992d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:21 +0200 +Subject: crypto: sahara - fix ahash selftest failure + +From: Ovidiu Panait + +[ Upstream commit afffcf3db98b9495114b79d5381f8cc3f69476fb ] + +update() calls should not modify the result buffer, so add an additional +check for "rctx->last" to make sure that only the final hash value is +copied into the buffer. + +Fixes the following selftest failure: +alg: ahash: sahara-sha256 update() used result buffer on test vector 3, +cfg="init+update+final aligned buffer" + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 888e5e5157bb..863171b44cda 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -1047,7 +1047,7 @@ static int sahara_sha_process(struct ahash_request *req) + + memcpy(rctx->context, dev->context_base, rctx->context_size); + +- if (req->result) ++ if (req->result && rctx->last) + memcpy(req->result, rctx->context, rctx->digest_size); + + return 0; +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-cbc-selftest-failure.patch b/queue-6.7/crypto-sahara-fix-cbc-selftest-failure.patch new file mode 100644 index 00000000000..4b74a3fc081 --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-cbc-selftest-failure.patch @@ -0,0 +1,94 @@ +From a1aa8df10afa7b16c611457c5c78d5ea39e63878 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:20 +0200 +Subject: crypto: sahara - fix cbc selftest failure + +From: Ovidiu Panait + +[ Upstream commit 9f10bc28c0fb676ae58aa3bfa358db8f5de124bb ] + +The kernel crypto API requires that all CBC implementations update the IV +buffer to contain the last ciphertext block. + +This fixes the following cbc selftest error: +alg: skcipher: sahara-cbc-aes encryption test failed (wrong output IV) on +test vector 0, cfg="in-place (one sglist)" + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 33 +++++++++++++++++++++++++++++++-- + 1 file changed, 31 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 5cc1cd59a384..888e5e5157bb 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -148,6 +148,7 @@ struct sahara_ctx { + + struct sahara_aes_reqctx { + unsigned long mode; ++ u8 iv_out[AES_BLOCK_SIZE]; + struct skcipher_request fallback_req; // keep at the end + }; + +@@ -541,8 +542,24 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + return -EINVAL; + } + ++static void sahara_aes_cbc_update_iv(struct skcipher_request *req) ++{ ++ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); ++ struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ unsigned int ivsize = crypto_skcipher_ivsize(skcipher); ++ ++ /* Update IV buffer to contain the last ciphertext block */ ++ if (rctx->mode & FLAGS_ENCRYPT) { ++ sg_pcopy_to_buffer(req->dst, sg_nents(req->dst), req->iv, ++ ivsize, req->cryptlen - ivsize); ++ } else { ++ memcpy(req->iv, rctx->iv_out, ivsize); ++ } ++} ++ + static int sahara_aes_process(struct skcipher_request *req) + { ++ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); + struct sahara_dev *dev = dev_ptr; + struct sahara_ctx *ctx; + struct sahara_aes_reqctx *rctx; +@@ -564,8 +581,17 @@ static int sahara_aes_process(struct skcipher_request *req) + rctx->mode &= FLAGS_MODE_MASK; + dev->flags = (dev->flags & ~FLAGS_MODE_MASK) | rctx->mode; + +- if ((dev->flags & FLAGS_CBC) && req->iv) +- memcpy(dev->iv_base, req->iv, AES_KEYSIZE_128); ++ if ((dev->flags & FLAGS_CBC) && req->iv) { ++ unsigned int ivsize = crypto_skcipher_ivsize(skcipher); ++ ++ memcpy(dev->iv_base, req->iv, ivsize); ++ ++ if (!(dev->flags & FLAGS_ENCRYPT)) { ++ sg_pcopy_to_buffer(req->src, sg_nents(req->src), ++ rctx->iv_out, ivsize, ++ req->cryptlen - ivsize); ++ } ++ } + + /* assign new context to device */ + dev->ctx = ctx; +@@ -588,6 +614,9 @@ static int sahara_aes_process(struct skcipher_request *req) + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if ((dev->flags & FLAGS_CBC) && req->iv) ++ sahara_aes_cbc_update_iv(req); ++ + return 0; + } + +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch b/queue-6.7/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch new file mode 100644 index 00000000000..508be244469 --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch @@ -0,0 +1,54 @@ +From b5f4a938930eb4443d3b0ba12b14174c6536c83c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:23 +0200 +Subject: crypto: sahara - fix error handling in sahara_hw_descriptor_create() + +From: Ovidiu Panait + +[ Upstream commit ee6e6f0a7f5b39d50a5ef5fcc006f4f693db18a7 ] + +Do not call dma_unmap_sg() for scatterlists that were not mapped +successfully. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index cbb7153e4162..c4eb66d2e08d 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -483,13 +483,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + DMA_TO_DEVICE); + if (!ret) { + dev_err(dev->device, "couldn't map in sg\n"); +- goto unmap_in; ++ return -EINVAL; + } ++ + ret = dma_map_sg(dev->device, dev->out_sg, dev->nb_out_sg, + DMA_FROM_DEVICE); + if (!ret) { + dev_err(dev->device, "couldn't map out sg\n"); +- goto unmap_out; ++ goto unmap_in; + } + + /* Create input links */ +@@ -537,9 +538,6 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + + return 0; + +-unmap_out: +- dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg, +- DMA_FROM_DEVICE); + unmap_in: + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-processing-hash-requests-with-req-.patch b/queue-6.7/crypto-sahara-fix-processing-hash-requests-with-req-.patch new file mode 100644 index 00000000000..b5cfee96b2a --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-processing-hash-requests-with-req-.patch @@ -0,0 +1,56 @@ +From 6cca63b3143f23b5c0597e6c059159909a39ec9d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:35 +0200 +Subject: crypto: sahara - fix processing hash requests with req->nbytes < + sg->length + +From: Ovidiu Panait + +[ Upstream commit 7bafa74d1ba35dcc173e1ce915e983d65905f77e ] + +It's not always the case that the entire sg entry needs to be processed. +Currently, when nbytes is less than sg->length, "Descriptor length" errors +are encountered. + +To fix this, take the actual request size into account when populating the +hw links. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index cfb02905c1ab..dd8291a4442c 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -776,6 +776,7 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, + int start) + { + struct scatterlist *sg; ++ unsigned int len; + unsigned int i; + int ret; + +@@ -797,12 +798,14 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, + if (!ret) + return -EFAULT; + ++ len = rctx->total; + for (i = start; i < dev->nb_in_sg + start; i++) { +- dev->hw_link[i]->len = sg->length; ++ dev->hw_link[i]->len = min(len, sg->length); + dev->hw_link[i]->p = sg->dma_address; + if (i == (dev->nb_in_sg + start - 1)) { + dev->hw_link[i]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[i]->next = dev->hw_phys_link[i + 1]; + sg = sg_next(sg); + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-processing-requests-with-cryptlen-.patch b/queue-6.7/crypto-sahara-fix-processing-requests-with-cryptlen-.patch new file mode 100644 index 00000000000..7f94f53311f --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-processing-requests-with-cryptlen-.patch @@ -0,0 +1,72 @@ +From 9c5ecf0d96c495e327a1ff2245aa46c4efb9b8f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:22 +0200 +Subject: crypto: sahara - fix processing requests with cryptlen < sg->length + +From: Ovidiu Panait + +[ Upstream commit 5b8668ce3452827d27f8c34ff6ba080a8f983ed0 ] + +It's not always the case that the entire sg entry needs to be processed. +Currently, when cryptlen is less than sg->legth, "Descriptor length" errors +are encountered. + +The error was noticed when testing xts(sahara-ecb-aes) with arbitrary sized +input data. To fix this, take the actual request size into account when +populating the hw links. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 863171b44cda..cbb7153e4162 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -444,6 +444,7 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + int ret; + int i, j; + int idx = 0; ++ u32 len; + + memcpy(dev->key_base, ctx->key, ctx->keylen); + +@@ -494,12 +495,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + /* Create input links */ + dev->hw_desc[idx]->p1 = dev->hw_phys_link[0]; + sg = dev->in_sg; ++ len = dev->total; + for (i = 0; i < dev->nb_in_sg; i++) { +- dev->hw_link[i]->len = sg->length; ++ dev->hw_link[i]->len = min(len, sg->length); + dev->hw_link[i]->p = sg->dma_address; + if (i == (dev->nb_in_sg - 1)) { + dev->hw_link[i]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[i]->next = dev->hw_phys_link[i + 1]; + sg = sg_next(sg); + } +@@ -508,12 +511,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + /* Create output links */ + dev->hw_desc[idx]->p2 = dev->hw_phys_link[i]; + sg = dev->out_sg; ++ len = dev->total; + for (j = i; j < dev->nb_out_sg + i; j++) { +- dev->hw_link[j]->len = sg->length; ++ dev->hw_link[j]->len = min(len, sg->length); + dev->hw_link[j]->p = sg->dma_address; + if (j == (dev->nb_out_sg + i - 1)) { + dev->hw_link[j]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[j]->next = dev->hw_phys_link[j + 1]; + sg = sg_next(sg); + } +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-fix-wait_for_completion_timeout-error-.patch b/queue-6.7/crypto-sahara-fix-wait_for_completion_timeout-error-.patch new file mode 100644 index 00000000000..65a4aa103b1 --- /dev/null +++ b/queue-6.7/crypto-sahara-fix-wait_for_completion_timeout-error-.patch @@ -0,0 +1,70 @@ +From ff6fcaec28e2f16e41ca92cd571f483f6124a21c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:33 +0200 +Subject: crypto: sahara - fix wait_for_completion_timeout() error handling + +From: Ovidiu Panait + +[ Upstream commit 2dba8e1d1a7957dcbe7888846268538847b471d1 ] + +The sg lists are not unmapped in case of timeout errors. Fix this. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 31973e6ce520..3661f02d131a 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -607,16 +607,17 @@ static int sahara_aes_process(struct skcipher_request *req) + + timeout = wait_for_completion_timeout(&dev->dma_completion, + msecs_to_jiffies(SAHARA_TIMEOUT_MS)); +- if (!timeout) { +- dev_err(dev->device, "AES timeout\n"); +- return -ETIMEDOUT; +- } + + dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg, + DMA_FROM_DEVICE); + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if (!timeout) { ++ dev_err(dev->device, "AES timeout\n"); ++ return -ETIMEDOUT; ++ } ++ + if ((dev->flags & FLAGS_CBC) && req->iv) + sahara_aes_cbc_update_iv(req); + +@@ -1007,15 +1008,16 @@ static int sahara_sha_process(struct ahash_request *req) + + timeout = wait_for_completion_timeout(&dev->dma_completion, + msecs_to_jiffies(SAHARA_TIMEOUT_MS)); +- if (!timeout) { +- dev_err(dev->device, "SHA timeout\n"); +- return -ETIMEDOUT; +- } + + if (rctx->sg_in_idx) + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if (!timeout) { ++ dev_err(dev->device, "SHA timeout\n"); ++ return -ETIMEDOUT; ++ } ++ + memcpy(rctx->context, dev->context_base, rctx->context_size); + + if (req->result && rctx->last) +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-handle-zero-length-aes-requests.patch b/queue-6.7/crypto-sahara-handle-zero-length-aes-requests.patch new file mode 100644 index 00000000000..fe42cad582f --- /dev/null +++ b/queue-6.7/crypto-sahara-handle-zero-length-aes-requests.patch @@ -0,0 +1,36 @@ +From 791747a6d387285bdf26dcf0f0c5cdaeb6686987 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:31 +0200 +Subject: crypto: sahara - handle zero-length aes requests + +From: Ovidiu Panait + +[ Upstream commit d1d6351e37aac14b32a291731d0855996c459d11 ] + +In case of a zero-length input, exit gracefully from sahara_aes_crypt(). + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 0771c7160c47..78666b82ac80 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -676,6 +676,9 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + struct sahara_dev *dev = dev_ptr; + int err = 0; + ++ if (!req->cryptlen) ++ return 0; ++ + if (unlikely(ctx->keylen != AES_KEYSIZE_128)) + return sahara_aes_fallback(req, mode); + +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch b/queue-6.7/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch new file mode 100644 index 00000000000..8098b97531c --- /dev/null +++ b/queue-6.7/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch @@ -0,0 +1,51 @@ +From 7e0094a6d9b846e9818e2f1b71b6bf9298654a18 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:34 +0200 +Subject: crypto: sahara - improve error handling in sahara_sha_process() + +From: Ovidiu Panait + +[ Upstream commit 5deff027fca49a1eb3b20359333cf2ae562a2343 ] + +sahara_sha_hw_data_descriptor_create() returns negative error codes on +failure, so make sure the errors are correctly handled / propagated. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 3661f02d131a..cfb02905c1ab 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -987,7 +987,10 @@ static int sahara_sha_process(struct ahash_request *req) + return ret; + + if (rctx->first) { +- sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); ++ ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); ++ if (ret) ++ return ret; ++ + dev->hw_desc[0]->next = 0; + rctx->first = 0; + } else { +@@ -995,7 +998,10 @@ static int sahara_sha_process(struct ahash_request *req) + + sahara_sha_hw_context_descriptor_create(dev, rctx, req, 0); + dev->hw_desc[0]->next = dev->hw_phys_desc[1]; +- sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); ++ ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); ++ if (ret) ++ return ret; ++ + dev->hw_desc[1]->next = 0; + } + +-- +2.43.0 + diff --git a/queue-6.7/crypto-sahara-remove-flags_new_key-logic.patch b/queue-6.7/crypto-sahara-remove-flags_new_key-logic.patch new file mode 100644 index 00000000000..ef3fd7acb72 --- /dev/null +++ b/queue-6.7/crypto-sahara-remove-flags_new_key-logic.patch @@ -0,0 +1,105 @@ +From 6571d5ae061bea62c3389f85de9bd9b58e5cf3b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:19 +0200 +Subject: crypto: sahara - remove FLAGS_NEW_KEY logic + +From: Ovidiu Panait + +[ Upstream commit 8fd183435728b139248a77978ea3732039341779 ] + +Remove the FLAGS_NEW_KEY logic as it has the following issues: +- the wrong key may end up being used when there are multiple data streams: + t1 t2 + setkey() + encrypt() + setkey() + encrypt() + + encrypt() <--- key from t2 is used +- switching between encryption and decryption with the same key is not + possible, as the hdr flags are only updated when a new setkey() is + performed + +With this change, the key is always sent along with the cryptdata when +performing encryption/decryption operations. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 34 +++++++++++++--------------------- + 1 file changed, 13 insertions(+), 21 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 02065131c300..5cc1cd59a384 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -43,7 +43,6 @@ + #define FLAGS_MODE_MASK 0x000f + #define FLAGS_ENCRYPT BIT(0) + #define FLAGS_CBC BIT(1) +-#define FLAGS_NEW_KEY BIT(3) + + #define SAHARA_HDR_BASE 0x00800000 + #define SAHARA_HDR_SKHA_ALG_AES 0 +@@ -141,8 +140,6 @@ struct sahara_hw_link { + }; + + struct sahara_ctx { +- unsigned long flags; +- + /* AES-specific context */ + int keylen; + u8 key[AES_KEYSIZE_128]; +@@ -447,26 +444,22 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + int i, j; + int idx = 0; + +- /* Copy new key if necessary */ +- if (ctx->flags & FLAGS_NEW_KEY) { +- memcpy(dev->key_base, ctx->key, ctx->keylen); +- ctx->flags &= ~FLAGS_NEW_KEY; ++ memcpy(dev->key_base, ctx->key, ctx->keylen); + +- if (dev->flags & FLAGS_CBC) { +- dev->hw_desc[idx]->len1 = AES_BLOCK_SIZE; +- dev->hw_desc[idx]->p1 = dev->iv_phys_base; +- } else { +- dev->hw_desc[idx]->len1 = 0; +- dev->hw_desc[idx]->p1 = 0; +- } +- dev->hw_desc[idx]->len2 = ctx->keylen; +- dev->hw_desc[idx]->p2 = dev->key_phys_base; +- dev->hw_desc[idx]->next = dev->hw_phys_desc[1]; ++ if (dev->flags & FLAGS_CBC) { ++ dev->hw_desc[idx]->len1 = AES_BLOCK_SIZE; ++ dev->hw_desc[idx]->p1 = dev->iv_phys_base; ++ } else { ++ dev->hw_desc[idx]->len1 = 0; ++ dev->hw_desc[idx]->p1 = 0; ++ } ++ dev->hw_desc[idx]->len2 = ctx->keylen; ++ dev->hw_desc[idx]->p2 = dev->key_phys_base; ++ dev->hw_desc[idx]->next = dev->hw_phys_desc[1]; ++ dev->hw_desc[idx]->hdr = sahara_aes_key_hdr(dev); + +- dev->hw_desc[idx]->hdr = sahara_aes_key_hdr(dev); ++ idx++; + +- idx++; +- } + + dev->nb_in_sg = sg_nents_for_len(dev->in_sg, dev->total); + if (dev->nb_in_sg < 0) { +@@ -608,7 +601,6 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + /* SAHARA only supports 128bit keys */ + if (keylen == AES_KEYSIZE_128) { + memcpy(ctx->key, key, keylen); +- ctx->flags |= FLAGS_NEW_KEY; + return 0; + } + +-- +2.43.0 + diff --git a/queue-6.7/crypto-scomp-fix-req-dst-buffer-overflow.patch b/queue-6.7/crypto-scomp-fix-req-dst-buffer-overflow.patch new file mode 100644 index 00000000000..5298b716329 --- /dev/null +++ b/queue-6.7/crypto-scomp-fix-req-dst-buffer-overflow.patch @@ -0,0 +1,57 @@ +From ffa5e50dd5d764cea9130c95bf5f737ec61c4b0f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Dec 2023 09:35:23 +0000 +Subject: crypto: scomp - fix req->dst buffer overflow + +From: Chengming Zhou + +[ Upstream commit 744e1885922a9943458954cfea917b31064b4131 ] + +The req->dst buffer size should be checked before copying from the +scomp_scratch->dst to avoid req->dst buffer overflow problem. + +Fixes: 1ab53a77b772 ("crypto: acomp - add driver-side scomp interface") +Reported-by: syzbot+3eff5e51bf1db122a16e@syzkaller.appspotmail.com +Closes: https://lore.kernel.org/all/0000000000000b05cd060d6b5511@google.com/ +Signed-off-by: Chengming Zhou +Reviewed-by: Barry Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/scompress.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/crypto/scompress.c b/crypto/scompress.c +index 442a82c9de7d..b108a30a7600 100644 +--- a/crypto/scompress.c ++++ b/crypto/scompress.c +@@ -117,6 +117,7 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + struct crypto_scomp *scomp = *tfm_ctx; + void **ctx = acomp_request_ctx(req); + struct scomp_scratch *scratch; ++ unsigned int dlen; + int ret; + + if (!req->src || !req->slen || req->slen > SCOMP_SCRATCH_SIZE) +@@ -128,6 +129,8 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + if (!req->dlen || req->dlen > SCOMP_SCRATCH_SIZE) + req->dlen = SCOMP_SCRATCH_SIZE; + ++ dlen = req->dlen; ++ + scratch = raw_cpu_ptr(&scomp_scratch); + spin_lock(&scratch->lock); + +@@ -145,6 +148,9 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + ret = -ENOMEM; + goto out; + } ++ } else if (req->dlen > dlen) { ++ ret = -ENOSPC; ++ goto out; + } + scatterwalk_map_and_copy(scratch->dst, req->dst, 0, req->dlen, + 1); +-- +2.43.0 + diff --git a/queue-6.7/crypto-virtio-handle-dataq-logic-with-tasklet.patch b/queue-6.7/crypto-virtio-handle-dataq-logic-with-tasklet.patch new file mode 100644 index 00000000000..1a56ff11411 --- /dev/null +++ b/queue-6.7/crypto-virtio-handle-dataq-logic-with-tasklet.patch @@ -0,0 +1,99 @@ +From e73968e572b9e013f7d99a527354d97496b57b63 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 11:49:45 +0000 +Subject: crypto: virtio - Handle dataq logic with tasklet + +From: Gonglei (Arei) + +[ Upstream commit fed93fb62e05c38152b0fc1dc9609639e63eed76 ] + +Doing ipsec produces a spinlock recursion warning. +This is due to crypto_finalize_request() being called in the upper half. +Move virtual data queue processing of virtio-crypto driver to tasklet. + +Fixes: dbaf0624ffa57 ("crypto: add virtio-crypto driver") +Reported-by: Halil Pasic +Signed-off-by: wangyangxin +Signed-off-by: Gonglei +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/virtio/virtio_crypto_common.h | 2 ++ + drivers/crypto/virtio/virtio_crypto_core.c | 23 +++++++++++--------- + 2 files changed, 15 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/virtio/virtio_crypto_common.h b/drivers/crypto/virtio/virtio_crypto_common.h +index 154590e1f764..7059bbe5a2eb 100644 +--- a/drivers/crypto/virtio/virtio_crypto_common.h ++++ b/drivers/crypto/virtio/virtio_crypto_common.h +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ struct data_queue { + char name[32]; + + struct crypto_engine *engine; ++ struct tasklet_struct done_task; + }; + + struct virtio_crypto { +diff --git a/drivers/crypto/virtio/virtio_crypto_core.c b/drivers/crypto/virtio/virtio_crypto_core.c +index 43a0838d31ff..428d76562447 100644 +--- a/drivers/crypto/virtio/virtio_crypto_core.c ++++ b/drivers/crypto/virtio/virtio_crypto_core.c +@@ -72,27 +72,28 @@ int virtio_crypto_ctrl_vq_request(struct virtio_crypto *vcrypto, struct scatterl + return 0; + } + +-static void virtcrypto_dataq_callback(struct virtqueue *vq) ++static void virtcrypto_done_task(unsigned long data) + { +- struct virtio_crypto *vcrypto = vq->vdev->priv; ++ struct data_queue *data_vq = (struct data_queue *)data; ++ struct virtqueue *vq = data_vq->vq; + struct virtio_crypto_request *vc_req; +- unsigned long flags; + unsigned int len; +- unsigned int qid = vq->index; + +- spin_lock_irqsave(&vcrypto->data_vq[qid].lock, flags); + do { + virtqueue_disable_cb(vq); + while ((vc_req = virtqueue_get_buf(vq, &len)) != NULL) { +- spin_unlock_irqrestore( +- &vcrypto->data_vq[qid].lock, flags); + if (vc_req->alg_cb) + vc_req->alg_cb(vc_req, len); +- spin_lock_irqsave( +- &vcrypto->data_vq[qid].lock, flags); + } + } while (!virtqueue_enable_cb(vq)); +- spin_unlock_irqrestore(&vcrypto->data_vq[qid].lock, flags); ++} ++ ++static void virtcrypto_dataq_callback(struct virtqueue *vq) ++{ ++ struct virtio_crypto *vcrypto = vq->vdev->priv; ++ struct data_queue *dq = &vcrypto->data_vq[vq->index]; ++ ++ tasklet_schedule(&dq->done_task); + } + + static int virtcrypto_find_vqs(struct virtio_crypto *vi) +@@ -150,6 +151,8 @@ static int virtcrypto_find_vqs(struct virtio_crypto *vi) + ret = -ENOMEM; + goto err_engine; + } ++ tasklet_init(&vi->data_vq[i].done_task, virtcrypto_done_task, ++ (unsigned long)&vi->data_vq[i]); + } + + kfree(names); +-- +2.43.0 + diff --git a/queue-6.7/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch b/queue-6.7/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch new file mode 100644 index 00000000000..a67dcf16cff --- /dev/null +++ b/queue-6.7/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch @@ -0,0 +1,43 @@ +From 5efd48c9e78eea51a8ac636b2df25f19be18a5b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 19:42:15 +0800 +Subject: crypto: virtio - Wait for tasklet to complete on device remove + +From: wangyangxin + +[ Upstream commit 67cc511e8d436456cc98033e6d4ba83ebfc8e672 ] + +The scheduled tasklet needs to be executed on device remove. + +Fixes: fed93fb62e05 ("crypto: virtio - Handle dataq logic with tasklet") +Signed-off-by: wangyangxin +Signed-off-by: Gonglei +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/virtio/virtio_crypto_core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/virtio/virtio_crypto_core.c b/drivers/crypto/virtio/virtio_crypto_core.c +index 428d76562447..b909c6a2bf1c 100644 +--- a/drivers/crypto/virtio/virtio_crypto_core.c ++++ b/drivers/crypto/virtio/virtio_crypto_core.c +@@ -500,12 +500,15 @@ static void virtcrypto_free_unused_reqs(struct virtio_crypto *vcrypto) + static void virtcrypto_remove(struct virtio_device *vdev) + { + struct virtio_crypto *vcrypto = vdev->priv; ++ int i; + + dev_info(&vdev->dev, "Start virtcrypto_remove.\n"); + + flush_work(&vcrypto->config_work); + if (virtcrypto_dev_started(vcrypto)) + virtcrypto_dev_stop(vcrypto); ++ for (i = 0; i < vcrypto->max_data_queues; i++) ++ tasklet_kill(&vcrypto->data_vq[i].done_task); + virtio_reset_device(vdev); + virtcrypto_free_unused_reqs(vcrypto); + virtcrypto_clear_crypto_engines(vcrypto); +-- +2.43.0 + diff --git a/queue-6.7/csky-fix-arch_jump_label_transform_static-override.patch b/queue-6.7/csky-fix-arch_jump_label_transform_static-override.patch new file mode 100644 index 00000000000..a8bc290134a --- /dev/null +++ b/queue-6.7/csky-fix-arch_jump_label_transform_static-override.patch @@ -0,0 +1,45 @@ +From 170324f1d26ed3d9bfa00aa067ba96c685eff5fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 22:02:59 +0100 +Subject: csky: fix arch_jump_label_transform_static override + +From: Arnd Bergmann + +[ Upstream commit ca8e45c8048a2c9503c74751d25414601f730580 ] + +The arch_jump_label_transform_static() function in csky was originally meant to +override the generic __weak function, but that got changed to an #ifndef check. + +This showed up as a missing-prototype warning: +arch/csky/kernel/jump_label.c:43:6: error: no previous prototype for 'arch_jump_label_transform_static' [-Werror=missing-prototypes] + +Change the method to use the new method of having a #define and a prototype +for the global function. + +Fixes: 7e6b9db27de9 ("jump_label: make initial NOP patching the special case") +Fixes: 4e8bb4ba5a55 ("csky: Add jump-label implementation") +Reviewed-by: Guo Ren +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/csky/include/asm/jump_label.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/csky/include/asm/jump_label.h b/arch/csky/include/asm/jump_label.h +index d488ba6084bc..98a3f4b168bd 100644 +--- a/arch/csky/include/asm/jump_label.h ++++ b/arch/csky/include/asm/jump_label.h +@@ -43,5 +43,10 @@ static __always_inline bool arch_static_branch_jump(struct static_key *key, + return true; + } + ++enum jump_label_type; ++void arch_jump_label_transform_static(struct jump_entry *entry, ++ enum jump_label_type type); ++#define arch_jump_label_transform_static arch_jump_label_transform_static ++ + #endif /* __ASSEMBLY__ */ + #endif /* __ASM_CSKY_JUMP_LABEL_H */ +-- +2.43.0 + diff --git a/queue-6.7/dlm-fix-format-seq-ops-type-4.patch b/queue-6.7/dlm-fix-format-seq-ops-type-4.patch new file mode 100644 index 00000000000..0a711fffd51 --- /dev/null +++ b/queue-6.7/dlm-fix-format-seq-ops-type-4.patch @@ -0,0 +1,38 @@ +From 10f3c8e2c373440579dfcb7c7ef592445f500a24 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 14:38:58 -0500 +Subject: dlm: fix format seq ops type 4 + +From: Alexander Aring + +[ Upstream commit 367e753d5c54a414d82610eb709fe71fda6cf1c3 ] + +This patch fixes to set the type 4 format ops in case of table_open4(). +It got accidentially changed by commit 541adb0d4d10 ("fs: dlm: debugfs +for queued callbacks") and since them toss debug dumps the same format +as format 5 that are the queued ast callbacks for lkbs. + +Fixes: 541adb0d4d10 ("fs: dlm: debugfs for queued callbacks") +Signed-off-by: Alexander Aring +Signed-off-by: David Teigland +Signed-off-by: Sasha Levin +--- + fs/dlm/debug_fs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/dlm/debug_fs.c b/fs/dlm/debug_fs.c +index 42f332f46359..c587bfadeff4 100644 +--- a/fs/dlm/debug_fs.c ++++ b/fs/dlm/debug_fs.c +@@ -748,7 +748,7 @@ static int table_open4(struct inode *inode, struct file *file) + struct seq_file *seq; + int ret; + +- ret = seq_open(file, &format5_seq_ops); ++ ret = seq_open(file, &format4_seq_ops); + if (ret) + return ret; + +-- +2.43.0 + diff --git a/queue-6.7/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch b/queue-6.7/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch new file mode 100644 index 00000000000..fe48b03a366 --- /dev/null +++ b/queue-6.7/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch @@ -0,0 +1,44 @@ +From 184a06fcdb281137d580b7ca03b5e7c5391b1610 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 16:25:26 +0800 +Subject: dma-mapping: clear dev->dma_mem to NULL after freeing it + +From: Joakim Zhang + +[ Upstream commit b07bc2347672cc8c7293c64499f1488278c5ca3d ] + +Reproduced with below sequence: +dma_declare_coherent_memory()->dma_release_coherent_memory() +->dma_declare_coherent_memory()->"return -EBUSY" error + +It will return -EBUSY from the dma_assign_coherent_memory() +in dma_declare_coherent_memory(), the reason is that dev->dma_mem +pointer has not been set to NULL after it's freed. + +Fixes: cf65a0f6f6ff ("dma-mapping: move all DMA mapping code to kernel/dma") +Signed-off-by: Joakim Zhang +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + kernel/dma/coherent.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c +index c21abc77c53e..ff5683a57f77 100644 +--- a/kernel/dma/coherent.c ++++ b/kernel/dma/coherent.c +@@ -132,8 +132,10 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, + + void dma_release_coherent_memory(struct device *dev) + { +- if (dev) ++ if (dev) { + _dma_release_coherent_memory(dev->dma_mem); ++ dev->dma_mem = NULL; ++ } + } + + static void *__dma_alloc_from_coherent(struct device *dev, +-- +2.43.0 + diff --git a/queue-6.7/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch b/queue-6.7/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch new file mode 100644 index 00000000000..8c694e072dd --- /dev/null +++ b/queue-6.7/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch @@ -0,0 +1,48 @@ +From 704dfc43e5281383264fa73bc84af7075e4e71cd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 00:24:58 +0800 +Subject: drivers/amd/pm: fix a use-after-free in kv_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 28dd788382c43b330480f57cd34cde0840896743 ] + +When ps allocated by kzalloc equals to NULL, kv_parse_power_table +frees adev->pm.dpm.ps that allocated before. However, after the control +flow goes through the following call chains: + +kv_parse_power_table + |-> kv_dpm_init + |-> kv_dpm_sw_init + |-> kv_dpm_fini + +The adev->pm.dpm.ps is used in the for loop of kv_dpm_fini after its +first free in kv_parse_power_table and causes a use-after-free bug. + +Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +index 5d28c951a319..5cb4725c773f 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +@@ -2735,10 +2735,8 @@ static int kv_parse_power_table(struct amdgpu_device *adev) + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); +- if (ps == NULL) { +- kfree(adev->pm.dpm.ps); ++ if (ps == NULL) + return -ENOMEM; +- } + adev->pm.dpm.ps[i].ps_priv = ps; + k = 0; + idx = (u8 *)&power_state->v2.clockInfoIndex[0]; +-- +2.43.0 + diff --git a/queue-6.7/drivers-clk-zynqmp-calculate-closest-mux-rate.patch b/queue-6.7/drivers-clk-zynqmp-calculate-closest-mux-rate.patch new file mode 100644 index 00000000000..08704e979d9 --- /dev/null +++ b/queue-6.7/drivers-clk-zynqmp-calculate-closest-mux-rate.patch @@ -0,0 +1,61 @@ +From 72ac273d3092a91ddc3145d7b3e687987b3d983e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 03:29:15 -0800 +Subject: drivers: clk: zynqmp: calculate closest mux rate + +From: Jay Buddhabhatti + +[ Upstream commit b782921ddd7f84f524723090377903f399fdbbcb ] + +Currently zynqmp clock driver is not calculating closest mux rate and +because of that Linux is not setting proper frequency for CPU and +not able to set given frequency for dynamic frequency scaling. + +E.g., In current logic initial acpu clock parent and frequency as below +apll1 0 0 0 2199999978 0 0 50000 Y + acpu0_mux 0 0 0 2199999978 0 0 50000 Y + acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y + acpu0 0 0 0 2199999978 0 0 50000 Y + +After changing acpu frequency to 549999994 Hz using CPU freq scaling its +selecting incorrect parent which is not closest frequency. +rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y + acpu0_mux 0 0 0 1599999984 0 0 50000 Y + acpu0_div1 0 0 0 533333328 0 0 50000 Y + acpu0 0 0 0 533333328 0 0 50000 Y + +Parent should remain same since 549999994 = 2199999978 / 4. + +So use __clk_mux_determine_rate_closest() generic function to calculate +closest rate for mux clock. After this change its selecting correct +parent and correct clock rate. +apll1 0 0 0 2199999978 0 0 50000 Y + acpu0_mux 0 0 0 2199999978 0 0 50000 Y + acpu0_div1 0 0 0 549999995 0 0 50000 Y + acpu0 0 0 0 549999995 0 0 50000 Y + +Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") +Signed-off-by: Jay Buddhabhatti +Link: https://lore.kernel.org/r/20231129112916.23125-2-jay.buddhabhatti@amd.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c +index 60359333f26d..9b5d3050b742 100644 +--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c ++++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c +@@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) + static const struct clk_ops zynqmp_clk_mux_ops = { + .get_parent = zynqmp_clk_mux_get_parent, + .set_parent = zynqmp_clk_mux_set_parent, +- .determine_rate = __clk_mux_determine_rate, ++ .determine_rate = __clk_mux_determine_rate_closest, + }; + + static const struct clk_ops zynqmp_clk_mux_ro_ops = { +-- +2.43.0 + diff --git a/queue-6.7/drivers-clk-zynqmp-update-divider-round-rate-logic.patch b/queue-6.7/drivers-clk-zynqmp-update-divider-round-rate-logic.patch new file mode 100644 index 00000000000..64ff707d702 --- /dev/null +++ b/queue-6.7/drivers-clk-zynqmp-update-divider-round-rate-logic.patch @@ -0,0 +1,121 @@ +From 62be2a80d553dcf481dddc658766021d1f16dcc2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 03:29:16 -0800 +Subject: drivers: clk: zynqmp: update divider round rate logic + +From: Jay Buddhabhatti + +[ Upstream commit 1fe15be1fb613534ecbac5f8c3f8744f757d237d ] + +Currently zynqmp divider round rate is considering single parent and +calculating rate and parent rate accordingly. But if divider clock flag +is set to SET_RATE_PARENT then its not trying to traverse through all +parent rate and not selecting best parent rate from that. So use common +divider_round_rate() which is traversing through all clock parents and +its rate and calculating proper parent rate. + +Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") +Signed-off-by: Jay Buddhabhatti +Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/divider.c | 66 +++--------------------------------- + 1 file changed, 5 insertions(+), 61 deletions(-) + +diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c +index 33a3b2a22659..5a00487ae408 100644 +--- a/drivers/clk/zynqmp/divider.c ++++ b/drivers/clk/zynqmp/divider.c +@@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, + return DIV_ROUND_UP_ULL(parent_rate, value); + } + +-static void zynqmp_get_divider2_val(struct clk_hw *hw, +- unsigned long rate, +- struct zynqmp_clk_divider *divider, +- u32 *bestdiv) +-{ +- int div1; +- int div2; +- long error = LONG_MAX; +- unsigned long div1_prate; +- struct clk_hw *div1_parent_hw; +- struct zynqmp_clk_divider *pdivider; +- struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); +- +- if (!div2_parent_hw) +- return; +- +- pdivider = to_zynqmp_clk_divider(div2_parent_hw); +- if (!pdivider) +- return; +- +- div1_parent_hw = clk_hw_get_parent(div2_parent_hw); +- if (!div1_parent_hw) +- return; +- +- div1_prate = clk_hw_get_rate(div1_parent_hw); +- *bestdiv = 1; +- for (div1 = 1; div1 <= pdivider->max_div;) { +- for (div2 = 1; div2 <= divider->max_div;) { +- long new_error = ((div1_prate / div1) / div2) - rate; +- +- if (abs(new_error) < abs(error)) { +- *bestdiv = div2; +- error = new_error; +- } +- if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) +- div2 = div2 << 1; +- else +- div2++; +- } +- if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) +- div1 = div1 << 1; +- else +- div1++; +- } +-} +- + /** + * zynqmp_clk_divider_round_rate() - Round rate of divider clock + * @hw: handle between common and hardware-specific interfaces +@@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, + u32 div_type = divider->div_type; + u32 bestdiv; + int ret; ++ u8 width; + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { +@@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + } + +- bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); +- +- /* +- * In case of two divisors, compute best divider values and return +- * divider2 value based on compute value. div1 will be automatically +- * set to optimum based on required total divider value. +- */ +- if (div_type == TYPE_DIV2 && +- (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { +- zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); +- } ++ width = fls(divider->max_div); + +- if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) +- bestdiv = rate % *prate ? 1 : bestdiv; ++ rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); + +- bestdiv = min_t(u32, bestdiv, divider->max_div); +- *prate = rate * bestdiv; ++ if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) ++ *prate = rate; + + return rate; + } +-- +2.43.0 + diff --git a/queue-6.7/drivers-perf-hisi-fix-some-event-id-for-hisilicon-uc.patch b/queue-6.7/drivers-perf-hisi-fix-some-event-id-for-hisilicon-uc.patch new file mode 100644 index 00000000000..c44a34e1a28 --- /dev/null +++ b/queue-6.7/drivers-perf-hisi-fix-some-event-id-for-hisilicon-uc.patch @@ -0,0 +1,39 @@ +From 6cea41eec102ec4a1b4e3dc9bc4512135d5667b0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 19:04:25 +0800 +Subject: drivers/perf: hisi: Fix some event id for HiSilicon UC pmu + +From: Junhao He + +[ Upstream commit 38bbef7240b8c5f2dc4493eec356e2efbf2da5f4 ] + +Some event id of HiSilicon uncore UC PMU driver is incorrect, fix them. + +Fixes: 312eca95e28d ("drivers/perf: hisi: Add support for HiSilicon UC PMU driver") +Signed-off-by: Junhao He +Reviewed-by: Yicong Yang +Link: https://lore.kernel.org/r/20231204110425.20354-1-hejunhao3@huawei.com +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + drivers/perf/hisilicon/hisi_uncore_uc_pmu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c +index 63da05e5831c..636fb79647c8 100644 +--- a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c ++++ b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c +@@ -383,8 +383,8 @@ static struct attribute *hisi_uc_pmu_events_attr[] = { + HISI_PMU_EVENT_ATTR(cpu_rd, 0x10), + HISI_PMU_EVENT_ATTR(cpu_rd64, 0x17), + HISI_PMU_EVENT_ATTR(cpu_rs64, 0x19), +- HISI_PMU_EVENT_ATTR(cpu_mru, 0x1a), +- HISI_PMU_EVENT_ATTR(cycles, 0x9c), ++ HISI_PMU_EVENT_ATTR(cpu_mru, 0x1c), ++ HISI_PMU_EVENT_ATTR(cycles, 0x95), + HISI_PMU_EVENT_ATTR(spipe_hit, 0xb3), + HISI_PMU_EVENT_ATTR(hpipe_hit, 0xdb), + HISI_PMU_EVENT_ATTR(cring_rxdat_cnt, 0xfa), +-- +2.43.0 + diff --git a/queue-6.7/drivers-thermal-loongson2_thermal-fix-incorrect-ptr_.patch b/queue-6.7/drivers-thermal-loongson2_thermal-fix-incorrect-ptr_.patch new file mode 100644 index 00000000000..73e2698d541 --- /dev/null +++ b/queue-6.7/drivers-thermal-loongson2_thermal-fix-incorrect-ptr_.patch @@ -0,0 +1,94 @@ +From 7c8166c90027da83d649c29c3589fe8597e3b6f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 17:57:45 +0800 +Subject: drivers/thermal/loongson2_thermal: Fix incorrect PTR_ERR() judgment + +From: Binbin Zhou + +[ Upstream commit 15ef92e9c41124ee9d88b01208364f3fe1f45f84 ] + +PTR_ERR() returns -ENODEV when thermal-zones are undefined, and we need +-ENODEV as the right value for comparison. + +Otherwise, tz->type is NULL when thermal-zones is undefined, resulting +in the following error: + +[ 12.290030] CPU 1 Unable to handle kernel paging request at virtual address fffffffffffffff1, era == 900000000355f410, ra == 90000000031579b8 +[ 12.302877] Oops[#1]: +[ 12.305190] CPU: 1 PID: 181 Comm: systemd-udevd Not tainted 6.6.0-rc7+ #5385 +[ 12.312304] pc 900000000355f410 ra 90000000031579b8 tp 90000001069e8000 sp 90000001069eba10 +[ 12.320739] a0 0000000000000000 a1 fffffffffffffff1 a2 0000000000000014 a3 0000000000000001 +[ 12.329173] a4 90000001069eb990 a5 0000000000000001 a6 0000000000001001 a7 900000010003431c +[ 12.337606] t0 fffffffffffffff1 t1 54567fd5da9b4fd4 t2 900000010614ec40 t3 00000000000dc901 +[ 12.346041] t4 0000000000000000 t5 0000000000000004 t6 900000010614ee20 t7 900000000d00b790 +[ 12.354472] t8 00000000000dc901 u0 54567fd5da9b4fd4 s9 900000000402ae10 s0 900000010614ec40 +[ 12.362916] s1 90000000039fced0 s2 ffffffffffffffed s3 ffffffffffffffed s4 9000000003acc000 +[ 12.362931] s5 0000000000000004 s6 fffffffffffff000 s7 0000000000000490 s8 90000001028b2ec8 +[ 12.362938] ra: 90000000031579b8 thermal_add_hwmon_sysfs+0x258/0x300 +[ 12.386411] ERA: 900000000355f410 strscpy+0xf0/0x160 +[ 12.391626] CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE) +[ 12.397898] PRMD: 00000004 (PPLV0 +PIE -PWE) +[ 12.403678] EUEN: 00000000 (-FPE -SXE -ASXE -BTE) +[ 12.409859] ECFG: 00071c1c (LIE=2-4,10-12 VS=7) +[ 12.415882] ESTAT: 00010000 [PIL] (IS= ECode=1 EsubCode=0) +[ 12.415907] BADV: fffffffffffffff1 +[ 12.415911] PRID: 0014a000 (Loongson-64bit, Loongson-2K1000) +[ 12.415917] Modules linked in: loongson2_thermal(+) vfat fat uio_pdrv_genirq uio fuse zram zsmalloc +[ 12.415950] Process systemd-udevd (pid: 181, threadinfo=00000000358b9718, task=00000000ace72fe3) +[ 12.415961] Stack : 0000000000000dc0 54567fd5da9b4fd4 900000000402ae10 9000000002df9358 +[ 12.415982] ffffffffffffffed 0000000000000004 9000000107a10aa8 90000001002a3410 +[ 12.415999] ffffffffffffffed ffffffffffffffed 9000000107a11268 9000000003157ab0 +[ 12.416016] 9000000107a10aa8 ffffff80020fc0c8 90000001002a3410 ffffffffffffffed +[ 12.416032] 0000000000000024 ffffff80020cc1e8 900000000402b2a0 9000000003acc000 +[ 12.416048] 90000001002a3410 0000000000000000 ffffff80020f4030 90000001002a3410 +[ 12.416065] 0000000000000000 9000000002df6808 90000001002a3410 0000000000000000 +[ 12.416081] ffffff80020f4030 0000000000000000 90000001002a3410 9000000002df2ba8 +[ 12.416097] 00000000000000b4 90000001002a34f4 90000001002a3410 0000000000000002 +[ 12.416114] ffffff80020f4030 fffffffffffffff0 90000001002a3410 9000000002df2f30 +[ 12.416131] ... +[ 12.416138] Call Trace: +[ 12.416142] [<900000000355f410>] strscpy+0xf0/0x160 +[ 12.416167] [<90000000031579b8>] thermal_add_hwmon_sysfs+0x258/0x300 +[ 12.416183] [<9000000003157ab0>] devm_thermal_add_hwmon_sysfs+0x50/0xe0 +[ 12.416200] [] loongson2_thermal_probe+0x128/0x200 [loongson2_thermal] +[ 12.416232] [<9000000002df6808>] platform_probe+0x68/0x140 +[ 12.416249] [<9000000002df2ba8>] really_probe+0xc8/0x3c0 +[ 12.416269] [<9000000002df2f30>] __driver_probe_device+0x90/0x180 +[ 12.416286] [<9000000002df3058>] driver_probe_device+0x38/0x160 +[ 12.416302] [<9000000002df33a8>] __driver_attach+0xa8/0x200 +[ 12.416314] [<9000000002deffec>] bus_for_each_dev+0x8c/0x120 +[ 12.416330] [<9000000002df198c>] bus_add_driver+0x10c/0x2a0 +[ 12.416346] [<9000000002df46b4>] driver_register+0x74/0x160 +[ 12.416358] [<90000000022201a4>] do_one_initcall+0x84/0x220 +[ 12.416372] [<90000000022f3ab8>] do_init_module+0x58/0x2c0 +[ 12.416386] [<90000000022f6538>] init_module_from_file+0x98/0x100 +[ 12.416399] [<90000000022f67f0>] sys_finit_module+0x230/0x3c0 +[ 12.416412] [<900000000358f7c8>] do_syscall+0x88/0xc0 +[ 12.416431] [<900000000222137c>] handle_syscall+0xbc/0x158 + +Fixes: e7e3a7c35791 ("thermal/drivers/loongson-2: Add thermal management support") +Cc: Yinbo Zhu +Signed-off-by: Binbin Zhou +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/343c14de98216636a47b43e8bfd47b70d0a8e068.1700817227.git.zhoubinbin@loongson.cn +Signed-off-by: Sasha Levin +--- + drivers/thermal/loongson2_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/thermal/loongson2_thermal.c b/drivers/thermal/loongson2_thermal.c +index 133098dc0854..99ca0c7bc41c 100644 +--- a/drivers/thermal/loongson2_thermal.c ++++ b/drivers/thermal/loongson2_thermal.c +@@ -127,7 +127,7 @@ static int loongson2_thermal_probe(struct platform_device *pdev) + if (!IS_ERR(tzd)) + break; + +- if (PTR_ERR(tzd) != ENODEV) ++ if (PTR_ERR(tzd) != -ENODEV) + continue; + + return dev_err_probe(dev, PTR_ERR(tzd), "failed to register"); +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-display-avoid-stringop-overflow-warnings-for.patch b/queue-6.7/drm-amd-display-avoid-stringop-overflow-warnings-for.patch new file mode 100644 index 00000000000..7ba9a9c19b6 --- /dev/null +++ b/queue-6.7/drm-amd-display-avoid-stringop-overflow-warnings-for.patch @@ -0,0 +1,65 @@ +From 1854210da7375bad90d893b6dc4166811b484d85 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 23:13:36 +0100 +Subject: drm/amd/display: avoid stringop-overflow warnings for + dp_decide_lane_settings() + +From: Arnd Bergmann + +[ Upstream commit c966dc0e9d96dc44423c404a2628236f1200c24e ] + +gcc prints a warning about a possible array overflow for a couple of +callers of dp_decide_lane_settings() after commit 1b56c90018f0 ("Makefile: +Enable -Wstringop-overflow globally"): + +drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c: In function 'dp_perform_fixed_vs_pe_training_sequence_legacy': +drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25: error: 'dp_decide_lane_settings' accessing 4 bytes in a region of size 1 [-Werror=stringop-overflow=] + 426 | dp_decide_lane_settings(lt_settings, dpcd_lane_adjust, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + 427 | lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); + | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25: note: referencing argument 4 of type 'union dpcd_training_lane[4]' + +I'm not entirely sure what caused this, but changing the prototype to expect +a pointer instead of an array avoids the warnings. + +Fixes: 7727e7b60f82 ("drm/amd/display: Improve robustness of FIXED_VS link training at DP1 rates") +Acked-by: Randy Dunlap +Tested-by: Randy Dunlap # build-tested +Signed-off-by: Arnd Bergmann +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c | 2 +- + .../gpu/drm/amd/display/dc/link/protocols/link_dp_training.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +index 90339c2dfd84..5a0b04518956 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +@@ -807,7 +807,7 @@ void dp_decide_lane_settings( + const struct link_training_settings *lt_settings, + const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], + struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX], +- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]) ++ union dpcd_training_lane *dpcd_lane_settings) + { + uint32_t lane; + +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h +index 7d027bac8255..851bd17317a0 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h +@@ -111,7 +111,7 @@ void dp_decide_lane_settings( + const struct link_training_settings *lt_settings, + const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], + struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX], +- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]); ++ union dpcd_training_lane *dpcd_lane_settings); + + enum dc_dp_training_pattern decide_cr_training_pattern( + const struct dc_link_settings *link_settings); +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-display-check-writeback-connectors-in-create.patch b/queue-6.7/drm-amd-display-check-writeback-connectors-in-create.patch new file mode 100644 index 00000000000..ccf8f2aaad1 --- /dev/null +++ b/queue-6.7/drm-amd-display-check-writeback-connectors-in-create.patch @@ -0,0 +1,50 @@ +From eef24a4306587ba5c5a82afc4f371ee99b7fc5f9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 06:25:28 -0700 +Subject: drm/amd/display: Check writeback connectors in + create_validate_stream_for_sink + +From: Alex Hung + +[ Upstream commit dbf5d3d02987faa0eec3710dd687cd912362d7b5 ] + +[WHY & HOW] +This is to check connector type to avoid +unhandled null pointer for writeback connectors. + +Tested-by: Daniel Wheeler +Fixes: 60e034f28600 ("drm/amd/display: Revert "drm/amd/display: Use drm_connector in create_validate_stream_for_sink"") +Signed-off-by: Alex Hung +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index beacda24b4ef..a9bd020b165a 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -6649,6 +6649,9 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, + break; + } + ++ if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) ++ return stream; ++ + dc_result = dc_validate_stream(adev->dm.dc, stream); + if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) + dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); +@@ -9373,7 +9376,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); + connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); +- if (connector && connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) ++ if (connector) + aconnector = to_amdgpu_dm_connector(connector); + + /* TODO This hack should go away */ +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-display-fix-null-pointer-dereference-at-hibe.patch b/queue-6.7/drm-amd-display-fix-null-pointer-dereference-at-hibe.patch new file mode 100644 index 00000000000..acab94ff082 --- /dev/null +++ b/queue-6.7/drm-amd-display-fix-null-pointer-dereference-at-hibe.patch @@ -0,0 +1,47 @@ +From 01f6878f0c94e642eb4e03f493fc468ec010d980 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 18:35:09 -0600 +Subject: drm/amd/display: Fix NULL pointer dereference at hibernate + +From: Mario Limonciello + +[ Upstream commit b719a9c15d52d4f56bdea8241a5d90fd9197ce99 ] + +During hibernate sequence the source context might not have a clk_mgr. +So don't use it to look for DML2 support. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2980 +Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2") +Reviewed-by: Harry Wentland +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index a1f1d1003992..e4bb1e25ee3b 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -4512,7 +4512,7 @@ void dc_resource_state_copy_construct( + struct dml2_context *dml2 = NULL; + + // Need to preserve allocated dml2 context +- if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2) ++ if (src_ctx->clk_mgr && src_ctx->clk_mgr->ctx->dc->debug.using_dml2) + dml2 = dst_ctx->bw_ctx.dml2; + #endif + +@@ -4520,7 +4520,7 @@ void dc_resource_state_copy_construct( + + #ifdef CONFIG_DRM_AMD_DC_FP + // Preserve allocated dml2 context +- if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2) ++ if (src_ctx->clk_mgr && src_ctx->clk_mgr->ctx->dc->debug.using_dml2) + dst_ctx->bw_ctx.dml2 = dml2; + #endif + +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-display-return-drm_connector-from-find_first.patch b/queue-6.7/drm-amd-display-return-drm_connector-from-find_first.patch new file mode 100644 index 00000000000..b2efdf2ffc0 --- /dev/null +++ b/queue-6.7/drm-amd-display-return-drm_connector-from-find_first.patch @@ -0,0 +1,108 @@ +From a03a13b6b1db19244e25caba4cb6d03052d88027 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 06:25:26 -0700 +Subject: drm/amd/display: Return drm_connector from + find_first_crtc_matching_connector + +From: Harry Wentland + +[ Upstream commit 748b091d641638e68330b1b24195eaba9aadf997 ] + +[WHY] +We will be dealing with two types of connector: amdgpu_dm_connector +and drm_writeback_connector. + +[HOW] +We want to find both and then cast to the appriopriate type afterwards. + +Tested-by: Daniel Wheeler +Reviewed-by: Alex Hung +Signed-off-by: Harry Wentland +Signed-off-by: Alex Hung +Signed-off-by: Alex Deucher +Stable-dep-of: dbf5d3d02987 ("drm/amd/display: Check writeback connectors in create_validate_stream_for_sink") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- + 3 files changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index d8c967cee498..5cf919a489a1 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2660,7 +2660,7 @@ static int dm_suspend(void *handle) + return 0; + } + +-struct amdgpu_dm_connector * ++struct drm_connector * + amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, + struct drm_crtc *crtc) + { +@@ -2673,7 +2673,7 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, + crtc_from_state = new_con_state->crtc; + + if (crtc_from_state == crtc) +- return to_amdgpu_dm_connector(connector); ++ return connector; + } + + return NULL; +@@ -9354,6 +9354,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + * update changed items + */ + struct amdgpu_crtc *acrtc = NULL; ++ struct drm_connector *connector = NULL; + struct amdgpu_dm_connector *aconnector = NULL; + struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; + struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; +@@ -9363,7 +9364,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); +- aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); ++ connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); ++ aconnector = to_amdgpu_dm_connector(connector); + + /* TODO This hack should go away */ + if (aconnector && enable) { +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +index 3d480be802cb..3710f4d0f2cb 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +@@ -834,7 +834,7 @@ struct dc_stream_state * + int dm_atomic_get_state(struct drm_atomic_state *state, + struct dm_atomic_state **dm_state); + +-struct amdgpu_dm_connector * ++struct drm_connector * + amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, + struct drm_crtc *crtc); + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +index 9b71643d8a89..602a2ab98abf 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +@@ -1500,14 +1500,16 @@ int pre_validate_dsc(struct drm_atomic_state *state, + int ind = find_crtc_index_in_state_by_stream(state, stream); + + if (ind >= 0) { ++ struct drm_connector *connector; + struct amdgpu_dm_connector *aconnector; + struct drm_connector_state *drm_new_conn_state; + struct dm_connector_state *dm_new_conn_state; + struct dm_crtc_state *dm_old_crtc_state; + +- aconnector = ++ connector = + amdgpu_dm_find_first_crtc_matching_connector(state, + state->crtcs[ind].ptr); ++ aconnector = to_amdgpu_dm_connector(connector); + drm_new_conn_state = + drm_atomic_get_new_connector_state(state, + &aconnector->base); +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-display-use-drm_connector-in-create_stream_f.patch b/queue-6.7/drm-amd-display-use-drm_connector-in-create_stream_f.patch new file mode 100644 index 00000000000..4ce80554fcd --- /dev/null +++ b/queue-6.7/drm-amd-display-use-drm_connector-in-create_stream_f.patch @@ -0,0 +1,211 @@ +From dc2f5ca1e7fd3c09b533b63f05e6007b822388e1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 06:25:27 -0700 +Subject: drm/amd/display: Use drm_connector in create_stream_for_sink + +From: Harry Wentland + +[ Upstream commit 3e094a2875260543ca74838decc0c995d3765096 ] + +[WHAT] +We need to use this function for both amdgpu_dm_connectors +and drm_writeback_connectors. Modify it to operate on +a drm_connector as a common base. + +Tested-by: Daniel Wheeler +Reviewed-by: Alex Hung +Signed-off-by: Harry Wentland +Signed-off-by: Alex Hung +Signed-off-by: Alex Deucher +Stable-dep-of: dbf5d3d02987 ("drm/amd/display: Check writeback connectors in create_validate_stream_for_sink") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 65 +++++++++++-------- + 1 file changed, 37 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 5cf919a489a1..beacda24b4ef 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -5527,6 +5527,7 @@ static void fill_stream_properties_from_drm_display_mode( + && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; + else if (drm_mode_is_420_also(info, mode_in) ++ && aconnector + && aconnector->force_yuv420_output) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; + else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) +@@ -5562,7 +5563,7 @@ static void fill_stream_properties_from_drm_display_mode( + timing_out->hdmi_vic = hv_frame.vic; + } + +- if (is_freesync_video_mode(mode_in, aconnector)) { ++ if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { + timing_out->h_addressable = mode_in->hdisplay; + timing_out->h_total = mode_in->htotal; + timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; +@@ -6039,14 +6040,14 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, + } + + static struct dc_stream_state * +-create_stream_for_sink(struct amdgpu_dm_connector *aconnector, ++create_stream_for_sink(struct drm_connector *connector, + const struct drm_display_mode *drm_mode, + const struct dm_connector_state *dm_state, + const struct dc_stream_state *old_stream, + int requested_bpc) + { ++ struct amdgpu_dm_connector *aconnector = NULL; + struct drm_display_mode *preferred_mode = NULL; +- struct drm_connector *drm_connector; + const struct drm_connector_state *con_state = &dm_state->base; + struct dc_stream_state *stream = NULL; + struct drm_display_mode mode; +@@ -6065,20 +6066,22 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + drm_mode_init(&mode, drm_mode); + memset(&saved_mode, 0, sizeof(saved_mode)); + +- if (aconnector == NULL) { +- DRM_ERROR("aconnector is NULL!\n"); ++ if (connector == NULL) { ++ DRM_ERROR("connector is NULL!\n"); + return stream; + } + +- drm_connector = &aconnector->base; +- +- if (!aconnector->dc_sink) { +- sink = create_fake_sink(aconnector); +- if (!sink) +- return stream; +- } else { +- sink = aconnector->dc_sink; +- dc_sink_retain(sink); ++ if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { ++ aconnector = NULL; ++ aconnector = to_amdgpu_dm_connector(connector); ++ if (!aconnector->dc_sink) { ++ sink = create_fake_sink(aconnector); ++ if (!sink) ++ return stream; ++ } else { ++ sink = aconnector->dc_sink; ++ dc_sink_retain(sink); ++ } + } + + stream = dc_create_stream_for_sink(sink); +@@ -6088,12 +6091,13 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + goto finish; + } + ++ /* We leave this NULL for writeback connectors */ + stream->dm_stream_context = aconnector; + + stream->timing.flags.LTE_340MCSC_SCRAMBLE = +- drm_connector->display_info.hdmi.scdc.scrambling.low_rates; ++ connector->display_info.hdmi.scdc.scrambling.low_rates; + +- list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { ++ list_for_each_entry(preferred_mode, &connector->modes, head) { + /* Search for preferred mode */ + if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { + native_mode_found = true; +@@ -6102,7 +6106,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + } + if (!native_mode_found) + preferred_mode = list_first_entry_or_null( +- &aconnector->base.modes, ++ &connector->modes, + struct drm_display_mode, + head); + +@@ -6116,7 +6120,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + * and the modelist may not be filled in time. + */ + DRM_DEBUG_DRIVER("No preferred mode found\n"); +- } else { ++ } else if (aconnector) { + recalculate_timing = is_freesync_video_mode(&mode, aconnector); + if (recalculate_timing) { + freesync_mode = get_highest_refresh_rate_mode(aconnector, false); +@@ -6139,13 +6143,17 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + */ + if (!scale || mode_refresh != preferred_refresh) + fill_stream_properties_from_drm_display_mode( +- stream, &mode, &aconnector->base, con_state, NULL, ++ stream, &mode, connector, con_state, NULL, + requested_bpc); + else + fill_stream_properties_from_drm_display_mode( +- stream, &mode, &aconnector->base, con_state, old_stream, ++ stream, &mode, connector, con_state, old_stream, + requested_bpc); + ++ /* The rest isn't needed for writeback connectors */ ++ if (!aconnector) ++ goto finish; ++ + if (aconnector->timing_changed) { + drm_dbg(aconnector->base.dev, + "overriding timing for automated test, bpc %d, changing to %d\n", +@@ -6163,7 +6171,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + + fill_audio_info( + &stream->audio_info, +- drm_connector, ++ connector, + sink); + + update_stream_signal(stream, sink); +@@ -6633,7 +6641,7 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, + enum dc_status dc_result = DC_OK; + + do { +- stream = create_stream_for_sink(aconnector, drm_mode, ++ stream = create_stream_for_sink(connector, drm_mode, + dm_state, old_stream, + requested_bpc); + if (stream == NULL) { +@@ -9365,15 +9373,16 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); + connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); +- aconnector = to_amdgpu_dm_connector(connector); ++ if (connector && connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) ++ aconnector = to_amdgpu_dm_connector(connector); + + /* TODO This hack should go away */ +- if (aconnector && enable) { ++ if (connector && enable) { + /* Make sure fake sink is created in plug-in scenario */ + drm_new_conn_state = drm_atomic_get_new_connector_state(state, +- &aconnector->base); ++ connector); + drm_old_conn_state = drm_atomic_get_old_connector_state(state, +- &aconnector->base); ++ connector); + + if (IS_ERR(drm_new_conn_state)) { + ret = PTR_ERR_OR_ZERO(drm_new_conn_state); +@@ -9520,7 +9529,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + * added MST connectors not found in existing crtc_state in the chained mode + * TODO: need to dig out the root cause of that + */ +- if (!aconnector) ++ if (!connector) + goto skip_modeset; + + if (modereset_required(new_crtc_state)) +@@ -9563,7 +9572,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, + * We want to do dc stream updates that do not require a + * full modeset below. + */ +- if (!(enable && aconnector && new_crtc_state->active)) ++ if (!(enable && connector && new_crtc_state->active)) + return 0; + /* + * Given above conditions, the dc state cannot be NULL because: +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch b/queue-6.7/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch new file mode 100644 index 00000000000..2576512db15 --- /dev/null +++ b/queue-6.7/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch @@ -0,0 +1,198 @@ +From d705649444bb1edc55999414de237858552fb06b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 00:59:38 +0800 +Subject: drm/amd/pm: fix a double-free in amdgpu_parse_extended_power_table + +From: Zhipeng Lu + +[ Upstream commit a6582701178a47c4d0cb2188c965c59c0c0647c8 ] + +The amdgpu_free_extended_power_table is called in every error-handling +paths of amdgpu_parse_extended_power_table. However, after the following +call chain of returning: + +amdgpu_parse_extended_power_table + |-> kv_dpm_init / si_dpm_init + (the only two caller of amdgpu_parse_extended_power_table) + |-> kv_dpm_sw_init / si_dpm_sw_init + (the only caller of kv_dpm_init / si_dpm_init, accordingly) + |-> kv_dpm_fini / si_dpm_fini + (goto dpm_failed in xx_dpm_sw_init) + |-> amdgpu_free_extended_power_table + +As above, the amdgpu_free_extended_power_table is called twice in this +returning chain and thus a double-free is triggered. Similarily, the +last kfree in amdgpu_parse_extended_power_table also cause a double free +with amdgpu_free_extended_power_table in kv_dpm_fini. + +Fixes: 84176663e70d ("drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 52 +++++-------------- + 1 file changed, 13 insertions(+), 39 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +index 81fb4e5dd804..60377747bab4 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +@@ -272,10 +272,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -283,10 +281,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -294,10 +290,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -305,10 +299,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { + ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = +@@ -339,10 +331,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + kcalloc(psl->ucNumEntries, + sizeof(struct amdgpu_phase_shedding_limits_entry), + GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) + return -ENOMEM; +- } + + entry = &psl->entries[0]; + for (i = 0; i < psl->ucNumEntries; i++) { +@@ -383,10 +373,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ATOM_PPLIB_CAC_Leakage_Record *entry; + u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table); + adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) + return -ENOMEM; +- } + entry = &cac_table->entries[0]; + for (i = 0; i < cac_table->ucNumEntries; i++) { + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { +@@ -438,10 +426,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_vce_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -493,10 +479,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -525,10 +509,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -548,10 +530,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(ext_hdr->usPPMTableOffset)); + adev->pm.dpm.dyn_state.ppm_table = + kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.ppm_table) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.ppm_table) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; + adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = + le16_to_cpu(ppm->usCpuCoreNumber); +@@ -583,10 +563,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -606,10 +584,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ATOM_PowerTune_Table *pt; + adev->pm.dpm.dyn_state.cac_tdp_table = + kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.cac_tdp_table) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.cac_tdp_table) + return -ENOMEM; +- } + if (rev > 0) { + ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *) + (mode_info->atom_context->bios + data_offset + +@@ -645,10 +621,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ret = amdgpu_parse_clk_voltage_dep_table( + &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, + dep_table); +- if (ret) { +- kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); ++ if (ret) + return ret; +- } + } + } + +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch b/queue-6.7/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch new file mode 100644 index 00000000000..14f04a138d0 --- /dev/null +++ b/queue-6.7/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch @@ -0,0 +1,45 @@ +From 3f8f12d451ce5021d07f0e3478e17a68ba39f1cf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 23:24:11 +0800 +Subject: drm/amd/pm: fix a double-free in si_dpm_init + +From: Zhipeng Lu + +[ Upstream commit ac16667237a82e2597e329eb9bc520d1cf9dff30 ] + +When the allocation of +adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries fails, +amdgpu_free_extended_power_table is called to free some fields of adev. +However, when the control flow returns to si_dpm_sw_init, it goes to +label dpm_failed and calls si_dpm_fini, which calls +amdgpu_free_extended_power_table again and free those fields again. Thus +a double-free is triggered. + +Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +index fc8e4ac6c8e7..df4f20293c16 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +@@ -7379,10 +7379,9 @@ static int si_dpm_init(struct amdgpu_device *adev) + kcalloc(4, + sizeof(struct amdgpu_clock_voltage_dependency_entry), + GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) + return -ENOMEM; +- } ++ + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; +-- +2.43.0 + diff --git a/queue-6.7/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch b/queue-6.7/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch new file mode 100644 index 00000000000..6fd1e2910a4 --- /dev/null +++ b/queue-6.7/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch @@ -0,0 +1,53 @@ +From c1e8c9bd09849d9ad08fbff7527c595fba9f4eaa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 16:22:47 +0800 +Subject: drm/amd/pm/smu7: fix a memleak in smu7_hwmgr_backend_init + +From: Zhipeng Lu + +[ Upstream commit 2f3be3ca779b11c332441b10e00443a2510f4d7b ] + +The hwmgr->backend, (i.e. data) allocated by kzalloc is not freed in +the error-handling paths of smu7_get_evv_voltages and +smu7_update_edc_leakage_table. However, it did be freed in the +error-handling of phm_initializa_dynamic_state_adjustment_rule_settings, +by smu7_hwmgr_backend_fini. So the lack of free in smu7_get_evv_voltages +and smu7_update_edc_leakage_table is considered a memleak in this patch. + +Fixes: 599a7e9fe1b6 ("drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.") +Fixes: 8f0804c6b7d0 ("drm/amd/pm: add edc leakage controller setting") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +index 11372fcc59c8..b1a8799e2dee 100644 +--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +@@ -2974,6 +2974,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + result = smu7_get_evv_voltages(hwmgr); + if (result) { + pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); ++ kfree(hwmgr->backend); ++ hwmgr->backend = NULL; + return -EINVAL; + } + } else { +@@ -3019,8 +3021,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + } + + result = smu7_update_edc_leakage_table(hwmgr); +- if (result) ++ if (result) { ++ smu7_hwmgr_backend_fini(hwmgr); + return result; ++ } + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.7/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch b/queue-6.7/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch new file mode 100644 index 00000000000..bf290146e29 --- /dev/null +++ b/queue-6.7/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch @@ -0,0 +1,48 @@ +From bc4206fcb3f1984d086c80a181c24719c0cb5d52 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 17:26:29 -0500 +Subject: drm/amdgpu/debugfs: fix error code when smc register accessors are + NULL +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +[ Upstream commit afe58346d5d3887b3e49ff623d2f2e471f232a8d ] + +Should be -EOPNOTSUPP. + +Fixes: 5104fdf50d32 ("drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL") +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +index 0e61ebdb3f3e..8d4a3ff65c18 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +@@ -755,7 +755,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, + int r; + + if (!adev->smc_rreg) +- return -EPERM; ++ return -EOPNOTSUPP; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; +@@ -814,7 +814,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * + int r; + + if (!adev->smc_wreg) +- return -EPERM; ++ return -EOPNOTSUPP; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; +-- +2.43.0 + diff --git a/queue-6.7/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch b/queue-6.7/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch new file mode 100644 index 00000000000..b6a7e0d93ec --- /dev/null +++ b/queue-6.7/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch @@ -0,0 +1,81 @@ +From 84055fe2c5190f85b96bd4fddccd13f5077900c1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Dec 2023 07:16:23 +0530 +Subject: drm/amdkfd: Confirm list is non-empty before utilizing + list_first_entry in kfd_topology.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Srinivasan Shanmugam + +[ Upstream commit 499839eca34ad62d43025ec0b46b80e77065f6d8 ] + +Before using list_first_entry, make sure to check that list is not +empty, if list is empty return -ENODATA. + +Fixes the below: +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1347 kfd_create_indirect_link_prop() warn: can 'gpu_link' even be NULL? +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1428 kfd_add_peer_prop() warn: can 'iolink1' even be NULL? +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1433 kfd_add_peer_prop() warn: can 'iolink2' even be NULL? + +Fixes: 0f28cca87e9a ("drm/amdkfd: Extend KFD device topology to surface peer-to-peer links") +Cc: Felix Kuehling +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Srinivasan Shanmugam +Suggested-by: Felix Kuehling +Suggested-by: Lijo Lazar +Reviewed-by: Felix Kuehling +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +index 057284bf50bb..58d775a0668d 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +@@ -1342,10 +1342,11 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g + num_cpu++; + } + ++ if (list_empty(&kdev->io_link_props)) ++ return -ENODATA; ++ + gpu_link = list_first_entry(&kdev->io_link_props, +- struct kfd_iolink_properties, list); +- if (!gpu_link) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); + + for (i = 0; i < num_cpu; i++) { + /* CPU <--> GPU */ +@@ -1423,15 +1424,17 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, + peer->gpu->adev)) + return ret; + ++ if (list_empty(&kdev->io_link_props)) ++ return -ENODATA; ++ + iolink1 = list_first_entry(&kdev->io_link_props, +- struct kfd_iolink_properties, list); +- if (!iolink1) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); ++ ++ if (list_empty(&peer->io_link_props)) ++ return -ENODATA; + + iolink2 = list_first_entry(&peer->io_link_props, +- struct kfd_iolink_properties, list); +- if (!iolink2) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); + + props = kfd_alloc_struct(props); + if (!props) +-- +2.43.0 + diff --git a/queue-6.7/drm-amdkfd-fix-type-of-dbg_flags-in-struct-kfd_proce.patch b/queue-6.7/drm-amdkfd-fix-type-of-dbg_flags-in-struct-kfd_proce.patch new file mode 100644 index 00000000000..dea25f56c56 --- /dev/null +++ b/queue-6.7/drm-amdkfd-fix-type-of-dbg_flags-in-struct-kfd_proce.patch @@ -0,0 +1,48 @@ +From 5d0d1e45a0aef72e17efc7d113c05de43c89d6f1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Dec 2023 08:10:42 +0530 +Subject: drm/amdkfd: Fix type of 'dbg_flags' in 'struct kfd_process' +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Srinivasan Shanmugam + +[ Upstream commit 217e85f97031791fb48a2d374c7bdcf439365b21 ] + +dbg_flags looks to be defined with incorrect data type; to process +multiple debug flag options, and hence defined dbg_flags as u32. + +Fixes the below: + +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.c:117 pm_map_process_aldebaran() warn: maybe use && instead of & + +Fixes: 0de4ec9a0353 ("drm/amdgpu: prepare map process for multi-process debug devices") +Suggested-by: Lijo Lazar +Cc: Felix Kuehling +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Srinivasan Shanmugam +Reviewed-by: Felix Kuehling +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +index 4c8e278a0d0c..28162bfbe1b3 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +@@ -971,7 +971,7 @@ struct kfd_process { + struct work_struct debug_event_workarea; + + /* Tracks debug per-vmid request for debug flags */ +- bool dbg_flags; ++ u32 dbg_flags; + + atomic_t poison; + /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ +-- +2.43.0 + diff --git a/queue-6.7/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch b/queue-6.7/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch new file mode 100644 index 00000000000..134547756d2 --- /dev/null +++ b/queue-6.7/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch @@ -0,0 +1,38 @@ +From 43e058e3096f45be6b336844988eef7a7730eebc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 3 Nov 2023 15:14:05 +0200 +Subject: drm/bridge: cdns-mhdp8546: Fix use of uninitialized variable + +From: Tomi Valkeinen + +[ Upstream commit 155d6fb61270dd297f128731cd155080deee8f3a ] + +'ret' could be uninitialized at the end of the function, although it's +not clear if that can happen in practice. + +Fixes: 6a3608eae6d3 ("drm: bridge: cdns-mhdp8546: Enable HDCP") +Acked-by: Maxime Ripard +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20231103-uninit-fixes-v2-3-c22b2444f5f5@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c +index 946212a95598..5e3b8edcf794 100644 +--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c +@@ -403,7 +403,8 @@ static int _cdns_mhdp_hdcp_disable(struct cdns_mhdp_device *mhdp) + + static int _cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type) + { +- int ret, tries = 3; ++ int ret = -EINVAL; ++ int tries = 3; + u32 i; + + for (i = 0; i < tries; i++) { +-- +2.43.0 + diff --git a/queue-6.7/drm-bridge-fix-typo-in-post_disable-description.patch b/queue-6.7/drm-bridge-fix-typo-in-post_disable-description.patch new file mode 100644 index 00000000000..dd592b7766c --- /dev/null +++ b/queue-6.7/drm-bridge-fix-typo-in-post_disable-description.patch @@ -0,0 +1,36 @@ +From bef36edbd575b329efde51f9ddc0602f95fa1ab1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 10:42:30 +0100 +Subject: drm/bridge: Fix typo in post_disable() description + +From: Dario Binacchi + +[ Upstream commit 288b039db225676e0c520c981a1b5a2562d893a3 ] + +s/singals/signals/ + +Fixes: 199e4e967af4 ("drm: Extract drm_bridge.h") +Signed-off-by: Dario Binacchi +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20231124094253.658064-1-dario.binacchi@amarulasolutions.com +Signed-off-by: Sasha Levin +--- + include/drm/drm_bridge.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h +index cfb7dcdb66c4..9ef461aa9b9e 100644 +--- a/include/drm/drm_bridge.h ++++ b/include/drm/drm_bridge.h +@@ -194,7 +194,7 @@ struct drm_bridge_funcs { + * or &drm_encoder_helper_funcs.dpms hook. + * + * The bridge must assume that the display pipe (i.e. clocks and timing +- * singals) feeding it is no longer running when this callback is ++ * signals) feeding it is no longer running when this callback is + * called. + * + * The @post_disable callback is optional. +-- +2.43.0 + diff --git a/queue-6.7/drm-bridge-imx93-mipi-dsi-fix-a-couple-of-building-w.patch b/queue-6.7/drm-bridge-imx93-mipi-dsi-fix-a-couple-of-building-w.patch new file mode 100644 index 00000000000..512f9e62418 --- /dev/null +++ b/queue-6.7/drm-bridge-imx93-mipi-dsi-fix-a-couple-of-building-w.patch @@ -0,0 +1,43 @@ +From 6f00cc9c95f6953a4a4e5d4709cb441102f9f5a9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Nov 2023 13:18:07 +0800 +Subject: drm/bridge: imx93-mipi-dsi: Fix a couple of building warnings + +From: Liu Ying + +[ Upstream commit 325b71e820b67569048c621227266783442b75ed ] + +Fix a couple of building warnings on used uninitialized 'best_m' and +'best_n' local variables by initializing 'best_m' to zero and 'best_n' +to UINT_MAX. This makes compiler happy only. No functional change. + +Fixes: ce62f8ea7e3f ("drm/bridge: imx: Add i.MX93 MIPI DSI support") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202311151746.f7u7dzbZ-lkp@intel.com/ +Signed-off-by: Liu Ying +Reviewed-by: Robert Foss +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20231123051807.3818342-1-victor.liu@nxp.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c +index 3ff30ce80c5b..2347f8dd632f 100644 +--- a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c ++++ b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c +@@ -226,8 +226,8 @@ dphy_pll_get_configure_from_opts(struct imx93_dsi *dsi, + unsigned long fout; + unsigned long best_fout = 0; + unsigned int fvco_div; +- unsigned int min_n, max_n, n, best_n; +- unsigned long m, best_m; ++ unsigned int min_n, max_n, n, best_n = UINT_MAX; ++ unsigned long m, best_m = 0; + unsigned long min_delta = ULONG_MAX; + unsigned long delta; + u64 tmp; +-- +2.43.0 + diff --git a/queue-6.7/drm-bridge-tc358767-fix-return-value-on-error-case.patch b/queue-6.7/drm-bridge-tc358767-fix-return-value-on-error-case.patch new file mode 100644 index 00000000000..f4131c7019b --- /dev/null +++ b/queue-6.7/drm-bridge-tc358767-fix-return-value-on-error-case.patch @@ -0,0 +1,39 @@ +From 6024a80e9161b2e16aa2e95f58c48782d5dfb32e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 3 Nov 2023 15:14:06 +0200 +Subject: drm/bridge: tc358767: Fix return value on error case + +From: Tomi Valkeinen + +[ Upstream commit 32bd29b619638256c5b75fb021d6d9f12fc4a984 ] + +If the hpd_pin is invalid, the driver returns 'ret'. But 'ret' contains +0, instead of an error value. + +Return -EINVAL instead. + +Fixes: f25ee5017e4f ("drm/bridge: tc358767: add IRQ and HPD support") +Acked-by: Maxime Ripard +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20231103-uninit-fixes-v2-4-c22b2444f5f5@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/tc358767.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c +index ef2e373606ba..615cc8f950d7 100644 +--- a/drivers/gpu/drm/bridge/tc358767.c ++++ b/drivers/gpu/drm/bridge/tc358767.c +@@ -2273,7 +2273,7 @@ static int tc_probe(struct i2c_client *client) + } else { + if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { + dev_err(dev, "failed to parse HPD number\n"); +- return ret; ++ return -EINVAL; + } + } + +-- +2.43.0 + diff --git a/queue-6.7/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch b/queue-6.7/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch new file mode 100644 index 00000000000..9875c14871c --- /dev/null +++ b/queue-6.7/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch @@ -0,0 +1,52 @@ +From 7d6414f5941a08af5b22179d78ee24cbcd5e6aa3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 2 Nov 2023 17:56:42 +0100 +Subject: drm/bridge: tpd12s015: Drop buggy __exit annotation for remove + function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit ce3e112e7ae854249d8755906acc5f27e1542114 ] + +With tpd12s015_remove() marked with __exit this function is discarded +when the driver is compiled as a built-in. The result is that when the +driver unbinds there is no cleanup done which results in resource +leakage or worse. + +Fixes: cff5e6f7e83f ("drm/bridge: Add driver for the TI TPD12S015 HDMI level shifter") +Signed-off-by: Uwe Kleine-König +Signed-off-by: Thomas Zimmermann +Link: https://patchwork.freedesktop.org/patch/msgid/20231102165640.3307820-19-u.kleine-koenig@pengutronix.de +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/ti-tpd12s015.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c +index e0e015243a60..b588fea12502 100644 +--- a/drivers/gpu/drm/bridge/ti-tpd12s015.c ++++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c +@@ -179,7 +179,7 @@ static int tpd12s015_probe(struct platform_device *pdev) + return 0; + } + +-static int __exit tpd12s015_remove(struct platform_device *pdev) ++static int tpd12s015_remove(struct platform_device *pdev) + { + struct tpd12s015_device *tpd = platform_get_drvdata(pdev); + +@@ -197,7 +197,7 @@ MODULE_DEVICE_TABLE(of, tpd12s015_of_match); + + static struct platform_driver tpd12s015_driver = { + .probe = tpd12s015_probe, +- .remove = __exit_p(tpd12s015_remove), ++ .remove = tpd12s015_remove, + .driver = { + .name = "tpd12s015", + .of_match_table = tpd12s015_of_match, +-- +2.43.0 + diff --git a/queue-6.7/drm-dp_mst-fix-fractional-dsc-bpp-handling.patch b/queue-6.7/drm-dp_mst-fix-fractional-dsc-bpp-handling.patch new file mode 100644 index 00000000000..13045cbd862 --- /dev/null +++ b/queue-6.7/drm-dp_mst-fix-fractional-dsc-bpp-handling.patch @@ -0,0 +1,203 @@ +From cb7007d42f829d4631a8e6f3d50583a92f5bddb8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 24 Oct 2023 04:08:57 +0300 +Subject: drm/dp_mst: Fix fractional DSC bpp handling +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit 7707dd6022593f3edd8e182e7935870cf326f874 ] + +The current code does '(bpp << 4) / 16' in the MST PBN +calculation, but that is just the same as 'bpp' so the +DSC codepath achieves absolutely nothing. Fix it up so that +the fractional part of the bpp value is actually used instead +of truncated away. 64*1006 has enough zero lsbs that we can +just shift that down in the dividend and thus still manage +to stick to a 32bit divisor. + +And while touching this, let's just make the whole thing more +straightforward by making the passed in bpp value .4 binary +fixed point always, instead of having to pass in different +things based on whether DSC is enabled or not. + +v2: +- Fix DSC kunit test cases. + +Cc: Manasi Navare +Cc: Lyude Paul +Cc: Harry Wentland +Cc: David Francis +Cc: Mikita Lipski +Cc: Alex Deucher +Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes") +Signed-off-by: Ville Syrjälä +[Imre: Fix kunit test cases] +Acked-by: Maxime Ripard +Reviewed-by: Lyude Paul +Acked-by: Harry Wentland +Signed-off-by: Imre Deak +Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-3-imre.deak@intel.com +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- + .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- + drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++-------------- + drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--- + drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +-- + .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++--- + include/drm/display/drm_dp_mst_helper.h | 2 +- + 7 files changed, 14 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 4e82ee4d74ac..d8c967cee498 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -6928,7 +6928,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, + max_bpc); + bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; + clock = adjusted_mode->clock; +- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); ++ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); + } + + dm_new_connector_state->vcpi_slots = +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +index 11da0eebee6c..9b71643d8a89 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +@@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( + } else { + /* check if mode could be supported within full_pbn */ + bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; +- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); ++ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4); + if (pbn > full_pbn) + return DC_FAIL_BANDWIDTH_VALIDATE; + } +diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c +index 0e0d0e76de06..772b00ebd57b 100644 +--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c ++++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c +@@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status); + + /** + * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode. +- * @clock: dot clock for the mode +- * @bpp: bpp for the mode. +- * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel ++ * @clock: dot clock ++ * @bpp: bpp as .4 binary fixed point + * + * This uses the formula in the spec to calculate the PBN value for a mode. + */ +-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) ++int drm_dp_calc_pbn_mode(int clock, int bpp) + { + /* + * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 +@@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) + * peak_kbps *= (1006/1000) + * peak_kbps *= (64/54) + * peak_kbps *= 8 convert to bytes +- * +- * If the bpp is in units of 1/16, further divide by 16. Put this +- * factor in the numerator rather than the denominator to avoid +- * integer overflow + */ +- +- if (dsc) +- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), +- 8 * 54 * 1000 * 1000); +- +- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006), +- 8 * 54 * 1000 * 1000); ++ return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4), ++ 1000 * 8 * 54 * 1000); + } + EXPORT_SYMBOL(drm_dp_calc_pbn_mode); + +diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c +index aa1061262613..03ac2817664e 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c +@@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, + continue; + + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, +- dsc ? bpp << 4 : bpp, +- dsc); ++ bpp << 4); + + slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, + connector->port, +@@ -979,7 +978,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, + return ret; + + if (mode_rate > max_rate || mode->clock > max_dotclk || +- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) { ++ drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) { + *status = MODE_CLOCK_HIGH; + return 0; + } +diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c +index 118807e38422..d093549f6eb7 100644 +--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c ++++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c +@@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, + const int clock = crtc_state->adjusted_mode.clock; + + asyh->or.bpc = connector->display_info.bpc; +- asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, +- false); ++ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4); + } + + mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr); +diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c +index 545beea33e8c..e3c818dfc0e6 100644 +--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c ++++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c +@@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases + .clock = 332880, + .bpp = 24, + .dsc = true, +- .expected = 50 ++ .expected = 1191 + }, + { + .clock = 324540, + .bpp = 24, + .dsc = true, +- .expected = 49 ++ .expected = 1161 + }, + }; + +@@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test) + { + const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value; + +- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc), ++ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4), + params->expected); + } + +diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h +index 4429d3b1745b..655862b3d2a4 100644 +--- a/include/drm/display/drm_dp_mst_helper.h ++++ b/include/drm/display/drm_dp_mst_helper.h +@@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, + int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, + int link_rate, int link_lane_count); + +-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); ++int drm_dp_calc_pbn_mode(int clock, int bpp); + + void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap); + +-- +2.43.0 + diff --git a/queue-6.7/drm-drv-propagate-errors-from-drm_modeset_register_a.patch b/queue-6.7/drm-drv-propagate-errors-from-drm_modeset_register_a.patch new file mode 100644 index 00000000000..ac8e4dca261 --- /dev/null +++ b/queue-6.7/drm-drv-propagate-errors-from-drm_modeset_register_a.patch @@ -0,0 +1,54 @@ +From 0f78cbae33cd11f0cc04fe367b3cc2636916458a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 01:55:52 +0300 +Subject: drm/drv: propagate errors from drm_modeset_register_all() + +From: Dmitry Baryshkov + +[ Upstream commit 5f8dec200923a76dc57187965fd59c1136f5d085 ] + +In case the drm_modeset_register_all() function fails, its error code +will be ignored. Instead make the drm_dev_register() bail out in case of +such an error. + +Fixes: 79190ea2658a ("drm: Add callbacks for late registering") +Reviewed-by: Neil Armstrong +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20231202225552.1283638-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_drv.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c +index 535f16e7882e..3c835c99daad 100644 +--- a/drivers/gpu/drm/drm_drv.c ++++ b/drivers/gpu/drm/drm_drv.c +@@ -949,8 +949,11 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) + goto err_minors; + } + +- if (drm_core_check_feature(dev, DRIVER_MODESET)) +- drm_modeset_register_all(dev); ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) { ++ ret = drm_modeset_register_all(dev); ++ if (ret) ++ goto err_unload; ++ } + + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", + driver->name, driver->major, driver->minor, +@@ -960,6 +963,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) + + goto out_unlock; + ++err_unload: ++ if (dev->driver->unload) ++ dev->driver->unload(dev); + err_minors: + remove_compat_control_link(dev); + drm_minor_unregister(dev, DRM_MINOR_ACCEL); +-- +2.43.0 + diff --git a/queue-6.7/drm-i915-display-move-releasing-gem-object-away-from.patch b/queue-6.7/drm-i915-display-move-releasing-gem-object-away-from.patch new file mode 100644 index 00000000000..2d8150a8f7a --- /dev/null +++ b/queue-6.7/drm-i915-display-move-releasing-gem-object-away-from.patch @@ -0,0 +1,54 @@ +From 4df8d65fcab6f4f044f8841ac095f203d2ef472a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 Oct 2023 10:21:57 +0300 +Subject: drm/i915/display: Move releasing gem object away from fb tracking +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jouni Högander + +[ Upstream commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 ] + +As a preparation for Xe we want to remove all i915_gem_object details away +from frontbuffer tacking code. Due to this move releasing gem object +reference to i915_gem_object_set_frontbuffer. + +Signed-off-by: Jouni Högander +Reviewed-by: Juha-Pekka Heikkila +Link: https://patchwork.freedesktop.org/patch/msgid/20231012072158.4115795-2-jouni.hogander@intel.com +Stable-dep-of: 560ea72c76eb ("drm/i915/dp_mst: Fix race between connector registration and setup") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_frontbuffer.c | 2 -- + drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h | 1 + + 2 files changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c +index ec46716b2f49..2ea37c0414a9 100644 +--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c ++++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c +@@ -265,8 +265,6 @@ static void frontbuffer_release(struct kref *ref) + spin_unlock(&intel_bo_to_i915(obj)->display.fb_tracking.lock); + + i915_active_fini(&front->write); +- +- i915_gem_object_put(obj); + kfree_rcu(front, rcu); + } + +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h b/drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h +index e5e870b6f186..9fbf14867a2a 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h ++++ b/drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h +@@ -89,6 +89,7 @@ i915_gem_object_set_frontbuffer(struct drm_i915_gem_object *obj, + + if (!front) { + RCU_INIT_POINTER(obj->frontbuffer, NULL); ++ drm_gem_object_put(intel_bo_to_drm_bo(obj)); + } else if (rcu_access_pointer(obj->frontbuffer)) { + cur = rcu_dereference_protected(obj->frontbuffer, true); + kref_get(&cur->ref); +-- +2.43.0 + diff --git a/queue-6.7/drm-imx-lcdc-fix-double-free-of-driver-data.patch b/queue-6.7/drm-imx-lcdc-fix-double-free-of-driver-data.patch new file mode 100644 index 00000000000..9359a29745b --- /dev/null +++ b/queue-6.7/drm-imx-lcdc-fix-double-free-of-driver-data.patch @@ -0,0 +1,58 @@ +From 7b5c925faf1a57ef8498ed105c4c9cc7c4e668fa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jul 2023 11:27:31 +0200 +Subject: drm/imx/lcdc: Fix double-free of driver data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit ff3670877e7c73d06c2a835d9abb62efcae0145c ] + +The struct imx_lcdc driver data is allocated using devm_drm_dev_alloc() +so it must not be explicitly kfree()d. + +Also drm_kms_helper_poll_fini() should not be called as there is no +matching drm_kms_helper_poll_init(). So drop the release function +completely. + +Fixes: c87e859cdeb5 ("drm/imx/lcdc: Implement DRM driver for imx25") +Signed-off-by: Uwe Kleine-König +Reviewed-by: Philipp Zabel +Signed-off-by: Philipp Zabel +Link: https://patchwork.freedesktop.org/patch/msgid/20230706092731.2630232-1-u.kleine-koenig@pengutronix.de +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/imx/lcdc/imx-lcdc.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c b/drivers/gpu/drm/imx/lcdc/imx-lcdc.c +index 22b65f4a0e30..4beb3b4bd694 100644 +--- a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c ++++ b/drivers/gpu/drm/imx/lcdc/imx-lcdc.c +@@ -342,21 +342,12 @@ static const struct drm_mode_config_helper_funcs imx_lcdc_mode_config_helpers = + .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, + }; + +-static void imx_lcdc_release(struct drm_device *drm) +-{ +- struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(drm); +- +- drm_kms_helper_poll_fini(drm); +- kfree(lcdc); +-} +- + DEFINE_DRM_GEM_DMA_FOPS(imx_lcdc_drm_fops); + + static struct drm_driver imx_lcdc_drm_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &imx_lcdc_drm_fops, + DRM_GEM_DMA_DRIVER_OPS_VMAP, +- .release = imx_lcdc_release, + .name = "imx-lcdc", + .desc = "i.MX LCDC driver", + .date = "20200716", +-- +2.43.0 + diff --git a/queue-6.7/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch b/queue-6.7/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch new file mode 100644 index 00000000000..0de2b23e670 --- /dev/null +++ b/queue-6.7/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch @@ -0,0 +1,48 @@ +From 5537d2f89beddebc647f420d4a46f30c1025e5d1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Nov 2023 09:29:27 -0500 +Subject: drm/mediatek: dp: Add phy_mtk_dp module as pre-dependency +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nícolas F. R. A. Prado + +[ Upstream commit c8048dd0b07df68724805254b9e994d99e9a7af4 ] + +The mtk_dp driver registers a phy device which is handled by the +phy_mtk_dp driver and assumes that the phy probe will complete +synchronously, proceeding to make use of functionality exposed by that +driver right away. This assumption however is false when the phy driver +is built as a module, causing the mtk_dp driver to fail probe in this +case. + +Add the phy_mtk_dp module as a pre-dependency to the mtk_dp module to +ensure the phy module has been loaded before the dp, so that the phy +probe happens synchrounously and the mtk_dp driver can probe +successfully even with the phy driver built as a module. + +Suggested-by: AngeloGioacchino Del Regno +Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Guillaume Ranquet +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231121142938.460846-1-nfraprado@collabora.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_dp.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c +index e4c16ba9902d..2136a596efa1 100644 +--- a/drivers/gpu/drm/mediatek/mtk_dp.c ++++ b/drivers/gpu/drm/mediatek/mtk_dp.c +@@ -2818,3 +2818,4 @@ MODULE_AUTHOR("Markus Schneider-Pargmann "); + MODULE_AUTHOR("Bo-Chen Chen "); + MODULE_DESCRIPTION("MediaTek DisplayPort Driver"); + MODULE_LICENSE("GPL"); ++MODULE_SOFTDEP("pre: phy_mtk_dp"); +-- +2.43.0 + diff --git a/queue-6.7/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch b/queue-6.7/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch new file mode 100644 index 00000000000..2e59119560d --- /dev/null +++ b/queue-6.7/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch @@ -0,0 +1,41 @@ +From 73d903c6e9ad69578aef98fba1a00d99ad2a46c5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 13:58:46 +0800 +Subject: drm/mediatek: Fix underrun in VDO1 when switches off the layer + +From: Hsiao Chien Sung + +[ Upstream commit 73b5ab27ab2ee616f2709dc212c2b0007894a12e ] + +Do not reset Merge while using CMDQ because reset API doesn't +wait for frame done event as CMDQ does and could lead to +underrun when the layer is switching off. + +Fixes: aaf94f7c3ae6 ("drm/mediatek: Add display merge async reset control") + +Reviewed-by: CK Hu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Hsiao Chien Sung +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-23-shawn.sung@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c +index e525a6b9e5b0..22f768d923d5 100644 +--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c ++++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c +@@ -103,7 +103,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CTRL); + +- if (priv->async_clk) ++ if (!cmdq_pkt && priv->async_clk) + reset_control_reset(priv->reset_ctl); + } + +-- +2.43.0 + diff --git a/queue-6.7/drm-mediatek-remove-the-redundant-driver-data-for-dp.patch b/queue-6.7/drm-mediatek-remove-the-redundant-driver-data-for-dp.patch new file mode 100644 index 00000000000..307fa0192e4 --- /dev/null +++ b/queue-6.7/drm-mediatek-remove-the-redundant-driver-data-for-dp.patch @@ -0,0 +1,62 @@ +From 436fc92fce9e20298357e7e5e95cc806f7a937e3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 13:58:45 +0800 +Subject: drm/mediatek: Remove the redundant driver data for DPI + +From: Hsiao Chien Sung + +[ Upstream commit 8ac6935e5689a491f0bec78fec732722b3dad094 ] + +DPI input is in 1T2P mode on both MT8195 and MT8188. +Remove the redundant driver data to align the settings, or +the screen will glitch. + +Fixes: 2847cd7e6403 ("drm/mediatek: Add mt8188 dpi compatibles and platform data") + +Reviewed-by: CK Hu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Hsiao Chien Sung +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-22-shawn.sung@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_dpi.c | 16 +--------------- + 1 file changed, 1 insertion(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c +index 4e3d9f7b4d8c..beb7d9d08e97 100644 +--- a/drivers/gpu/drm/mediatek/mtk_dpi.c ++++ b/drivers/gpu/drm/mediatek/mtk_dpi.c +@@ -966,20 +966,6 @@ static const struct mtk_dpi_conf mt8186_conf = { + .csc_enable_bit = CSC_ENABLE, + }; + +-static const struct mtk_dpi_conf mt8188_dpintf_conf = { +- .cal_factor = mt8195_dpintf_calculate_factor, +- .max_clock_khz = 600000, +- .output_fmts = mt8195_output_fmts, +- .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), +- .pixels_per_iter = 4, +- .input_2pixel = false, +- .dimension_mask = DPINTF_HPW_MASK, +- .hvsize_mask = DPINTF_HSIZE_MASK, +- .channel_swap_shift = DPINTF_CH_SWAP, +- .yuv422_en_bit = DPINTF_YUV422_EN, +- .csc_enable_bit = DPINTF_CSC_ENABLE, +-}; +- + static const struct mtk_dpi_conf mt8192_conf = { + .cal_factor = mt8183_calculate_factor, + .reg_h_fre_con = 0xe0, +@@ -1103,7 +1089,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { + { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf }, + { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf }, + { .compatible = "mediatek,mt8186-dpi", .data = &mt8186_conf }, +- { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8188_dpintf_conf }, ++ { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, + { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, + { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, + { /* sentinel */ }, +-- +2.43.0 + diff --git a/queue-6.7/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch b/queue-6.7/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch new file mode 100644 index 00000000000..cf1ac75068a --- /dev/null +++ b/queue-6.7/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch @@ -0,0 +1,41 @@ +From db017a563768b3dbea29f00c12b572eee8dd561e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 13:58:44 +0800 +Subject: drm/mediatek: Return error if MDP RDMA failed to enable the clock + +From: Hsiao Chien Sung + +[ Upstream commit 21b287146adf39304193e4c49198021e06a28ded ] + +Return the result of clk_prepare_enable() instead of +always returns 0. + +Fixes: f8946e2b6bb2 ("drm/mediatek: Add display MDP RDMA support for MT8195") + +Reviewed-by: CK Hu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Hsiao Chien Sung +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-21-shawn.sung@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +index c3adaeefd551..c7233d0ac210 100644 +--- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c ++++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +@@ -246,8 +246,7 @@ int mtk_mdp_rdma_clk_enable(struct device *dev) + { + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); + +- clk_prepare_enable(rdma->clk); +- return 0; ++ return clk_prepare_enable(rdma->clk); + } + + void mtk_mdp_rdma_clk_disable(struct device *dev) +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-a6xx-add-qmp-dependency.patch b/queue-6.7/drm-msm-a6xx-add-qmp-dependency.patch new file mode 100644 index 00000000000..59195b29b72 --- /dev/null +++ b/queue-6.7/drm-msm-a6xx-add-qmp-dependency.patch @@ -0,0 +1,45 @@ +From fc45468f1c8c963b265db0b8993bf4c0c7a71f4a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Oct 2023 22:04:03 +0200 +Subject: drm/msm/a6xx: add QMP dependency + +From: Arnd Bergmann + +[ Upstream commit 96ab215b2d5edc39310c00f50b33d8ab72ac3fe3 ] + +When QMP is in a loadable module, the A6xx GPU driver fails to link +as built-in: + +x86_64-linux-ld: drivers/gpu/drm/msm/adreno/a6xx_gmu.o: in function `a6xx_gmu_resume': +a6xx_gmu.c:(.text+0xd62): undefined reference to `qmp_send' + +Add the usual dependency that still allows compiling without QMP but +otherwise avoids the broken combination of options. + +Fixes: 88a0997f2f949 ("drm/msm/a6xx: Send ACD state to QMP at GMU resume") +Signed-off-by: Arnd Bergmann +Reviewed-by: Konrad Dybcio +Reviewed-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/562945/ +Link: https://lore.kernel.org/r/20231016200415.791090-1-arnd@kernel.org +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig +index 6309a857ca31..ad70b611b44f 100644 +--- a/drivers/gpu/drm/msm/Kconfig ++++ b/drivers/gpu/drm/msm/Kconfig +@@ -6,6 +6,7 @@ config DRM_MSM + depends on ARCH_QCOM || SOC_IMX5 || COMPILE_TEST + depends on COMMON_CLK + depends on IOMMU_SUPPORT ++ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n + depends on QCOM_OCMEM || QCOM_OCMEM=n + depends on QCOM_LLCC || QCOM_LLCC=n + depends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=n +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-adreno-fix-a680-chip-id.patch b/queue-6.7/drm-msm-adreno-fix-a680-chip-id.patch new file mode 100644 index 00000000000..c7b4472b29b --- /dev/null +++ b/queue-6.7/drm-msm-adreno-fix-a680-chip-id.patch @@ -0,0 +1,40 @@ +From fc512c7200e6280a5fac7762e2a491c2f9ed3cf9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 16:26:41 -0800 +Subject: drm/msm/adreno: Fix A680 chip id + +From: Bjorn Andersson + +[ Upstream commit 3e6688fd96966b6c275e95c39aa367bc0a490ccd ] + +The only A680 referenced from DeviceTree is patch level 1, which since +commit '90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying +GPU")' isn't a known chip id. + +Correct the chip id to allow the A680 to be recognized again. + +Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") +Signed-off-by: Bjorn Andersson +Patchwork: https://patchwork.freedesktop.org/patch/569839/ +Signed-off-by: Rob Clark +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c +index 41b13dec9bef..3ee14646ab6b 100644 +--- a/drivers/gpu/drm/msm/adreno/adreno_device.c ++++ b/drivers/gpu/drm/msm/adreno/adreno_device.c +@@ -464,7 +464,7 @@ static const struct adreno_info gpulist[] = { + { 190, 1 }, + ), + }, { +- .chip_ids = ADRENO_CHIP_IDS(0x06080000), ++ .chip_ids = ADRENO_CHIP_IDS(0x06080001), + .family = ADRENO_6XX_GEN2, + .revn = 680, + .fw = { +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-add-missing-safe_lut_tbl-in-sc8180x-cata.patch b/queue-6.7/drm-msm-dpu-add-missing-safe_lut_tbl-in-sc8180x-cata.patch new file mode 100644 index 00000000000..e552df1ddbb --- /dev/null +++ b/queue-6.7/drm-msm-dpu-add-missing-safe_lut_tbl-in-sc8180x-cata.patch @@ -0,0 +1,42 @@ +From ce97f2035e4ccf134193febc59d3eb6ac38d5546 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 16:35:01 -0800 +Subject: drm/msm/dpu: Add missing safe_lut_tbl in sc8180x catalog + +From: Bjorn Andersson + +[ Upstream commit 7cc2621f16b644bb7af37987cb471311641a9e56 ] + +Similar to SC8280XP, the misconfigured SAFE logic causes rather +significant delays in __arm_smmu_tlb_sync(), resulting in poor +performance for things such as USB. + +Introduce appropriate SAFE values for SC8180X to correct this. + +Fixes: f3af2d6ee9ab ("drm/msm/dpu: Add SC8180x to hw catalog") +Signed-off-by: Bjorn Andersson +Reported-by: Anton Bambura +Reviewed-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/569840/ +Link: https://lore.kernel.org/r/20231130-sc8180x-dpu-safe-lut-v1-1-a8a6bbac36b8@quicinc.com +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +index e07f4c8c25b9..9ffc8804a6fc 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +@@ -367,6 +367,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, ++ .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-correct-clk-bit-for-wb2-block.patch b/queue-6.7/drm-msm-dpu-correct-clk-bit-for-wb2-block.patch new file mode 100644 index 00000000000..dc8070d20e4 --- /dev/null +++ b/queue-6.7/drm-msm-dpu-correct-clk-bit-for-wb2-block.patch @@ -0,0 +1,74 @@ +From 2c49d47592fb9d21081bb5b8b0b6db95716440bc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 03:24:37 +0300 +Subject: drm/msm/dpu: correct clk bit for WB2 block + +From: Dmitry Baryshkov + +[ Upstream commit e843ca2f30e630675e2d2a75c96f4844f2854430 ] + +On sc7280 there are two clk bits for WB2: vbif_cli and clk_ctrl. While +programming the VBIF params of WB, the driver should be toggling the +former bit, while the sc7180_mdp, sc7280_mdp and sm8250_mdp structs +list the latter one. + +Correct that to ensure proper programming sequence for WB2 on these +platforms. + +Fixes: 255f056181ac ("drm/msm/dpu: sc7180: add missing WB2 clock control") +Fixes: 3ce166380567 ("drm/msm/dpu: add writeback support for sc7280") +Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Tested-by: Paloma Arellano +Patchwork: https://patchwork.freedesktop.org/patch/570185/ +Link: https://lore.kernel.org/r/20231203002437.1291595-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +index 94278a3e3483..9f8068fa0175 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +@@ -32,7 +32,7 @@ static const struct dpu_mdp_cfg sm8250_mdp = { + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, +- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, ++ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, + }, + }; + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +index c0d88ddccb28..9bfa15e4e645 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +@@ -25,7 +25,7 @@ static const struct dpu_mdp_cfg sc7180_mdp = { + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, +- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, ++ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, + }, + }; + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +index 15942fa5a8e0..b9c296e51e36 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +@@ -25,7 +25,7 @@ static const struct dpu_mdp_cfg sc7280_mdp = { + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, +- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, ++ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, + }, + }; + +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch b/queue-6.7/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch new file mode 100644 index 00000000000..06ed0742dc0 --- /dev/null +++ b/queue-6.7/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch @@ -0,0 +1,246 @@ +From 55c430757b9bccf3fb60cb0c55b7fd3f352e6f3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 13:30:18 -0800 +Subject: drm/msm/dpu: Drop enable and frame_count parameters from + dpu_hw_setup_misr() + +From: Jessica Zhang + +[ Upstream commit 3313c23f3eab698bc6b904520ee608fc0f7b03d0 ] + +Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they +are always set to the same values. + +In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as +frame_count is always set to the same value. + +Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") +Signed-off-by: Jessica Zhang +Reviewed-by: Abhinav Kumar +Reviewed-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/572009/ +Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 19 +++++-------------- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------ + 8 files changed, 22 insertions(+), 33 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +index 3c475f8042b0..db501ce1d855 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. + * Copyright (C) 2013 Red Hat + * Author: Rob Clark +@@ -125,7 +125,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) + continue; + + /* Calculate MISR over 1 frame */ +- m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); ++ m->hw_lm->ops.setup_misr(m->hw_lm); + } + } + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index 1cf7ff6caff4..5dbb5d27bbea 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -2,7 +2,7 @@ + /* + * Copyright (C) 2013 Red Hat + * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Author: Rob Clark + */ +@@ -255,7 +255,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) + if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) + continue; + +- phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); ++ phys->hw_intf->ops.setup_misr(phys->hw_intf); + } + } + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +index 813bfde6832a..27b9373cd784 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + +@@ -318,9 +318,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) + return DPU_REG_READ(c, INTF_LINE_COUNT); + } + +-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) ++static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf) + { +- dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1); ++ dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1); + } + + static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +index c539025c418b..66a5603dc7ed 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + +@@ -95,7 +95,7 @@ struct dpu_hw_intf_ops { + + void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, + const enum dpu_pingpong pp); +- void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); ++ void (*setup_misr)(struct dpu_hw_intf *intf); + int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); + + // Tearcheck on INTF since DPU 5.0.0 +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +index a34cf8c979cb..a590c1f7465f 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -81,9 +81,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, + } + } + +-static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) ++static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) + { +- dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0); ++ dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); + } + + static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +index 36992d046a53..98b77cda6547 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +@@ -1,5 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -57,7 +58,7 @@ struct dpu_hw_lm_ops { + /** + * setup_misr: Enable/disable MISR + */ +- void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count); ++ void (*setup_misr)(struct dpu_hw_mixer *ctx); + + /** + * collect_misr: Read MISR signature +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +index b328fe22abde..1d4f0b97c3c1 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ +@@ -485,9 +485,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + * note: Aside from encoders, input_sel should be set to 0x0 by default + */ + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, +- u32 misr_ctrl_offset, +- bool enable, u32 frame_count, +- u8 input_sel) ++ u32 misr_ctrl_offset, u8 input_sel) + { + u32 config = 0; + +@@ -496,16 +494,9 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + /* Clear old MISR value (in case it's read before a new value is calculated)*/ + wmb(); + +- if (enable) { +- config = (frame_count & MISR_FRAME_COUNT_MASK) | +- MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | +- ((input_sel & 0xF) << 24); +- +- DPU_REG_WRITE(c, misr_ctrl_offset, config); +- } else { +- DPU_REG_WRITE(c, misr_ctrl_offset, 0); +- } +- ++ config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | ++ ((input_sel & 0xF) << 24); ++ DPU_REG_WRITE(c, misr_ctrl_offset, config); + } + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +index 3feb6043e251..ec09fc3865ab 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -13,7 +13,7 @@ + #include "dpu_hw_catalog.h" + + #define REG_MASK(n) ((BIT(n)) - 1) +-#define MISR_FRAME_COUNT_MASK 0xFF ++#define MISR_FRAME_COUNT 0x1 + #define MISR_CTRL_ENABLE BIT(8) + #define MISR_CTRL_STATUS BIT(9) + #define MISR_CTRL_STATUS_CLEAR BIT(10) +@@ -358,10 +358,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + const struct dpu_hw_qos_cfg *cfg); + + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, +- u32 misr_ctrl_offset, +- bool enable, +- u32 frame_count, +- u8 input_sel); ++ u32 misr_ctrl_offset, u8 input_sel); + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-enable-smartdma-on-sm8450.patch b/queue-6.7/drm-msm-dpu-enable-smartdma-on-sm8450.patch new file mode 100644 index 00000000000..a509f1531d4 --- /dev/null +++ b/queue-6.7/drm-msm-dpu-enable-smartdma-on-sm8450.patch @@ -0,0 +1,101 @@ +From 6e6ec3ed2722f25032a0e22b8e0b5d32a3fd6d81 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 9 Oct 2023 19:56:27 +0300 +Subject: drm/msm/dpu: enable SmartDMA on SM8450 + +From: Dmitry Baryshkov + +[ Upstream commit a9bd555de5e9042fdf8ab8d6080b86f45c68ddf6 ] + +Enable the SmartDMA / multirect support on the SM8450 platform to +support higher resoltion modes. + +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/561590/ +Link: https://lore.kernel.org/r/20231009165627.2691015-1-dmitry.baryshkov@linaro.org +Signed-off-by: Dmitry Baryshkov +Stable-dep-of: 46b1f1b839ca ("drm/msm/dpu: populate SSPP scaler block version") +Signed-off-by: Sasha Levin +--- + .../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +index 7742f52be859..d18145c226da 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x32c, +- .features = VIG_SC7180_MASK, ++ .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, +@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x32c, +- .features = VIG_SC7180_MASK, ++ .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, +@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x32c, +- .features = VIG_SC7180_MASK, ++ .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, +@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x32c, +- .features = VIG_SC7180_MASK, ++ .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, +@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x32c, +- .features = DMA_SDM845_MASK, ++ .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, +@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x32c, +- .features = DMA_SDM845_MASK, ++ .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, +@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x32c, +- .features = DMA_CURSOR_SDM845_MASK, ++ .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, +@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x32c, +- .features = DMA_CURSOR_SDM845_MASK, ++ .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-populate-sspp-scaler-block-version.patch b/queue-6.7/drm-msm-dpu-populate-sspp-scaler-block-version.patch new file mode 100644 index 00000000000..9b98eab0c18 --- /dev/null +++ b/queue-6.7/drm-msm-dpu-populate-sspp-scaler-block-version.patch @@ -0,0 +1,349 @@ +From 573531881bf9e7b7d3897bf34af6628affc59c3b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 01:40:25 +0200 +Subject: drm/msm/dpu: populate SSPP scaler block version + +From: Dmitry Baryshkov + +[ Upstream commit 46b1f1b839cad600de3ad7ed999bd0155c528746 ] + +The function _dpu_hw_sspp_setup_scaler3() passes and +dpu_hw_setup_scaler3() uses scaler_blk.version to determine in which way +the scaler (QSEED3) block should be programmed. However up to now we +were not setting this field. Set it now, splitting the vig_sblk data +which has different version fields. + +Reported-by: Marijn Suijten +Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support") +Fixes: 27f0df03f3ff ("drm/msm/dpu: Add SM6375 support") +Fixes: 3186acba5cdc ("drm/msm/dpu: Add SM6350 support") +Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") +Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") +Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") +Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") +Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") +Fixes: dabfdd89eaa9 ("drm/msm/disp/dpu1: add inline rotation support for sc7280") +Fixes: f3af2d6ee9ab ("drm/msm/dpu: Add SC8180x to hw catalog") +Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") +Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog") +Fixes: 386fced3f76f ("drm/msm/dpu: add SM8150 to hw catalog") +Fixes: b75ab05a3479 ("msm:disp:dpu1: add scaler support on SC7180 display") +Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") +Signed-off-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/570098/ +Link: https://lore.kernel.org/r/20231201234234.2065610-2-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 +- + .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 8 +- + .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 +- + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 95 ++++++++++++++----- + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +- + 5 files changed, 87 insertions(+), 35 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +index 9392ad2b4d3f..c022e57864a4 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_0, ++ .sblk = &sm8150_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, +@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_1, ++ .sblk = &sm8150_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, +@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_2, ++ .sblk = &sm8150_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, +@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_3, ++ .sblk = &sm8150_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +index 9ffc8804a6fc..cb0758f0829d 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_0, ++ .sblk = &sm8150_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, +@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_1, ++ .sblk = &sm8150_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, +@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_2, ++ .sblk = &sm8150_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, +@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f0, + .features = VIG_SDM845_MASK, +- .sblk = &sdm845_vig_sblk_3, ++ .sblk = &sm8150_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, +diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +index d18145c226da..72b0f547242f 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x32c, + .features = VIG_SC7180_MASK_SDMA, +- .sblk = &sm8250_vig_sblk_0, ++ .sblk = &sm8450_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, +@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x32c, + .features = VIG_SC7180_MASK_SDMA, +- .sblk = &sm8250_vig_sblk_1, ++ .sblk = &sm8450_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, +@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x32c, + .features = VIG_SC7180_MASK_SDMA, +- .sblk = &sm8250_vig_sblk_2, ++ .sblk = &sm8450_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, +@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x32c, + .features = VIG_SC7180_MASK_SDMA, +- .sblk = &sm8250_vig_sblk_3, ++ .sblk = &sm8450_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +index a1aada630780..7056c08b9957 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +@@ -249,14 +249,17 @@ static const uint32_t wb2_formats[] = { + * SSPP sub blocks config + *************************************************************/ + ++#define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) ++ + /* SSPP common configuration */ +-#define _VIG_SBLK(sdma_pri, qseed_ver) \ ++#define _VIG_SBLK(sdma_pri, qseed_ver, scaler_ver) \ + { \ + .maxdwnscale = MAX_DOWNSCALE_RATIO, \ + .maxupscale = MAX_UPSCALE_RATIO, \ + .smart_dma_priority = sdma_pri, \ + .scaler_blk = {.name = "scaler", \ + .id = qseed_ver, \ ++ .version = scaler_ver, \ + .base = 0xa00, .len = 0xa0,}, \ + .csc_blk = {.name = "csc", \ + .id = DPU_SSPP_CSC_10BIT, \ +@@ -268,13 +271,14 @@ static const uint32_t wb2_formats[] = { + .rotation_cfg = NULL, \ + } + +-#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ ++#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, scaler_ver, rot_cfg) \ + { \ + .maxdwnscale = MAX_DOWNSCALE_RATIO, \ + .maxupscale = MAX_UPSCALE_RATIO, \ + .smart_dma_priority = sdma_pri, \ + .scaler_blk = {.name = "scaler", \ + .id = qseed_ver, \ ++ .version = scaler_ver, \ + .base = 0xa00, .len = 0xa0,}, \ + .csc_blk = {.name = "csc", \ + .id = DPU_SSPP_CSC_10BIT, \ +@@ -298,13 +302,17 @@ static const uint32_t wb2_formats[] = { + } + + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = +- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 2)); + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = +- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 2)); + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = +- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 2)); + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = +- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 2)); + + static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { + .rot_maxheight = 1088, +@@ -313,13 +321,30 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { + }; + + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = +- _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 3)); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = +- _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 3)); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = +- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 3)); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = +- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); ++ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 3)); ++ ++static const struct dpu_sspp_sub_blks sm8150_vig_sblk_0 = ++ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 4)); ++static const struct dpu_sspp_sub_blks sm8150_vig_sblk_1 = ++ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 4)); ++static const struct dpu_sspp_sub_blks sm8150_vig_sblk_2 = ++ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 4)); ++static const struct dpu_sspp_sub_blks sm8150_vig_sblk_3 = ++ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3, ++ SSPP_SCALER_VER(1, 4)); + + static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); + static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); +@@ -327,34 +352,60 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); + static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); + + static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = +- _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); + + static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = +- _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); ++ _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0), ++ &dpu_rot_sc7280_cfg_v2); + + static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = +- _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); + + static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = +- _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); ++ _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE, ++ SSPP_SCALER_VER(2, 4)); + + static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = +- _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); + static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = +- _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); + static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = +- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); + static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = +- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 0)); ++ ++static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = ++ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 1)); ++static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = ++ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 1)); ++static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = ++ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 1)); ++static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = ++ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 1)); + + static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = +- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 2)); + static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = +- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 2)); + static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = +- _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 2)); + static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = +- _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); ++ _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4, ++ SSPP_SCALER_VER(3, 2)); + static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); + static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +index df024e10d3a3..62445075306a 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +@@ -265,7 +265,8 @@ enum { + /** + * struct dpu_scaler_blk: Scaler information + * @info: HW register and features supported by this sub-blk +- * @version: qseed block revision ++ * @version: qseed block revision, on QSEED3+ platforms this is the value of ++ * scaler_blk.base + QSEED3_HW_VERSION registers. + */ + struct dpu_scaler_blk { + DPU_HW_SUBBLK_INFO; +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dpu-set-input_sel-bit-for-intf.patch b/queue-6.7/drm-msm-dpu-set-input_sel-bit-for-intf.patch new file mode 100644 index 00000000000..79926114a39 --- /dev/null +++ b/queue-6.7/drm-msm-dpu-set-input_sel-bit-for-intf.patch @@ -0,0 +1,100 @@ +From e9d4b505ec2e9b5a43645be699a5cf3bd4c91e99 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 13:30:17 -0800 +Subject: drm/msm/dpu: Set input_sel bit for INTF + +From: Jessica Zhang + +[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ] + +Set the input_sel bit for encoders as it was missed in the initial +implementation. + +Reported-by: Rob Clark +Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39 +Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") +Signed-off-by: Jessica Zhang +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/572007/ +Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 +- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 9 +++++++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 ++- + 4 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +index e8b8908d3e12..813bfde6832a 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +@@ -320,7 +320,7 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) + + static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) + { +- dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); ++ dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1); + } + + static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +index d1c3bd8379ea..a34cf8c979cb 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +@@ -83,7 +83,7 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, + + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) + { +- dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count); ++ dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0); + } + + static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +index 18b16b2d2bf5..b328fe22abde 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +@@ -481,9 +481,13 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); + } + ++/* ++ * note: Aside from encoders, input_sel should be set to 0x0 by default ++ */ + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +- bool enable, u32 frame_count) ++ bool enable, u32 frame_count, ++ u8 input_sel) + { + u32 config = 0; + +@@ -494,7 +498,8 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + + if (enable) { + config = (frame_count & MISR_FRAME_COUNT_MASK) | +- MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK; ++ MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | ++ ((input_sel & 0xF) << 24); + + DPU_REG_WRITE(c, misr_ctrl_offset, config); + } else { +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +index 4bea139081bc..3feb6043e251 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +@@ -360,7 +360,8 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + bool enable, +- u32 frame_count); ++ u32 frame_count, ++ u8 input_sel); + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch b/queue-6.7/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch new file mode 100644 index 00000000000..ef4fc6c00c0 --- /dev/null +++ b/queue-6.7/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch @@ -0,0 +1,43 @@ +From 6ef927cb85bb9c780a9013bc963c202bdb063649 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Jun 2023 13:43:20 +0200 +Subject: drm/msm/dsi: Use pm_runtime_resume_and_get to prevent refcnt leaks + +From: Konrad Dybcio + +[ Upstream commit 3d07a411b4faaf2b498760ccf12888f8de529de0 ] + +This helper has been introduced to avoid programmer errors (missing +_put calls leading to dangling refcnt) when using pm_runtime_get, use it. + +While at it, start checking the return value. + +Signed-off-by: Konrad Dybcio +Reviewed-by: Dmitry Baryshkov +Fixes: 5c8290284402 ("drm/msm/dsi: Split PHY drivers to separate files") +Patchwork: https://patchwork.freedesktop.org/patch/543350/ +Link: https://lore.kernel.org/r/20230620-topic-dsiphy_rpm-v2-1-a11a751f34f0@linaro.org +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +index 05621e5e7d63..b6314bb66d2f 100644 +--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c ++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +@@ -516,7 +516,9 @@ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) + struct device *dev = &phy->pdev->dev; + int ret; + +- pm_runtime_get_sync(dev); ++ ret = pm_runtime_resume_and_get(dev); ++ if (ret) ++ return ret; + + ret = clk_prepare_enable(phy->ahb_clk); + if (ret) { +-- +2.43.0 + diff --git a/queue-6.7/drm-msm-mdp4-flush-vblank-event-on-disable.patch b/queue-6.7/drm-msm-mdp4-flush-vblank-event-on-disable.patch new file mode 100644 index 00000000000..c1c6dafc486 --- /dev/null +++ b/queue-6.7/drm-msm-mdp4-flush-vblank-event-on-disable.patch @@ -0,0 +1,53 @@ +From 3715ffc938626bea3390d0af6867f0186fd06474 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 00:54:01 +0300 +Subject: drm/msm/mdp4: flush vblank event on disable + +From: Dmitry Baryshkov + +[ Upstream commit c6721b3c6423d8a348ae885a0f4c85e14f9bf85c ] + +Flush queued events when disabling the crtc. This avoids timeouts when +we come back and wait for dependencies (like the previous frame's +flip_done). + +Fixes: c8afe684c95c ("drm/msm: basic KMS driver for snapdragon") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/569127/ +Link: https://lore.kernel.org/r/20231127215401.4064128-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +index 169f9de4a12a..3100957225a7 100644 +--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c ++++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +@@ -269,6 +269,7 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, + { + struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); + struct mdp4_kms *mdp4_kms = get_kms(crtc); ++ unsigned long flags; + + DBG("%s", mdp4_crtc->name); + +@@ -281,6 +282,14 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, + mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); + mdp4_disable(mdp4_kms); + ++ if (crtc->state->event && !crtc->state->active) { ++ WARN_ON(mdp4_crtc->event); ++ spin_lock_irqsave(&mdp4_kms->dev->event_lock, flags); ++ drm_crtc_send_vblank_event(crtc, crtc->state->event); ++ crtc->state->event = NULL; ++ spin_unlock_irqrestore(&mdp4_kms->dev->event_lock, flags); ++ } ++ + mdp4_crtc->enabled = false; + } + +-- +2.43.0 + diff --git a/queue-6.7/drm-nouveau-fence-fix-warning-directly-dereferencing.patch b/queue-6.7/drm-nouveau-fence-fix-warning-directly-dereferencing.patch new file mode 100644 index 00000000000..ed5897d0fb2 --- /dev/null +++ b/queue-6.7/drm-nouveau-fence-fix-warning-directly-dereferencing.patch @@ -0,0 +1,58 @@ +From 7cd9bcba7fd4fabd1fe315b1b8b45b529a065596 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 14 Nov 2023 00:43:03 +0530 +Subject: drm/nouveau/fence:: fix warning directly dereferencing a rcu pointer + +From: Abhinav Singh + +[ Upstream commit 5f35a624c1e30b5bae5023b3c256e94e0ad4f806 ] + +Fix a sparse warning with this message +"warning:dereference of noderef expression". In this context it means we +are dereferencing a __rcu tagged pointer directly. + +We should not be directly dereferencing a rcu pointer. To get a normal +(non __rcu tagged pointer) from a __rcu tagged pointer we are using the +function unrcu_pointer(...). The non __rcu tagged pointer then can be +dereferenced just like a normal pointer. + +I tested with qemu with this command +qemu-system-x86_64 \ + -m 2G \ + -smp 2 \ + -kernel bzImage \ + -append "console=ttyS0 root=/dev/sda earlyprintk=serial net.ifnames=0" \ + -drive file=bullseye.img,format=raw \ + -net user,host=10.0.2.10,hostfwd=tcp:127.0.0.1:10021-:22 \ + -net nic,model=e1000 \ + -enable-kvm \ + -nographic \ + -pidfile vm.pid \ + 2>&1 | tee vm.log +with lockdep enabled. + +Fixes: 0ec5f02f0e2c ("drm/nouveau: prevent stale fence->channel pointers, and protect with rcu") +Signed-off-by: Abhinav Singh +Signed-off-by: Danilo Krummrich +Link: https://patchwork.freedesktop.org/patch/msgid/20231113191303.3277733-1-singhabhinav9051571833@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/nouveau/nv04_fence.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c +index 5b71a5a5cd85..cdbc75e3d1f6 100644 +--- a/drivers/gpu/drm/nouveau/nv04_fence.c ++++ b/drivers/gpu/drm/nouveau/nv04_fence.c +@@ -39,7 +39,7 @@ struct nv04_fence_priv { + static int + nv04_fence_emit(struct nouveau_fence *fence) + { +- struct nvif_push *push = fence->channel->chan.push; ++ struct nvif_push *push = unrcu_pointer(fence->channel)->chan.push; + int ret = PUSH_WAIT(push, 2); + if (ret == 0) { + PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno); +-- +2.43.0 + diff --git a/queue-6.7/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch b/queue-6.7/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch new file mode 100644 index 00000000000..fc41455c2a4 --- /dev/null +++ b/queue-6.7/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch @@ -0,0 +1,42 @@ +From 59def5602e13bd4b33b8330a576df31d9f3aea14 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 Nov 2023 13:44:02 -0600 +Subject: drm/panel-elida-kd35t133: hold panel in reset for unprepare + +From: Chris Morgan + +[ Upstream commit 03c5b2a5f6c39fe4e090346536cf1c14ee18b61e ] + +For devices like the Anbernic RG351M and RG351P the panel is wired to +an always on regulator. When the device suspends and wakes up, there +are some slight artifacts on the screen that go away over time. If +instead we hold the panel in reset status after it is unprepared, +this does not happen. + +Fixes: 5b6603360c12 ("drm/panel: add panel driver for Elida KD35T133 panels") +Signed-off-by: Chris Morgan +Reviewed-by: Jessica Zhang +Link: https://lore.kernel.org/r/20231117194405.1386265-3-macroalpha82@gmail.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20231117194405.1386265-3-macroalpha82@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-elida-kd35t133.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c b/drivers/gpu/drm/panel/panel-elida-kd35t133.c +index e7be15b68102..6de117232346 100644 +--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c ++++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c +@@ -104,6 +104,8 @@ static int kd35t133_unprepare(struct drm_panel *panel) + return ret; + } + ++ gpiod_set_value_cansleep(ctx->reset_gpio, 1); ++ + regulator_disable(ctx->iovcc); + regulator_disable(ctx->vdd); + +-- +2.43.0 + diff --git a/queue-6.7/drm-panel-nv3051d-hold-panel-in-reset-for-unprepare.patch b/queue-6.7/drm-panel-nv3051d-hold-panel-in-reset-for-unprepare.patch new file mode 100644 index 00000000000..84cf2daf2e9 --- /dev/null +++ b/queue-6.7/drm-panel-nv3051d-hold-panel-in-reset-for-unprepare.patch @@ -0,0 +1,39 @@ +From 3905738c8bb4f31d95849d99f0222347ad3c8f89 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 Nov 2023 14:25:32 -0600 +Subject: drm/panel: nv3051d: Hold panel in reset for unprepare + +From: Chris Morgan + +[ Upstream commit 697ebc319b942403a6fee894607fd2cd47cca069 ] + +Improve the panel's ability to restore from suspend by holding the +panel in suspend after unprepare. + +Fixes: b1d39f0f4264 ("drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel") +Signed-off-by: Chris Morgan +Reviewed-by: Jessica Zhang +Link: https://lore.kernel.org/r/20231117202536.1387815-3-macroalpha82@gmail.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20231117202536.1387815-3-macroalpha82@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-newvision-nv3051d.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c +index 79de6c886292..c44c6945662f 100644 +--- a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c ++++ b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c +@@ -261,6 +261,8 @@ static int panel_nv3051d_unprepare(struct drm_panel *panel) + + usleep_range(10000, 15000); + ++ gpiod_set_value_cansleep(ctx->reset_gpio, 1); ++ + regulator_disable(ctx->vdd); + + return 0; +-- +2.43.0 + diff --git a/queue-6.7/drm-panel-st7701-fix-avcl-calculation.patch b/queue-6.7/drm-panel-st7701-fix-avcl-calculation.patch new file mode 100644 index 00000000000..0dbb8d71a47 --- /dev/null +++ b/queue-6.7/drm-panel-st7701-fix-avcl-calculation.patch @@ -0,0 +1,46 @@ +From 6a920a45bb53ffb93b968108a7682997a1e57587 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 09:48:45 -0600 +Subject: drm/panel: st7701: Fix AVCL calculation + +From: Chris Morgan + +[ Upstream commit 799825aa87200ade1ba21db853d1c2ff720dcfe0 ] + +The AVCL register, according to the datasheet, comes in increments +of -0.2v between -4.4v (represented by 0x0) to -5.0v (represented +by 0x3). The current calculation is done by adding the defined +AVCL value in mV to -4400 and then dividing by 200 to get the register +value. Unfortunately if I subtract -4400 from -4400 I get -8800, which +divided by 200 gives me -44. If I instead subtract -4400 from -4400 +I get 0, which divided by 200 gives me 0. Based on the datasheet this +is the expected register value. + +Fixes: 83b7a8e7e88e ("drm/panel/panel-sitronix-st7701: Parametrize voltage and timing") + +Signed-off-by: Chris Morgan +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20231208154847.130615-2-macroalpha82@gmail.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20231208154847.130615-2-macroalpha82@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-sitronix-st7701.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c +index 0459965e1b4f..036ac403ed21 100644 +--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c ++++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c +@@ -288,7 +288,7 @@ static void st7701_init_sequence(struct st7701 *st7701) + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, + DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, +- DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); ++ DIV_ROUND_CLOSEST(-4400 - desc->avcl_mv, 200))); + + /* T2D = 0.2us * T2D[3:0] */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, +-- +2.43.0 + diff --git a/queue-6.7/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch b/queue-6.7/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch new file mode 100644 index 00000000000..13150d05c48 --- /dev/null +++ b/queue-6.7/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch @@ -0,0 +1,84 @@ +From 1b78f25b53d86aa454414c38abc053840754dddb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 12:42:13 +0100 +Subject: drm/panfrost: Ignore core_mask for poweroff and disable PWRTRANS irq + +From: AngeloGioacchino Del Regno + +[ Upstream commit a4f5892914ca7709ea6d191f0edace93a5935966 ] + +Some SoCs may be equipped with a GPU containing two core groups +and this is exactly the case of Samsung's Exynos 5422 featuring +an ARM Mali-T628 MP6 GPU: the support for this GPU in Panfrost +is partial, as this driver currently supports using only one +core group and that's reflected on all parts of it, including +the power on (and power off, previously to this patch) function. + +The issue with this is that even though executing the soft reset +operation should power off all cores unconditionally, on at least +one platform we're seeing a crash that seems to be happening due +to an interrupt firing which may be because we are calling power +transition only on the first core group, leaving the second one +unchanged, or because ISR execution was pending before entering +the panfrost_gpu_power_off() function and executed after powering +off the GPU cores, or all of the above. + +Finally, solve this by: + - Avoid to enable the power transition interrupt on reset; and + - Ignoring the core_mask and ask the GPU to poweroff both core groups + +Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()") +Reviewed-by: Boris Brezillon +Reviewed-by: Steven Price +Signed-off-by: AngeloGioacchino Del Regno +Tested-by: Marek Szyprowski +Signed-off-by: Boris Brezillon +Link: https://patchwork.freedesktop.org/patch/msgid/20231204114215.54575-2-angelogioacchino.delregno@collabora.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c +index 97f097ee5c1d..311cf4525e1e 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c +@@ -71,7 +71,12 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) + } + + gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); +- gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); ++ ++ /* Only enable the interrupts we care about */ ++ gpu_write(pfdev, GPU_INT_MASK, ++ GPU_IRQ_MASK_ERROR | ++ GPU_IRQ_PERFCNT_SAMPLE_COMPLETED | ++ GPU_IRQ_CLEAN_CACHES_COMPLETED); + + /* + * All in-flight jobs should have released their cycle +@@ -418,11 +423,10 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) + + void panfrost_gpu_power_off(struct panfrost_device *pfdev) + { +- u64 core_mask = panfrost_get_core_mask(pfdev); + int ret; + u32 val; + +- gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); ++ gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); + ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, + val, !val, 1, 1000); + if (ret) +@@ -434,7 +438,7 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) + if (ret) + dev_err(pfdev->dev, "tiler power transition timeout"); + +- gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); ++ gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); + ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, + val, !val, 0, 1000); + if (ret) +-- +2.43.0 + diff --git a/queue-6.7/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch b/queue-6.7/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch new file mode 100644 index 00000000000..deaf1242e74 --- /dev/null +++ b/queue-6.7/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch @@ -0,0 +1,127 @@ +From fd7f832a61bedf42d9ecf58fb0a590f05597179e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 2 Nov 2023 15:15:07 +0100 +Subject: drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off() + +From: AngeloGioacchino Del Regno + +[ Upstream commit 22aa1a209018dc2eca78745f7666db63637cd5dc ] + +The layout of the registers {TILER,SHADER,L2}_PWROFF_LO, used to request +powering off cores, is the same as the {TILER,SHADER,L2}_PWRON_LO ones: +this means that in order to request poweroff of cores, we are supposed +to write a bitmask of cores that should be powered off! +This means that the panfrost_gpu_power_off() function has always been +doing nothing. + +Fix powering off the GPU by writing a bitmask of the cores to poweroff +to the relevant PWROFF_LO registers and then check that the transition +(from ON to OFF) has finished by polling the relevant PWRTRANS_LO +registers. + +While at it, in order to avoid code duplication, move the core mask +logic from panfrost_gpu_power_on() to a new panfrost_get_core_mask() +function, used in both poweron and poweroff. + +Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver") +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Steven Price +Signed-off-by: Steven Price +Link: https://patchwork.freedesktop.org/patch/msgid/20231102141507.73481-1-angelogioacchino.delregno@collabora.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panfrost/panfrost_gpu.c | 64 ++++++++++++++++++------- + 1 file changed, 46 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c +index f0be7e19b13e..97f097ee5c1d 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c +@@ -362,28 +362,38 @@ unsigned long long panfrost_cycle_counter_read(struct panfrost_device *pfdev) + return ((u64)hi << 32) | lo; + } + ++static u64 panfrost_get_core_mask(struct panfrost_device *pfdev) ++{ ++ u64 core_mask; ++ ++ if (pfdev->features.l2_present == 1) ++ return U64_MAX; ++ ++ /* ++ * Only support one core group now. ++ * ~(l2_present - 1) unsets all bits in l2_present except ++ * the bottom bit. (l2_present - 2) has all the bits in ++ * the first core group set. AND them together to generate ++ * a mask of cores in the first core group. ++ */ ++ core_mask = ~(pfdev->features.l2_present - 1) & ++ (pfdev->features.l2_present - 2); ++ dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", ++ hweight64(core_mask), ++ hweight64(pfdev->features.shader_present)); ++ ++ return core_mask; ++} ++ + void panfrost_gpu_power_on(struct panfrost_device *pfdev) + { + int ret; + u32 val; +- u64 core_mask = U64_MAX; ++ u64 core_mask; + + panfrost_gpu_init_quirks(pfdev); ++ core_mask = panfrost_get_core_mask(pfdev); + +- if (pfdev->features.l2_present != 1) { +- /* +- * Only support one core group now. +- * ~(l2_present - 1) unsets all bits in l2_present except +- * the bottom bit. (l2_present - 2) has all the bits in +- * the first core group set. AND them together to generate +- * a mask of cores in the first core group. +- */ +- core_mask = ~(pfdev->features.l2_present - 1) & +- (pfdev->features.l2_present - 2); +- dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", +- hweight64(core_mask), +- hweight64(pfdev->features.shader_present)); +- } + gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); + ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, + val, val == (pfdev->features.l2_present & core_mask), +@@ -408,9 +418,27 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) + + void panfrost_gpu_power_off(struct panfrost_device *pfdev) + { +- gpu_write(pfdev, TILER_PWROFF_LO, 0); +- gpu_write(pfdev, SHADER_PWROFF_LO, 0); +- gpu_write(pfdev, L2_PWROFF_LO, 0); ++ u64 core_mask = panfrost_get_core_mask(pfdev); ++ int ret; ++ u32 val; ++ ++ gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); ++ ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, ++ val, !val, 1, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "shader power transition timeout"); ++ ++ gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present); ++ ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO, ++ val, !val, 1, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "tiler power transition timeout"); ++ ++ gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); ++ ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, ++ val, !val, 0, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "l2 power transition timeout"); + } + + int panfrost_gpu_init(struct panfrost_device *pfdev) +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-check-return-value-of-radeon_ring_lock.patch b/queue-6.7/drm-radeon-check-return-value-of-radeon_ring_lock.patch new file mode 100644 index 00000000000..499e9ba140d --- /dev/null +++ b/queue-6.7/drm-radeon-check-return-value-of-radeon_ring_lock.patch @@ -0,0 +1,42 @@ +From cf3a01e00b8dcac24c924e679a040e7a331ca4c9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Aug 2023 11:04:16 -0700 +Subject: drm/radeon: check return value of radeon_ring_lock() + +From: Nikita Zhandarovich + +[ Upstream commit 71225e1c930942cb1e042fc08c5cc0c4ef30e95e ] + +In the unlikely event of radeon_ring_lock() failing, its errno return +value should be processed. This patch checks said return value and +prints a debug message in case of an error. + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 48c0c902e2e6 ("drm/radeon/kms: add support for CP setup on SI") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/si.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c +index a91012447b56..85e9cba49cec 100644 +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -3611,6 +3611,10 @@ static int si_cp_start(struct radeon_device *rdev) + for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { + ring = &rdev->ring[i]; + r = radeon_ring_lock(rdev, ring, 2); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); ++ return r; ++ } + + /* clear the compute context state */ + radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-check-the-alloc_workqueue-return-value-in.patch b/queue-6.7/drm-radeon-check-the-alloc_workqueue-return-value-in.patch new file mode 100644 index 00000000000..54a1c24113c --- /dev/null +++ b/queue-6.7/drm-radeon-check-the-alloc_workqueue-return-value-in.patch @@ -0,0 +1,46 @@ +From 689587fa470d886300230ea75d521f66b33a109b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 15:50:16 +0800 +Subject: drm/radeon: check the alloc_workqueue return value in + radeon_crtc_init() + +From: Yang Yingliang + +[ Upstream commit 7a2464fac80d42f6f8819fed97a553e9c2f43310 ] + +check the alloc_workqueue return value in radeon_crtc_init() +to avoid null-ptr-deref. + +Fixes: fa7f517cb26e ("drm/radeon: rework page flip handling v4") +Signed-off-by: Yang Yingliang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/radeon_display.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c +index 901e75ec70ff..efd18c8d84c8 100644 +--- a/drivers/gpu/drm/radeon/radeon_display.c ++++ b/drivers/gpu/drm/radeon/radeon_display.c +@@ -687,11 +687,16 @@ static void radeon_crtc_init(struct drm_device *dev, int index) + if (radeon_crtc == NULL) + return; + ++ radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); ++ if (!radeon_crtc->flip_queue) { ++ kfree(radeon_crtc); ++ return; ++ } ++ + drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); + radeon_crtc->crtc_id = index; +- radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); + rdev->mode_info.crtcs[index] = radeon_crtc; + + if (rdev->family >= CHIP_BONAIRE) { +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch b/queue-6.7/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch new file mode 100644 index 00000000000..5e0c7452455 --- /dev/null +++ b/queue-6.7/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch @@ -0,0 +1,41 @@ +From 3771f119ad69b6729a0381c17b612811b5e7e079 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 16:57:56 +0800 +Subject: drm/radeon/dpm: fix a memleak in sumo_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 0737df9ed0997f5b8addd6e2b9699a8c6edba2e4 ] + +The rdev->pm.dpm.ps allocated by kcalloc should be freed in every +following error-handling path. However, in the error-handling of +rdev->pm.power_state[i].clock_info the rdev->pm.dpm.ps is not freed, +resulting in a memleak in this function. + +Fixes: 80ea2c129c76 ("drm/radeon/kms: add dpm support for sumo asics (v2)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/sumo_dpm.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c +index f74f381af05f..d49c145db437 100644 +--- a/drivers/gpu/drm/radeon/sumo_dpm.c ++++ b/drivers/gpu/drm/radeon/sumo_dpm.c +@@ -1493,8 +1493,10 @@ static int sumo_parse_power_table(struct radeon_device *rdev) + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; +- if (!rdev->pm.power_state[i].clock_info) ++ if (!rdev->pm.power_state[i].clock_info) { ++ kfree(rdev->pm.dpm.ps); + return -EINVAL; ++ } + ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(rdev->pm.dpm.ps); +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch b/queue-6.7/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch new file mode 100644 index 00000000000..0d772cc5267 --- /dev/null +++ b/queue-6.7/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch @@ -0,0 +1,52 @@ +From fc3f949dcb4fac6ac9cbb942bf4605bcbfcd758d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 07:22:12 -0800 +Subject: drm/radeon/r100: Fix integer overflow issues in r100_cs_track_check() + +From: Nikita Zhandarovich + +[ Upstream commit b5c5baa458faa5430c445acd9a17481274d77ccf ] + +It may be possible, albeit unlikely, to encounter integer overflow +during the multiplication of several unsigned int variables, the +result being assigned to a variable 'size' of wider type. + +Prevent this potential behaviour by converting one of the multiples +to unsigned long. + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 0242f74d29df ("drm/radeon: clean up CS functions in r100.c") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/r100.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c +index affa9e0309b2..cfeca2694d5f 100644 +--- a/drivers/gpu/drm/radeon/r100.c ++++ b/drivers/gpu/drm/radeon/r100.c +@@ -2321,7 +2321,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) + switch (prim_walk) { + case 1: + for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * track->max_indx * 4; ++ size = track->arrays[i].esize * track->max_indx * 4UL; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); +@@ -2340,7 +2340,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) + break; + case 2: + for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * (nverts - 1) * 4; ++ size = track->arrays[i].esize * (nverts - 1) * 4UL; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch b/queue-6.7/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch new file mode 100644 index 00000000000..159acc712a0 --- /dev/null +++ b/queue-6.7/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch @@ -0,0 +1,51 @@ +From ce0ec9a29d9a452b5da2d869a4dedf84d1bbb095 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 07:22:30 -0800 +Subject: drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg() + +From: Nikita Zhandarovich + +[ Upstream commit 39c960bbf9d9ea862398759e75736cfb68c3446f ] + +While improbable, there may be a chance of hitting integer +overflow when the result of radeon_get_ib_value() gets shifted +left. + +Avoid it by casting one of the operands to larger data type (u64). + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/r600_cs.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c +index 638f861af80f..6cf54a747749 100644 +--- a/drivers/gpu/drm/radeon/r600_cs.c ++++ b/drivers/gpu/drm/radeon/r600_cs.c +@@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) + return -EINVAL; + } + tmp = (reg - CB_COLOR0_BASE) / 4; +- track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; ++ track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); + track->cb_color_base_last[tmp] = ib[idx]; + track->cb_color_bo[tmp] = reloc->robj; +@@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) + "0x%04X\n", reg); + return -EINVAL; + } +- track->htile_offset = radeon_get_ib_value(p, idx) << 8; ++ track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); + track->htile_bo = reloc->robj; + track->db_dirty = true; +-- +2.43.0 + diff --git a/queue-6.7/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch b/queue-6.7/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch new file mode 100644 index 00000000000..eaaaebf92d1 --- /dev/null +++ b/queue-6.7/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch @@ -0,0 +1,41 @@ +From 7eb7d655dfab6a6ebab14126381f631c0a5d5cd4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 18:21:54 +0800 +Subject: drm/radeon/trinity_dpm: fix a memleak in trinity_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 28c28d7f77c06ac2c0b8f9c82bc04eba22912b3b ] + +The rdev->pm.dpm.ps allocated by kcalloc should be freed in every +following error-handling path. However, in the error-handling of +rdev->pm.power_state[i].clock_info the rdev->pm.dpm.ps is not freed, +resulting in a memleak in this function. + +Fixes: d70229f70447 ("drm/radeon/kms: add dpm support for trinity asics") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/trinity_dpm.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c +index 08ea1c864cb2..ef1cc7bad20a 100644 +--- a/drivers/gpu/drm/radeon/trinity_dpm.c ++++ b/drivers/gpu/drm/radeon/trinity_dpm.c +@@ -1726,8 +1726,10 @@ static int trinity_parse_power_table(struct radeon_device *rdev) + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; +- if (!rdev->pm.power_state[i].clock_info) ++ if (!rdev->pm.power_state[i].clock_info) { ++ kfree(rdev->pm.dpm.ps); + return -EINVAL; ++ } + ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(rdev->pm.dpm.ps); +-- +2.43.0 + diff --git a/queue-6.7/drm-sched-fix-bounds-limiting-when-given-a-malformed.patch b/queue-6.7/drm-sched-fix-bounds-limiting-when-given-a-malformed.patch new file mode 100644 index 00000000000..3bf94d12bf7 --- /dev/null +++ b/queue-6.7/drm-sched-fix-bounds-limiting-when-given-a-malformed.patch @@ -0,0 +1,54 @@ +From 5aaefeb586de1c5c5ea57d728db17d758f78d096 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 23:58:53 -0500 +Subject: drm/sched: Fix bounds limiting when given a malformed entity +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Luben Tuikov + +[ Upstream commit 2bbe6ab2be53858507f11f99f856846d04765ae3 ] + +If we're given a malformed entity in drm_sched_entity_init()--shouldn't +happen, but we verify--with out-of-bounds priority value, we set it to an +allowed value. Fix the expression which sets this limit. + +Signed-off-by: Luben Tuikov +Fixes: 56e449603f0ac5 ("drm/sched: Convert the GPU scheduler to variable number of run-queues") +Link: https://patchwork.freedesktop.org/patch/msgid/20231123122422.167832-2-ltuikov89@gmail.com +Reviewed-by: Christian König +Link: https://lore.kernel.org/r/dbb91dbe-ef77-4d79-aaf9-2adb171c1d7a@amd.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/scheduler/sched_entity.c | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c +index 409e4256f6e7..0a7a7e4ad8d1 100644 +--- a/drivers/gpu/drm/scheduler/sched_entity.c ++++ b/drivers/gpu/drm/scheduler/sched_entity.c +@@ -81,12 +81,15 @@ int drm_sched_entity_init(struct drm_sched_entity *entity, + */ + pr_warn("%s: called with uninitialized scheduler\n", __func__); + } else if (num_sched_list) { +- /* The "priority" of an entity cannot exceed the number +- * of run-queues of a scheduler. ++ /* The "priority" of an entity cannot exceed the number of run-queues of a ++ * scheduler. Protect against num_rqs being 0, by converting to signed. + */ +- if (entity->priority >= sched_list[0]->num_rqs) +- entity->priority = max_t(u32, sched_list[0]->num_rqs, +- DRM_SCHED_PRIORITY_MIN); ++ if (entity->priority >= sched_list[0]->num_rqs) { ++ drm_err(sched_list[0], "entity with out-of-bounds priority:%u num_rqs:%u\n", ++ entity->priority, sched_list[0]->num_rqs); ++ entity->priority = max_t(s32, (s32) sched_list[0]->num_rqs - 1, ++ (s32) DRM_SCHED_PRIORITY_MIN); ++ } + entity->rq = sched_list[0]->sched_rq[entity->priority]; + } + +-- +2.43.0 + diff --git a/queue-6.7/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch b/queue-6.7/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch new file mode 100644 index 00000000000..e69f6441106 --- /dev/null +++ b/queue-6.7/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch @@ -0,0 +1,57 @@ +From 32be18e7352385916a43cf26b10f3666cde28e19 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:59 +0200 +Subject: drm/tidss: Check for K2G in in dispc_softreset() + +From: Tomi Valkeinen + +[ Upstream commit 151825150cf9c2e9fb90763d35b9dff3783628ac ] + +K2G doesn't have softreset feature. Instead of having every caller of +dispc_softreset() check for K2G, move the check into dispc_softreset(), +and make dispc_softreset() return 0 in case of K2G. + +Reviewed-by: Laurent Pinchart +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-6-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 9a29f5fa8453..2af623842cfb 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2707,6 +2707,10 @@ static int dispc_softreset(struct dispc_device *dispc) + u32 val; + int ret = 0; + ++ /* K2G display controller does not support soft reset */ ++ if (dispc->feat->subrev == DISPC_K2G) ++ return 0; ++ + /* Soft reset */ + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + /* Wait for reset to complete */ +@@ -2829,12 +2833,9 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + +- /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) { +- r = dispc_softreset(dispc); +- if (r) +- return r; +- } ++ r = dispc_softreset(dispc); ++ if (r) ++ return r; + + tidss->dispc = dispc; + +-- +2.43.0 + diff --git a/queue-6.7/drm-tidss-fix-dss-reset.patch b/queue-6.7/drm-tidss-fix-dss-reset.patch new file mode 100644 index 00000000000..116700a6a7b --- /dev/null +++ b/queue-6.7/drm-tidss-fix-dss-reset.patch @@ -0,0 +1,106 @@ +From 6d8bb1f06cee9f692d3284c9c7d1ffa85eda42a1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:38:01 +0200 +Subject: drm/tidss: Fix dss reset + +From: Tomi Valkeinen + +[ Upstream commit bc288a927815efcf9d7f4a54d4d89c5df478c635 ] + +The probe function calls dispc_softreset() before runtime PM is enabled +and without enabling any of the DSS clocks. This happens to work by +luck, and we need to make sure the DSS HW is active and the fclk is +enabled. + +To fix the above, add a new function, dispc_init_hw(), which does: + +- pm_runtime_set_active() +- clk_prepare_enable(fclk) +- dispc_softreset(). + +This ensures that the reset can be successfully accomplished. + +Note that we use pm_runtime_set_active(), not the normal +pm_runtime_get(). The reason for this is that at this point we haven't +enabled the runtime PM yet and also we don't want the normal resume +callback to be called: the dispc resume callback does some initial HW +setup, and it expects that the HW was off (no video ports are +streaming). If the bootloader has enabled the DSS and has set up a +boot time splash-screen, the DSS would be enabled and streaming which +might lead to issues with the normal resume callback. + +Fixes: c9b2d923befd ("drm/tidss: Soft Reset DISPC on startup") +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-8-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 45 ++++++++++++++++++++++++++++- + 1 file changed, 44 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 2af623842cfb..98efbaf3b0c2 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2724,6 +2724,49 @@ static int dispc_softreset(struct dispc_device *dispc) + return 0; + } + ++static int dispc_init_hw(struct dispc_device *dispc) ++{ ++ struct device *dev = dispc->dev; ++ int ret; ++ ++ ret = pm_runtime_set_active(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to active\n"); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(dispc->fclk); ++ if (ret) { ++ dev_err(dev, "Failed to enable DSS fclk\n"); ++ goto err_runtime_suspend; ++ } ++ ++ ret = dispc_softreset(dispc); ++ if (ret) ++ goto err_clk_disable; ++ ++ clk_disable_unprepare(dispc->fclk); ++ ret = pm_runtime_set_suspended(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to suspended\n"); ++ return ret; ++ } ++ ++ return 0; ++ ++err_clk_disable: ++ clk_disable_unprepare(dispc->fclk); ++ ++err_runtime_suspend: ++ ret = pm_runtime_set_suspended(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to suspended\n"); ++ return ret; ++ } ++ ++ return ret; ++} ++ + int dispc_init(struct tidss_device *tidss) + { + struct device *dev = tidss->dev; +@@ -2833,7 +2876,7 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + +- r = dispc_softreset(dispc); ++ r = dispc_init_hw(dispc); + if (r) + return r; + +-- +2.43.0 + diff --git a/queue-6.7/drm-tidss-move-reset-to-the-end-of-dispc_init.patch b/queue-6.7/drm-tidss-move-reset-to-the-end-of-dispc_init.patch new file mode 100644 index 00000000000..a356973a704 --- /dev/null +++ b/queue-6.7/drm-tidss-move-reset-to-the-end-of-dispc_init.patch @@ -0,0 +1,55 @@ +From 590329fe81c8bf87194c7dc10a4c234d9a510ab4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:57 +0200 +Subject: drm/tidss: Move reset to the end of dispc_init() + +From: Tomi Valkeinen + +[ Upstream commit 36d1e0852680aa038e2428d450673390111b165c ] + +We do a DSS reset in the middle of the dispc_init(). While that happens +to work now, we should really make sure that e..g the fclk, which is +acquired only later in the function, is enabled when doing a reset. This +will be handled in a later patch, but for now, let's move the +dispc_softreset() call to the end of dispc_init(), which is a sensible +place for it anyway. + +Reviewed-by: Laurent Pinchart +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-4-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 9d9dee7abaef..8d822372bf94 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2777,10 +2777,6 @@ int dispc_init(struct tidss_device *tidss) + return r; + } + +- /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) +- dispc_softreset(dispc); +- + for (i = 0; i < dispc->feat->num_vps; i++) { + u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; + u32 *gamma_table; +@@ -2829,6 +2825,10 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + ++ /* K2G display controller does not support soft reset */ ++ if (feat->subrev != DISPC_K2G) ++ dispc_softreset(dispc); ++ + tidss->dispc = dispc; + + return 0; +-- +2.43.0 + diff --git a/queue-6.7/drm-tidss-return-error-value-from-from-softreset.patch b/queue-6.7/drm-tidss-return-error-value-from-from-softreset.patch new file mode 100644 index 00000000000..d49ea94920d --- /dev/null +++ b/queue-6.7/drm-tidss-return-error-value-from-from-softreset.patch @@ -0,0 +1,66 @@ +From 8ff541e00b3b6b4fa2d8d313111b564ee1235f21 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:58 +0200 +Subject: drm/tidss: Return error value from from softreset + +From: Tomi Valkeinen + +[ Upstream commit aceafbb5035c4bfc75a321863ed1e393d644d2d2 ] + +Return an error value from dispc_softreset() so that the caller can +handle the errors. + +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-5-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 8d822372bf94..9a29f5fa8453 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2702,7 +2702,7 @@ static void dispc_init_errata(struct dispc_device *dispc) + } + } + +-static void dispc_softreset(struct dispc_device *dispc) ++static int dispc_softreset(struct dispc_device *dispc) + { + u32 val; + int ret = 0; +@@ -2712,8 +2712,12 @@ static void dispc_softreset(struct dispc_device *dispc) + /* Wait for reset to complete */ + ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, + val, val & 1, 100, 5000); +- if (ret) +- dev_warn(dispc->dev, "failed to reset dispc\n"); ++ if (ret) { ++ dev_err(dispc->dev, "failed to reset dispc\n"); ++ return ret; ++ } ++ ++ return 0; + } + + int dispc_init(struct tidss_device *tidss) +@@ -2826,8 +2830,11 @@ int dispc_init(struct tidss_device *tidss) + &dispc->memory_bandwidth_limit); + + /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) +- dispc_softreset(dispc); ++ if (feat->subrev != DISPC_K2G) { ++ r = dispc_softreset(dispc); ++ if (r) ++ return r; ++ } + + tidss->dispc = dispc; + +-- +2.43.0 + diff --git a/queue-6.7/drm-tilcdc-fix-irq-free-on-unload.patch b/queue-6.7/drm-tilcdc-fix-irq-free-on-unload.patch new file mode 100644 index 00000000000..7f47862009e --- /dev/null +++ b/queue-6.7/drm-tilcdc-fix-irq-free-on-unload.patch @@ -0,0 +1,40 @@ +From 104795336ed1674f11e1dbf05d7d261753608c69 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Sep 2023 10:12:50 +0300 +Subject: drm/tilcdc: Fix irq free on unload + +From: Tomi Valkeinen + +[ Upstream commit 38360bf96d816e175bc602c4ee76953cd303b71d ] + +The driver only frees the reserved irq if priv->irq_enabled is set to +true. However, the driver mistakenly sets priv->irq_enabled to false, +instead of true, in tilcdc_irq_install(), and thus the driver never +frees the irq, causing issues on loading the driver a second time. + +Fixes: b6366814fa77 ("drm/tilcdc: Convert to Linux IRQ interfaces") +Cc: Thomas Zimmermann +Reviewed-by: Aradhya Bhatia +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20230919-lcdc-v1-1-ba60da7421e1@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c +index 8ebd7134ee21..2f6eaac7f659 100644 +--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c ++++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c +@@ -138,7 +138,7 @@ static int tilcdc_irq_install(struct drm_device *dev, unsigned int irq) + if (ret) + return ret; + +- priv->irq_enabled = false; ++ priv->irq_enabled = true; + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.7/dt-bindings-arm-qcom-fix-html-link.patch b/queue-6.7/dt-bindings-arm-qcom-fix-html-link.patch new file mode 100644 index 00000000000..0742dfd1716 --- /dev/null +++ b/queue-6.7/dt-bindings-arm-qcom-fix-html-link.patch @@ -0,0 +1,43 @@ +From e684506613684e6aa0390b3bba6dbc6e60b448f7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 19:04:41 -0800 +Subject: dt-bindings: arm: qcom: Fix html link + +From: Stephen Boyd + +[ Upstream commit 3c3fcac8d3b1b0f242845c3b3c3263bd38b3b92f ] + +This link got broken by commit e790a4ce5290 ("arm: docs: Move Arm +documentation to Documentation/arch/") when the doc moved from arm/ to +arch/arm/. Fix the link so that it can continue to be followed. + +Fixes: e790a4ce5290 ("arm: docs: Move Arm documentation to Documentation/arch/") +Cc: Alexandre TORGUE +Cc: Yanteng Si +Cc: Jonathan Corbet +Reviewed-by: Douglas Anderson +Acked-by: Krzysztof Kozlowski +Signed-off-by: Stephen Boyd +Link: https://lore.kernel.org/r/20231129030443.2753833-1-swboyd@chromium.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + Documentation/devicetree/bindings/arm/qcom.yaml | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml +index 7f80f48a0954..8a6466d1fc4e 100644 +--- a/Documentation/devicetree/bindings/arm/qcom.yaml ++++ b/Documentation/devicetree/bindings/arm/qcom.yaml +@@ -138,7 +138,7 @@ description: | + There are many devices in the list below that run the standard ChromeOS + bootloader setup and use the open source depthcharge bootloader to boot the + OS. These devices do not use the scheme described above. For details, see: +- https://docs.kernel.org/arm/google/chromebook-boot-flow.html ++ https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html + + properties: + $nodename: +-- +2.43.0 + diff --git a/queue-6.7/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch b/queue-6.7/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch new file mode 100644 index 00000000000..fd018025221 --- /dev/null +++ b/queue-6.7/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch @@ -0,0 +1,125 @@ +From 6740dd5ce1ce64e23a9cd02d4e380bfdfdde94c1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 Oct 2023 16:33:42 +0800 +Subject: dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with + generic names + +From: Moudy Ho + +[ Upstream commit f5f185bf7c42f6ca885202fefc40fc871d08a722 ] + +The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names. +In addition, fix improper space indent in example. + +Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek MDP3 components") +Signed-off-by: Moudy Ho +Acked-by: Rob Herring +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + .../bindings/media/mediatek,mdp3-rdma.yaml | 29 +++++++++++-------- + .../bindings/media/mediatek,mdp3-wrot.yaml | 23 +++++++++------ + 2 files changed, 31 insertions(+), 21 deletions(-) + +diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +index 7032c7e15039..3e128733ef53 100644 +--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml ++++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +@@ -61,6 +61,9 @@ properties: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + ++ '#dma-cells': ++ const: 1 ++ + required: + - compatible + - reg +@@ -70,6 +73,7 @@ required: + - clocks + - iommus + - mboxes ++ - '#dma-cells' + + additionalProperties: false + +@@ -80,16 +84,17 @@ examples: + #include + #include + +- mdp3_rdma0: mdp3-rdma0@14001000 { +- compatible = "mediatek,mt8183-mdp3-rdma"; +- reg = <0x14001000 0x1000>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; +- mediatek,gce-events = , +- ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_MDP_RDMA0>, +- <&mmsys CLK_MM_MDP_RSZ1>; +- iommus = <&iommu>; +- mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, +- <&gce 21 CMDQ_THR_PRIO_LOWEST>; ++ dma-controller@14001000 { ++ compatible = "mediatek,mt8183-mdp3-rdma"; ++ reg = <0x14001000 0x1000>; ++ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; ++ mediatek,gce-events = , ++ ; ++ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; ++ clocks = <&mmsys CLK_MM_MDP_RDMA0>, ++ <&mmsys CLK_MM_MDP_RSZ1>; ++ iommus = <&iommu>; ++ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, ++ <&gce 21 CMDQ_THR_PRIO_LOWEST>; ++ #dma-cells = <1>; + }; +diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +index 0baa77198fa2..64ea98aa0592 100644 +--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml ++++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +@@ -50,6 +50,9 @@ properties: + iommus: + maxItems: 1 + ++ '#dma-cells': ++ const: 1 ++ + required: + - compatible + - reg +@@ -58,6 +61,7 @@ required: + - power-domains + - clocks + - iommus ++ - '#dma-cells' + + additionalProperties: false + +@@ -68,13 +72,14 @@ examples: + #include + #include + +- mdp3_wrot0: mdp3-wrot0@14005000 { +- compatible = "mediatek,mt8183-mdp3-wrot"; +- reg = <0x14005000 0x1000>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; +- mediatek,gce-events = , +- ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_MDP_WROT0>; +- iommus = <&iommu>; ++ dma-controller@14005000 { ++ compatible = "mediatek,mt8183-mdp3-wrot"; ++ reg = <0x14005000 0x1000>; ++ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; ++ mediatek,gce-events = , ++ ; ++ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; ++ clocks = <&mmsys CLK_MM_MDP_WROT0>; ++ iommus = <&iommu>; ++ #dma-cells = <1>; + }; +-- +2.43.0 + diff --git a/queue-6.7/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch b/queue-6.7/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch new file mode 100644 index 00000000000..17408f3d836 --- /dev/null +++ b/queue-6.7/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch @@ -0,0 +1,91 @@ +From 9169577542066e48cb6c4f6aaf427b4d3face201 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 23:19:53 +0100 +Subject: EDAC/thunderx: Fix possible out-of-bounds string access + +From: Arnd Bergmann + +[ Upstream commit 475c58e1a471e9b873e3e39958c64a2d278275c8 ] + +Enabling -Wstringop-overflow globally exposes a warning for a common bug +in the usage of strncat(): + + drivers/edac/thunderx_edac.c: In function 'thunderx_ocx_com_threaded_isr': + drivers/edac/thunderx_edac.c:1136:17: error: 'strncat' specified bound 1024 equals destination size [-Werror=stringop-overflow=] + 1136 | strncat(msg, other, OCX_MESSAGE_SIZE); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ... + 1145 | strncat(msg, other, OCX_MESSAGE_SIZE); + ... + 1150 | strncat(msg, other, OCX_MESSAGE_SIZE); + + ... + +Apparently the author of this driver expected strncat() to behave the +way that strlcat() does, which uses the size of the destination buffer +as its third argument rather than the length of the source buffer. The +result is that there is no check on the size of the allocated buffer. + +Change it to strlcat(). + + [ bp: Trim compiler output, fixup commit message. ] + +Fixes: 41003396f932 ("EDAC, thunderx: Add Cavium ThunderX EDAC driver") +Signed-off-by: Arnd Bergmann +Signed-off-by: Borislav Petkov (AMD) +Reviewed-by: Gustavo A. R. Silva +Link: https://lore.kernel.org/r/20231122222007.3199885-1-arnd@kernel.org +Signed-off-by: Sasha Levin +--- + drivers/edac/thunderx_edac.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c +index b9c5772da959..90d46e5c4ff0 100644 +--- a/drivers/edac/thunderx_edac.c ++++ b/drivers/edac/thunderx_edac.c +@@ -1133,7 +1133,7 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id) + decode_register(other, OCX_OTHER_SIZE, + ocx_com_errors, ctx->reg_com_int); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + for (lane = 0; lane < OCX_RX_LANES; lane++) + if (ctx->reg_com_int & BIT(lane)) { +@@ -1142,12 +1142,12 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id) + lane, ctx->reg_lane_int[lane], + lane, ctx->reg_lane_stat11[lane]); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + decode_register(other, OCX_OTHER_SIZE, + ocx_lane_errors, + ctx->reg_lane_int[lane]); +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + } + + if (ctx->reg_com_int & OCX_COM_INT_CE) +@@ -1217,7 +1217,7 @@ static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id) + decode_register(other, OCX_OTHER_SIZE, + ocx_com_link_errors, ctx->reg_com_link_int); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + if (ctx->reg_com_link_int & OCX_COM_LINK_INT_UE) + edac_device_handle_ue(ocx->edac_dev, 0, 0, msg); +@@ -1896,7 +1896,7 @@ static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id) + + decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx->reg_int); + +- strncat(msg, other, L2C_MESSAGE_SIZE); ++ strlcat(msg, other, L2C_MESSAGE_SIZE); + + if (ctx->reg_int & mask_ue) + edac_device_handle_ue(l2c->edac_dev, 0, 0, msg); +-- +2.43.0 + diff --git a/queue-6.7/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch b/queue-6.7/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch new file mode 100644 index 00000000000..e28ed547336 --- /dev/null +++ b/queue-6.7/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch @@ -0,0 +1,109 @@ +From 325899b97696736a695e7279f0e661357837c3ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Nov 2023 14:40:56 +0900 +Subject: efivarfs: force RO when remounting if SetVariable is not supported + +From: Ilias Apalodimas + +[ Upstream commit 0e8d2444168dd519fea501599d150e62718ed2fe ] + +If SetVariable at runtime is not supported by the firmware we never assign +a callback for that function. At the same time mount the efivarfs as +RO so no one can call that. However, we never check the permission flags +when someone remounts the filesystem as RW. As a result this leads to a +crash looking like this: + +$ mount -o remount,rw /sys/firmware/efi/efivars +$ efi-updatevar -f PK.auth PK + +[ 303.279166] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 +[ 303.280482] Mem abort info: +[ 303.280854] ESR = 0x0000000086000004 +[ 303.281338] EC = 0x21: IABT (current EL), IL = 32 bits +[ 303.282016] SET = 0, FnV = 0 +[ 303.282414] EA = 0, S1PTW = 0 +[ 303.282821] FSC = 0x04: level 0 translation fault +[ 303.283771] user pgtable: 4k pages, 48-bit VAs, pgdp=000000004258c000 +[ 303.284913] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000 +[ 303.286076] Internal error: Oops: 0000000086000004 [#1] PREEMPT SMP +[ 303.286936] Modules linked in: qrtr tpm_tis tpm_tis_core crct10dif_ce arm_smccc_trng rng_core drm fuse ip_tables x_tables ipv6 +[ 303.288586] CPU: 1 PID: 755 Comm: efi-updatevar Not tainted 6.3.0-rc1-00108-gc7d0c4695c68 #1 +[ 303.289748] Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2023.04-00627-g88336918701d 04/01/2023 +[ 303.291150] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ 303.292123] pc : 0x0 +[ 303.292443] lr : efivar_set_variable_locked+0x74/0xec +[ 303.293156] sp : ffff800008673c10 +[ 303.293619] x29: ffff800008673c10 x28: ffff0000037e8000 x27: 0000000000000000 +[ 303.294592] x26: 0000000000000800 x25: ffff000002467400 x24: 0000000000000027 +[ 303.295572] x23: ffffd49ea9832000 x22: ffff0000020c9800 x21: ffff000002467000 +[ 303.296566] x20: 0000000000000001 x19: 00000000000007fc x18: 0000000000000000 +[ 303.297531] x17: 0000000000000000 x16: 0000000000000000 x15: 0000aaaac807ab54 +[ 303.298495] x14: ed37489f673633c0 x13: 71c45c606de13f80 x12: 47464259e219acf4 +[ 303.299453] x11: ffff000002af7b01 x10: 0000000000000003 x9 : 0000000000000002 +[ 303.300431] x8 : 0000000000000010 x7 : ffffd49ea8973230 x6 : 0000000000a85201 +[ 303.301412] x5 : 0000000000000000 x4 : ffff0000020c9800 x3 : 00000000000007fc +[ 303.302370] x2 : 0000000000000027 x1 : ffff000002467400 x0 : ffff000002467000 +[ 303.303341] Call trace: +[ 303.303679] 0x0 +[ 303.303938] efivar_entry_set_get_size+0x98/0x16c +[ 303.304585] efivarfs_file_write+0xd0/0x1a4 +[ 303.305148] vfs_write+0xc4/0x2e4 +[ 303.305601] ksys_write+0x70/0x104 +[ 303.306073] __arm64_sys_write+0x1c/0x28 +[ 303.306622] invoke_syscall+0x48/0x114 +[ 303.307156] el0_svc_common.constprop.0+0x44/0xec +[ 303.307803] do_el0_svc+0x38/0x98 +[ 303.308268] el0_svc+0x2c/0x84 +[ 303.308702] el0t_64_sync_handler+0xf4/0x120 +[ 303.309293] el0t_64_sync+0x190/0x194 +[ 303.309794] Code: ???????? ???????? ???????? ???????? (????????) +[ 303.310612] ---[ end trace 0000000000000000 ]--- + +Fix this by adding a .reconfigure() function to the fs operations which +we can use to check the requested flags and deny anything that's not RO +if the firmware doesn't implement SetVariable at runtime. + +Fixes: f88814cc2578 ("efi/efivars: Expose RT service availability via efivars abstraction") +Signed-off-by: Ilias Apalodimas +Signed-off-by: Ard Biesheuvel +Signed-off-by: Sasha Levin +--- + fs/efivarfs/super.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/fs/efivarfs/super.c b/fs/efivarfs/super.c +index 77240953a92e..869537f1a550 100644 +--- a/fs/efivarfs/super.c ++++ b/fs/efivarfs/super.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + + #include "internal.h" + +@@ -333,9 +334,20 @@ static int efivarfs_get_tree(struct fs_context *fc) + return get_tree_single(fc, efivarfs_fill_super); + } + ++static int efivarfs_reconfigure(struct fs_context *fc) ++{ ++ if (!efivar_supports_writes() && !(fc->sb_flags & SB_RDONLY)) { ++ pr_err("Firmware does not support SetVariableRT. Can not remount with rw\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static const struct fs_context_operations efivarfs_context_ops = { + .get_tree = efivarfs_get_tree, + .parse_param = efivarfs_parse_param, ++ .reconfigure = efivarfs_reconfigure, + }; + + static int efivarfs_init_fs_context(struct fs_context *fc) +-- +2.43.0 + diff --git a/queue-6.7/efivarfs-free-s_fs_info-on-unmount.patch b/queue-6.7/efivarfs-free-s_fs_info-on-unmount.patch new file mode 100644 index 00000000000..29cd1a24628 --- /dev/null +++ b/queue-6.7/efivarfs-free-s_fs_info-on-unmount.patch @@ -0,0 +1,43 @@ +From f31ab66d48fd65ad7321c36db1c08dcae93a26d6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 17:39:28 +0100 +Subject: efivarfs: Free s_fs_info on unmount + +From: Ard Biesheuvel + +[ Upstream commit 547713d502f7b4b8efccd409cff84d731a23853b ] + +Now that we allocate a s_fs_info struct on fs context creation, we +should ensure that we free it again when the superblock goes away. + +Fixes: 5329aa5101f7 ("efivarfs: Add uid/gid mount options") +Signed-off-by: Ard Biesheuvel +Signed-off-by: Sasha Levin +--- + fs/efivarfs/super.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/fs/efivarfs/super.c b/fs/efivarfs/super.c +index 869537f1a550..edf29c15db77 100644 +--- a/fs/efivarfs/super.c ++++ b/fs/efivarfs/super.c +@@ -368,6 +368,8 @@ static int efivarfs_init_fs_context(struct fs_context *fc) + + static void efivarfs_kill_sb(struct super_block *sb) + { ++ struct efivarfs_fs_info *sfi = sb->s_fs_info; ++ + kill_litter_super(sb); + + if (!efivar_is_available()) +@@ -375,6 +377,7 @@ static void efivarfs_kill_sb(struct super_block *sb) + + /* Remove all entries and destroy */ + efivar_entry_iter(efivarfs_destroy, &efivarfs_list, NULL); ++ kfree(sfi); + } + + static struct file_system_type efivarfs_type = { +-- +2.43.0 + diff --git a/queue-6.7/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch b/queue-6.7/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch new file mode 100644 index 00000000000..71c23069bcc --- /dev/null +++ b/queue-6.7/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch @@ -0,0 +1,50 @@ +From b246611b226a3c3631e7c9d581fe137fbff55cbe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 02:04:31 +0800 +Subject: erofs: fix memory leak on short-lived bounced pages + +From: Gao Xiang + +[ Upstream commit 93d6fda7f926451a0fa1121b9558d75ca47e861e ] + +Both MicroLZMA and DEFLATE algorithms can use short-lived pages on +demand for the overlapped inplace I/O decompression. + +However, those short-lived pages are actually added to +`be->compressed_pages`. Thus, it should be checked instead of +`pcl->compressed_bvecs`. + +The LZ4 algorithm doesn't work like this, so it won't be impacted. + +Fixes: 67139e36d970 ("erofs: introduce `z_erofs_parse_in_bvecs'") +Reviewed-by: Yue Hu +Reviewed-by: Chao Yu +Signed-off-by: Gao Xiang +Link: https://lore.kernel.org/r/20231128180431.4116991-1-hsiangkao@linux.alibaba.com +Signed-off-by: Sasha Levin +--- + fs/erofs/zdata.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c +index a7e6847f6f8f..a33cd6757f98 100644 +--- a/fs/erofs/zdata.c ++++ b/fs/erofs/zdata.c +@@ -1309,12 +1309,11 @@ static int z_erofs_decompress_pcluster(struct z_erofs_decompress_backend *be, + put_page(page); + } else { + for (i = 0; i < pclusterpages; ++i) { +- page = pcl->compressed_bvecs[i].page; ++ /* consider shortlived pages added when decompressing */ ++ page = be->compressed_pages[i]; + + if (erofs_page_is_managed(sbi, page)) + continue; +- +- /* recycle all individual short-lived pages */ + (void)z_erofs_put_shortlivedpage(be->pagepool, page); + WRITE_ONCE(pcl->compressed_bvecs[i].page, NULL); + } +-- +2.43.0 + diff --git a/queue-6.7/f2fs-fix-to-avoid-dirent-corruption.patch b/queue-6.7/f2fs-fix-to-avoid-dirent-corruption.patch new file mode 100644 index 00000000000..356ced5719c --- /dev/null +++ b/queue-6.7/f2fs-fix-to-avoid-dirent-corruption.patch @@ -0,0 +1,60 @@ +From d214fcd0a21a651805fb8f7d69b04befdf76ee99 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 17:25:16 +0800 +Subject: f2fs: fix to avoid dirent corruption + +From: Chao Yu + +[ Upstream commit 53edb549565f55ccd0bdf43be3d66ce4c2d48b28 ] + +As Al reported in link[1]: + +f2fs_rename() +... + if (old_dir != new_dir && !whiteout) + f2fs_set_link(old_inode, old_dir_entry, + old_dir_page, new_dir); + else + f2fs_put_page(old_dir_page, 0); + +You want correct inumber in the ".." link. And cross-directory +rename does move the source to new parent, even if you'd been asked +to leave a whiteout in the old place. + +[1] https://lore.kernel.org/all/20231017055040.GN800259@ZenIV/ + +With below testcase, it may cause dirent corruption, due to it missed +to call f2fs_set_link() to update ".." link to new directory. +- mkdir -p dir/foo +- renameat2 -w dir/foo bar + +[ASSERT] (__chk_dots_dentries:1421) --> Bad inode number[0x4] for '..', parent parent ino is [0x3] +[FSCK] other corrupted bugs [Fail] + +Fixes: 7e01e7ad746b ("f2fs: support RENAME_WHITEOUT") +Cc: Jan Kara +Reported-by: Al Viro +Signed-off-by: Chao Yu +Reviewed-by: Jan Kara +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/namei.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c +index d0053b0284d8..7f71bae2c83b 100644 +--- a/fs/f2fs/namei.c ++++ b/fs/f2fs/namei.c +@@ -1106,7 +1106,7 @@ static int f2fs_rename(struct mnt_idmap *idmap, struct inode *old_dir, + } + + if (old_dir_entry) { +- if (old_dir != new_dir && !whiteout) ++ if (old_dir != new_dir) + f2fs_set_link(old_inode, old_dir_entry, + old_dir_page, new_dir); + else +-- +2.43.0 + diff --git a/queue-6.7/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch b/queue-6.7/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch new file mode 100644 index 00000000000..1d69533cccd --- /dev/null +++ b/queue-6.7/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch @@ -0,0 +1,40 @@ +From 059dbfdb79e4b812d2310929ae60caffc3333e64 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:44 +0800 +Subject: f2fs: fix to check compress file in f2fs_move_file_range() + +From: Chao Yu + +[ Upstream commit fb9b65340c818875ea86464faf3c744bdce0055c ] + +f2fs_move_file_range() doesn't support migrating compressed cluster +data, let's add the missing check condition and return -EOPNOTSUPP +for the case until we support it. + +Fixes: 4c8ff7095bef ("f2fs: support data compression") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/file.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c +index e50363583f01..37917c634e22 100644 +--- a/fs/f2fs/file.c ++++ b/fs/f2fs/file.c +@@ -2818,6 +2818,11 @@ static int f2fs_move_file_range(struct file *file_in, loff_t pos_in, + goto out; + } + ++ if (f2fs_compressed_file(src) || f2fs_compressed_file(dst)) { ++ ret = -EOPNOTSUPP; ++ goto out_unlock; ++ } ++ + ret = -EINVAL; + if (pos_in + len > src->i_size || pos_in + len < pos_in) + goto out_unlock; +-- +2.43.0 + diff --git a/queue-6.7/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch b/queue-6.7/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch new file mode 100644 index 00000000000..e0f15ee4343 --- /dev/null +++ b/queue-6.7/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch @@ -0,0 +1,70 @@ +From 0153faa81abd7d592f463b9308ac5ea2a0e02d2d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Dec 2023 10:15:27 +0800 +Subject: f2fs: fix to check return value of f2fs_recover_xattr_data + +From: Zhiguo Niu + +[ Upstream commit 86d7d57a3f096c8349b32a0cd5f6f314e4416a6d ] + +Should check return value of f2fs_recover_xattr_data in +__f2fs_setxattr rather than doing invalid retry if error happen. + +Also just do set_page_dirty in f2fs_recover_xattr_data when +page is changed really. + +Fixes: 50a472bbc79f ("f2fs: do not return EFSCORRUPTED, but try to run online repair") +Signed-off-by: Zhiguo Niu +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/node.c | 6 +++--- + fs/f2fs/xattr.c | 11 +++++++---- + 2 files changed, 10 insertions(+), 7 deletions(-) + +diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c +index 6c7f6a649d27..9b546fd21010 100644 +--- a/fs/f2fs/node.c ++++ b/fs/f2fs/node.c +@@ -2751,11 +2751,11 @@ int f2fs_recover_xattr_data(struct inode *inode, struct page *page) + f2fs_update_inode_page(inode); + + /* 3: update and set xattr node page dirty */ +- if (page) ++ if (page) { + memcpy(F2FS_NODE(xpage), F2FS_NODE(page), + VALID_XATTR_BLOCK_SIZE); +- +- set_page_dirty(xpage); ++ set_page_dirty(xpage); ++ } + f2fs_put_page(xpage, 1); + + return 0; +diff --git a/fs/f2fs/xattr.c b/fs/f2fs/xattr.c +index a8fc2cac6879..f290fe9327c4 100644 +--- a/fs/f2fs/xattr.c ++++ b/fs/f2fs/xattr.c +@@ -660,11 +660,14 @@ static int __f2fs_setxattr(struct inode *inode, int index, + here = __find_xattr(base_addr, last_base_addr, NULL, index, len, name); + if (!here) { + if (!F2FS_I(inode)->i_xattr_nid) { ++ error = f2fs_recover_xattr_data(inode, NULL); + f2fs_notice(F2FS_I_SB(inode), +- "recover xattr in inode (%lu)", inode->i_ino); +- f2fs_recover_xattr_data(inode, NULL); +- kfree(base_addr); +- goto retry; ++ "recover xattr in inode (%lu), error(%d)", ++ inode->i_ino, error); ++ if (!error) { ++ kfree(base_addr); ++ goto retry; ++ } + } + f2fs_err(F2FS_I_SB(inode), "set inode (%lu) has corrupted xattr", + inode->i_ino); +-- +2.43.0 + diff --git a/queue-6.7/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch b/queue-6.7/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch new file mode 100644 index 00000000000..286de1eec6d --- /dev/null +++ b/queue-6.7/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch @@ -0,0 +1,36 @@ +From 0b4d95469ccd93658c8dd05619b3581030b0f53c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:47 +0800 +Subject: f2fs: fix to update iostat correctly in f2fs_filemap_fault() + +From: Chao Yu + +[ Upstream commit bb34cc6ca87ff78f9fb5913d7619dc1389554da6 ] + +In f2fs_filemap_fault(), it fixes to update iostat info only if +VM_FAULT_LOCKED is tagged in return value of filemap_fault(). + +Fixes: 8b83ac81f428 ("f2fs: support read iostat") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/file.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c +index 37917c634e22..8912511980ae 100644 +--- a/fs/f2fs/file.c ++++ b/fs/f2fs/file.c +@@ -42,7 +42,7 @@ static vm_fault_t f2fs_filemap_fault(struct vm_fault *vmf) + vm_fault_t ret; + + ret = filemap_fault(vmf); +- if (!ret) ++ if (ret & VM_FAULT_LOCKED) + f2fs_update_iostat(F2FS_I_SB(inode), inode, + APP_MAPPED_READ_IO, F2FS_BLKSIZE); + +-- +2.43.0 + diff --git a/queue-6.7/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch b/queue-6.7/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch new file mode 100644 index 00000000000..9efe4a9f6d1 --- /dev/null +++ b/queue-6.7/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch @@ -0,0 +1,69 @@ +From 8b995703018e2639494f2ae345afc25e259dee70 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:43 +0800 +Subject: f2fs: fix to wait on block writeback for post_read case + +From: Chao Yu + +[ Upstream commit 55fdc1c24a1d6229fe0ecf31335fb9a2eceaaa00 ] + +If inode is compressed, but not encrypted, it missed to call +f2fs_wait_on_block_writeback() to wait for GCed page writeback +in IPU write path. + +Thread A GC-Thread + - f2fs_gc + - do_garbage_collect + - gc_data_segment + - move_data_block + - f2fs_submit_page_write + migrate normal cluster's block via + meta_inode's page cache +- f2fs_write_single_data_page + - f2fs_do_write_data_page + - f2fs_inplace_write_data + - f2fs_submit_page_bio + +IRQ +- f2fs_read_end_io + IRQ + old data overrides new data due to + out-of-order GC and common IO. + - f2fs_read_end_io + +Fixes: 4c8ff7095bef ("f2fs: support data compression") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/data.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c +index 4e42b5f24deb..bc3f05d43b62 100644 +--- a/fs/f2fs/data.c ++++ b/fs/f2fs/data.c +@@ -2566,9 +2566,6 @@ int f2fs_encrypt_one_page(struct f2fs_io_info *fio) + + page = fio->compressed_page ? fio->compressed_page : fio->page; + +- /* wait for GCed page writeback via META_MAPPING */ +- f2fs_wait_on_block_writeback(inode, fio->old_blkaddr); +- + if (fscrypt_inode_uses_inline_crypto(inode)) + return 0; + +@@ -2755,6 +2752,10 @@ int f2fs_do_write_data_page(struct f2fs_io_info *fio) + goto out_writepage; + } + ++ /* wait for GCed page writeback via META_MAPPING */ ++ if (fio->post_read) ++ f2fs_wait_on_block_writeback(inode, fio->old_blkaddr); ++ + /* + * If current allocation needs SSR, + * it had better in-place writes for updated data. +-- +2.43.0 + diff --git a/queue-6.7/f2fs-restrict-max-filesize-for-16k-f2fs.patch b/queue-6.7/f2fs-restrict-max-filesize-for-16k-f2fs.patch new file mode 100644 index 00000000000..e790eff539a --- /dev/null +++ b/queue-6.7/f2fs-restrict-max-filesize-for-16k-f2fs.patch @@ -0,0 +1,46 @@ +From 04968e4208cf783ddb86f30c8bf56be3088bba20 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 18:38:01 -0800 +Subject: f2fs: Restrict max filesize for 16K f2fs + +From: Daniel Rosenberg + +[ Upstream commit a6a010f5def544af3efcfe21683905a712b60536 ] + +Blocks are tracked by u32, so the max permitted filesize is +(U32_MAX + 1) * BLOCK_SIZE. Additionally, in order to support crypto +data unit sizes of 4K with a 16K block with IV_INO_LBLK_{32,64}, we must +further restrict max filesize to (U32_MAX + 1) * 4096. This does not +affect 4K blocksize f2fs as the natural limit for files are well below +that. + +Fixes: d7e9a9037de2 ("f2fs: Support Block Size == Page Size") +Signed-off-by: Daniel Rosenberg +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/super.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c +index 033af907c3b1..5dfbc6b4c0ac 100644 +--- a/fs/f2fs/super.c ++++ b/fs/f2fs/super.c +@@ -3364,6 +3364,14 @@ loff_t max_file_blocks(struct inode *inode) + leaf_count *= NIDS_PER_BLOCK; + result += leaf_count; + ++ /* ++ * For compatibility with FSCRYPT_POLICY_FLAG_IV_INO_LBLK_{64,32} with ++ * a 4K crypto data unit, we must restrict the max filesize to what can ++ * fit within U32_MAX + 1 data units. ++ */ ++ ++ result = min(result, (((loff_t)U32_MAX + 1) * 4096) >> F2FS_BLKSIZE_BITS); ++ + return result; + } + +-- +2.43.0 + diff --git a/queue-6.7/fbdev-imxfb-fix-left-margin-setting.patch b/queue-6.7/fbdev-imxfb-fix-left-margin-setting.patch new file mode 100644 index 00000000000..35e483382c9 --- /dev/null +++ b/queue-6.7/fbdev-imxfb-fix-left-margin-setting.patch @@ -0,0 +1,121 @@ +From fc1649f7d5c25c262f859529749d0612cdfeac82 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 11:41:50 +0100 +Subject: fbdev: imxfb: fix left margin setting + +From: Dario Binacchi + +[ Upstream commit 5758844105f7dd9a0a04990cd92499a1a593dd36 ] + +The previous setting did not take into account the CSTN mode. +For the H_WAIT_2 bitfield (bits 0-7) of the LCDC Horizontal Configuration +Register (LCDCR), the IMX25RM manual states that: + +In TFT mode, it specifies the number of SCLK periods between the end of +HSYNC and the beginning of OE signal, and the total delay time equals +(H_WAIT_2 + 3) of SCLK periods. +In CSTN mode, it specifies the number of SCLK periods between the end of +HSYNC and the first display data in each line, and the total delay time +equals (H_WAIT_2 + 2) of SCLK periods. + +The patch handles both cases. + +Fixes: 4e47382fbca9 ("fbdev: imxfb: warn about invalid left/right margin") +Fixes: 7e8549bcee00 ("imxfb: Fix margin settings") +Signed-off-by: Dario Binacchi +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/video/fbdev/imxfb.c | 27 +++++++++++++++++++++++++-- + 1 file changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c +index 84201c9608d3..7042a43b81d8 100644 +--- a/drivers/video/fbdev/imxfb.c ++++ b/drivers/video/fbdev/imxfb.c +@@ -42,6 +42,7 @@ + #include