From d52062d9d56623dd235f620e93dcac879c7660b5 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 19 Dec 2019 10:32:05 +0100 Subject: [PATCH] 4.4-stable patches added patches: pci-fix-intel-acs-quirk-updcr-register-address.patch pci-msi-fix-incorrect-msi-x-masking-on-resume.patch --- ...tel-acs-quirk-updcr-register-address.patch | 46 ++++++++++++++ ...ix-incorrect-msi-x-masking-on-resume.patch | 63 +++++++++++++++++++ queue-4.4/series | 2 + 3 files changed, 111 insertions(+) create mode 100644 queue-4.4/pci-fix-intel-acs-quirk-updcr-register-address.patch create mode 100644 queue-4.4/pci-msi-fix-incorrect-msi-x-masking-on-resume.patch diff --git a/queue-4.4/pci-fix-intel-acs-quirk-updcr-register-address.patch b/queue-4.4/pci-fix-intel-acs-quirk-updcr-register-address.patch new file mode 100644 index 00000000000..62e3d42a38c --- /dev/null +++ b/queue-4.4/pci-fix-intel-acs-quirk-updcr-register-address.patch @@ -0,0 +1,46 @@ +From d8558ac8c93d429d65d7490b512a3a67e559d0d4 Mon Sep 17 00:00:00 2001 +From: Steffen Liebergeld +Date: Wed, 18 Sep 2019 15:16:52 +0200 +Subject: PCI: Fix Intel ACS quirk UPDCR register address + +From: Steffen Liebergeld + +commit d8558ac8c93d429d65d7490b512a3a67e559d0d4 upstream. + +According to documentation [0] the correct offset for the Upstream Peer +Decode Configuration Register (UPDCR) is 0x1014. It was previously defined +as 0x1114. + +d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") +intended to enforce isolation between PCI devices allowing them to be put +into separate IOMMU groups. Due to the wrong register offset the intended +isolation was not fully enforced. This is fixed with this patch. + +Please note that I did not test this patch because I have no hardware that +implements this register. + +[0] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf (page 325) +Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") +Link: https://lore.kernel.org/r/7a3505df-79ba-8a28-464c-88b83eefffa6@kernkonzept.com +Signed-off-by: Steffen Liebergeld +Signed-off-by: Bjorn Helgaas +Reviewed-by: Andrew Murray +Acked-by: Ashok Raj +Cc: stable@vger.kernel.org # v3.15+ +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/quirks.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -4038,7 +4038,7 @@ int pci_dev_specific_acs_enabled(struct + #define INTEL_BSPR_REG_BPPD (1 << 9) + + /* Upstream Peer Decode Configuration Register */ +-#define INTEL_UPDCR_REG 0x1114 ++#define INTEL_UPDCR_REG 0x1014 + /* 5:0 Peer Decode Enable bits */ + #define INTEL_UPDCR_REG_MASK 0x3f + diff --git a/queue-4.4/pci-msi-fix-incorrect-msi-x-masking-on-resume.patch b/queue-4.4/pci-msi-fix-incorrect-msi-x-masking-on-resume.patch new file mode 100644 index 00000000000..aa0e1bf84cb --- /dev/null +++ b/queue-4.4/pci-msi-fix-incorrect-msi-x-masking-on-resume.patch @@ -0,0 +1,63 @@ +From e045fa29e89383c717e308609edd19d2fd29e1be Mon Sep 17 00:00:00 2001 +From: Jian-Hong Pan +Date: Tue, 8 Oct 2019 11:42:39 +0800 +Subject: PCI/MSI: Fix incorrect MSI-X masking on resume + +From: Jian-Hong Pan + +commit e045fa29e89383c717e308609edd19d2fd29e1be upstream. + +When a driver enables MSI-X, msix_program_entries() reads the MSI-X Vector +Control register for each vector and saves it in desc->masked. Each +register is 32 bits and bit 0 is the actual Mask bit. + +When we restored these registers during resume, we previously set the Mask +bit if *any* bit in desc->masked was set instead of when the Mask bit +itself was set: + + pci_restore_state + pci_restore_msi_state + __pci_restore_msix_state + for_each_pci_msi_entry + msix_mask_irq(entry, entry->masked) <-- entire u32 word + __pci_msix_desc_mask_irq(desc, flag) + mask_bits = desc->masked & ~PCI_MSIX_ENTRY_CTRL_MASKBIT + if (flag) <-- testing entire u32, not just bit 0 + mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT + writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL) + +This means that after resume, MSI-X vectors were masked when they shouldn't +be, which leads to timeouts like this: + + nvme nvme0: I/O 978 QID 3 timeout, completion polled + +On resume, set the Mask bit only when the saved Mask bit from suspend was +set. + +This should remove the need for 19ea025e1d28 ("nvme: Add quirk for Kingston +NVME SSD running FW E8FK11.T"). + +[bhelgaas: commit log, move fix to __pci_msix_desc_mask_irq()] +Link: https://bugzilla.kernel.org/show_bug.cgi?id=204887 +Link: https://lore.kernel.org/r/20191008034238.2503-1-jian-hong@endlessm.com +Fixes: f2440d9acbe8 ("PCI MSI: Refactor interrupt masking code") +Signed-off-by: Jian-Hong Pan +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/msi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/msi.c ++++ b/drivers/pci/msi.c +@@ -224,7 +224,7 @@ u32 __pci_msix_desc_mask_irq(struct msi_ + return 0; + + mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; +- if (flag) ++ if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT) + mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; + writel(mask_bits, desc->mask_base + offset); + diff --git a/queue-4.4/series b/queue-4.4/series index 9d126d56c12..ce00021836b 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -148,3 +148,5 @@ tcp-fix-rejected-syncookies-due-to-stale-timestamps.patch tcp-tighten-acceptance-of-acks-not-matching-a-child-socket.patch tcp-protect-accesses-to-.ts_recent_stamp-with-read-write-_once.patch net-ethernet-ti-cpsw-fix-extra-rx-interrupt.patch +pci-fix-intel-acs-quirk-updcr-register-address.patch +pci-msi-fix-incorrect-msi-x-masking-on-resume.patch -- 2.47.3