From d9005d7a709dee8dabdb3060c8430135c6b92242 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 6 Feb 2025 15:45:00 +0100 Subject: [PATCH] drop a phy samsung patch that broke the build --- ...l-samsung-hdmi-clean-up-fld_tg_code-.patch | 86 --- ...fix-64-by-32-division-cocci-warnings.patch | 39 - ...l-samsung-hdmi-replace-register-defi.patch | 235 ------ ...l-samsung-hdmi-simplify-reg21_pms_s_.patch | 90 --- ...l-samsung-hdmi-support-dynamic-integ.patch | 666 ------------------ queue-6.12/series | 5 - ...l-samsung-hdmi-clean-up-fld_tg_code-.patch | 86 --- queue-6.13/series | 1 - 8 files changed, 1208 deletions(-) delete mode 100644 queue-6.12/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch delete mode 100644 queue-6.12/phy-freescale-fsl-samsung-hdmi-fix-64-by-32-division-cocci-warnings.patch delete mode 100644 queue-6.12/phy-freescale-fsl-samsung-hdmi-replace-register-defi.patch delete mode 100644 queue-6.12/phy-freescale-fsl-samsung-hdmi-simplify-reg21_pms_s_.patch delete mode 100644 queue-6.12/phy-freescale-fsl-samsung-hdmi-support-dynamic-integ.patch delete mode 100644 queue-6.13/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch diff --git a/queue-6.12/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch b/queue-6.12/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch deleted file mode 100644 index cd86875c65..0000000000 --- a/queue-6.12/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 1cb49b3434942402a93ff0673e84efad996194f5 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 26 Oct 2024 08:19:59 -0500 -Subject: phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation - -From: Adam Ford - -[ Upstream commit d567679f2b6a8bcea20589bbea6488c0236886cd ] - -Currently, the calcuation for fld_tg_code is based on a lookup table, -but there are gaps in the lookup table, and frequencies in these -gaps may not properly use the correct divider. Based on the description -of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz, -so directly calcuate the value of FLD_CK_DIV from pixclk. -This allow for proper calcuation of any pixel clock and eliminates a -few gaps in the LUT. - -Since the value of the int_pllclk is in Hz, do the fixed-point -math in Hz to achieve a more accurate value and reduces the complexity -of the caluation to 24MHz * (256 / int_pllclk). - -Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY") -Signed-off-by: Adam Ford -Reviewed-by: Frieder Schrempf -Link: https://lore.kernel.org/r/20241026132014.73050-3-aford173@gmail.com -Signed-off-by: Vinod Koul -Signed-off-by: Sasha Levin ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 32 +++++++------------- - 1 file changed, 11 insertions(+), 21 deletions(-) - -diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -index 029de69fbeaf4..6801a09c86a77 100644 ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -388,25 +388,17 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - { - u32 pclk = cfg->pixclk; - u32 fld_tg_code; -- u32 pclk_khz; -- u8 div = 1; -- -- switch (cfg->pixclk) { -- case 22250000 ... 47500000: -- div = 1; -- break; -- case 50349650 ... 99000000: -- div = 2; -- break; -- case 100699300 ... 198000000: -- div = 4; -- break; -- case 205000000 ... 297000000: -- div = 8; -- break; -+ u32 int_pllclk; -+ u8 div; -+ -+ /* Find int_pllclk speed */ -+ for (div = 0; div < 4; div++) { -+ int_pllclk = pclk / (1 << div); -+ if (int_pllclk < (50 * MHZ)) -+ break; - } - -- writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)); -+ writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); - - /* - * Calculation for the frequency lock detector target code (fld_tg_code) -@@ -419,10 +411,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - * settings rounding up always too. TODO: Check if that is - * correct. - */ -- pclk /= div; -- pclk_khz = pclk / 1000; -- fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24; -- fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000); -+ -+ fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk); - - /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ - writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), --- -2.39.5 - diff --git a/queue-6.12/phy-freescale-fsl-samsung-hdmi-fix-64-by-32-division-cocci-warnings.patch b/queue-6.12/phy-freescale-fsl-samsung-hdmi-fix-64-by-32-division-cocci-warnings.patch deleted file mode 100644 index f012754c6f..0000000000 --- a/queue-6.12/phy-freescale-fsl-samsung-hdmi-fix-64-by-32-division-cocci-warnings.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 739214dd1c209e34323814fb815fb17cccb9f95b Mon Sep 17 00:00:00 2001 -From: Adam Ford -Date: Sun, 15 Dec 2024 16:05:55 -0600 -Subject: phy: freescale: fsl-samsung-hdmi: Fix 64-by-32 division cocci warnings - -From: Adam Ford - -commit 739214dd1c209e34323814fb815fb17cccb9f95b upstream. - -The Kernel test robot returns the following warning: - do_div() does a 64-by-32 division, please consider using div64_ul instead. - -To prevent the 64-by-32 divsion, consolidate both the multiplication -and the do_div into one line which explicitly uses u64 sizes. - -Fixes: 1951dbb41d1d ("phy: freescale: fsl-samsung-hdmi: Support dynamic integer") -Signed-off-by: Adam Ford -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202412091243.fSObwwPi-lkp@intel.com/ -Signed-off-by: Greg Kroah-Hartman - -Link: https://lore.kernel.org/r/20241215220555.99113-1-aford173@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -471,8 +471,7 @@ static unsigned long fsl_samsung_hdmi_ph - * Fvco = (M * f_ref) / P, - * where f_ref is 24MHz. - */ -- tmp = (u64)_m * 24 * MHZ; -- do_div(tmp, _p); -+ tmp = div64_ul((u64)_m * 24 * MHZ, _p); - if (tmp < 750 * MHZ || - tmp > 3000 * MHZ) - continue; diff --git a/queue-6.12/phy-freescale-fsl-samsung-hdmi-replace-register-defi.patch b/queue-6.12/phy-freescale-fsl-samsung-hdmi-replace-register-defi.patch deleted file mode 100644 index d6cbd638ba..0000000000 --- a/queue-6.12/phy-freescale-fsl-samsung-hdmi-replace-register-defi.patch +++ /dev/null @@ -1,235 +0,0 @@ -From 19dfeda621a2d96990c81bf73dd7541cd2491ed8 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 14 Sep 2024 06:27:45 -0500 -Subject: phy: freescale: fsl-samsung-hdmi: Replace register defines with macro - -From: Adam Ford - -[ Upstream commit 4a5a9e2577d61a4ee3e9788e0c2b0c1cbc5ba7b3 ] - -There are 47 registers defined as PHY_REG_xx were xx goes from 00 to -47. Simplify this by replacing them all with a macro which is passed -the register number to return the proper register offset. - -Signed-off-by: Adam Ford -Reviewed-by: Marco Felsch -Reviewed-by: Frieder Schrempf -Tested-by: Frieder Schrempf -Reviewed-by: Dominique Martinet -Tested-by: Dominique Martinet -Link: https://lore.kernel.org/r/20240914112816.520224-2-aford173@gmail.com -Signed-off-by: Vinod Koul -Stable-dep-of: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") -Signed-off-by: Sasha Levin ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 133 ++++++------------- - 1 file changed, 43 insertions(+), 90 deletions(-) - -diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -index 9048cdc760c21..acea7008aefc5 100644 ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -14,76 +14,29 @@ - #include - #include - --#define PHY_REG_00 0x00 --#define PHY_REG_01 0x04 --#define PHY_REG_02 0x08 --#define PHY_REG_08 0x20 --#define PHY_REG_09 0x24 --#define PHY_REG_10 0x28 --#define PHY_REG_11 0x2c -- --#define PHY_REG_12 0x30 --#define REG12_CK_DIV_MASK GENMASK(5, 4) -- --#define PHY_REG_13 0x34 --#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) -- --#define PHY_REG_14 0x38 --#define REG14_TOL_MASK GENMASK(7, 4) --#define REG14_RP_CODE_MASK GENMASK(3, 1) --#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) -- --#define PHY_REG_15 0x3c --#define PHY_REG_16 0x40 --#define PHY_REG_17 0x44 --#define PHY_REG_18 0x48 --#define PHY_REG_19 0x4c --#define PHY_REG_20 0x50 -- --#define PHY_REG_21 0x54 --#define REG21_SEL_TX_CK_INV BIT(7) --#define REG21_PMS_S_MASK GENMASK(3, 0) -- --#define PHY_REG_22 0x58 --#define PHY_REG_23 0x5c --#define PHY_REG_24 0x60 --#define PHY_REG_25 0x64 --#define PHY_REG_26 0x68 --#define PHY_REG_27 0x6c --#define PHY_REG_28 0x70 --#define PHY_REG_29 0x74 --#define PHY_REG_30 0x78 --#define PHY_REG_31 0x7c --#define PHY_REG_32 0x80 -+#define PHY_REG(reg) (reg * 4) - -+#define REG12_CK_DIV_MASK GENMASK(5, 4) -+ -+#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) -+ -+#define REG14_TOL_MASK GENMASK(7, 4) -+#define REG14_RP_CODE_MASK GENMASK(3, 1) -+#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) -+ -+#define REG21_SEL_TX_CK_INV BIT(7) -+#define REG21_PMS_S_MASK GENMASK(3, 0) - /* - * REG33 does not match the ref manual. According to Sandor Yu from NXP, - * "There is a doc issue on the i.MX8MP latest RM" - * REG33 is being used per guidance from Sandor - */ -+#define REG33_MODE_SET_DONE BIT(7) -+#define REG33_FIX_DA BIT(1) - --#define PHY_REG_33 0x84 --#define REG33_MODE_SET_DONE BIT(7) --#define REG33_FIX_DA BIT(1) -- --#define PHY_REG_34 0x88 --#define REG34_PHY_READY BIT(7) --#define REG34_PLL_LOCK BIT(6) --#define REG34_PHY_CLK_READY BIT(5) -- --#define PHY_REG_35 0x8c --#define PHY_REG_36 0x90 --#define PHY_REG_37 0x94 --#define PHY_REG_38 0x98 --#define PHY_REG_39 0x9c --#define PHY_REG_40 0xa0 --#define PHY_REG_41 0xa4 --#define PHY_REG_42 0xa8 --#define PHY_REG_43 0xac --#define PHY_REG_44 0xb0 --#define PHY_REG_45 0xb4 --#define PHY_REG_46 0xb8 --#define PHY_REG_47 0xbc -+#define REG34_PHY_READY BIT(7) -+#define REG34_PLL_LOCK BIT(6) -+#define REG34_PHY_CLK_READY BIT(5) - - #define PHY_PLL_DIV_REGS_NUM 6 - -@@ -369,29 +322,29 @@ struct reg_settings { - }; - - static const struct reg_settings common_phy_cfg[] = { -- { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 }, -- { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 }, -- { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 }, -+ { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, -+ { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, -+ { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, - /* REG12 pixclk specific */ - /* REG13 pixclk specific */ - /* REG14 pixclk specific */ -- { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c }, -- { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 }, -- { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 }, -+ { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c }, -+ { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 }, -+ { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 }, - /* REG21 pixclk specific */ -- { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 }, -- { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f }, -- { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 }, -- { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 }, -- { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 }, -- { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 }, -- { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 }, -- { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 }, -- { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 }, -- { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 }, -- { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f }, -- { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 }, -- { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 } -+ { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 }, -+ { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f }, -+ { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 }, -+ { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 }, -+ { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 }, -+ { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 }, -+ { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 }, -+ { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 }, -+ { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 }, -+ { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 }, -+ { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f }, -+ { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 }, -+ { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 } - }; - - struct fsl_samsung_hdmi_phy { -@@ -442,7 +395,7 @@ fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, - } - - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), -- phy->regs + PHY_REG_21); -+ phy->regs + PHY_REG(21)); - } - - static void -@@ -469,7 +422,7 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - break; - } - -- writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); -+ writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)); - - /* - * Calculation for the frequency lock detector target code (fld_tg_code) -@@ -489,11 +442,11 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - - /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ - writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), -- phy->regs + PHY_REG_13); -+ phy->regs + PHY_REG(13)); - writeb(FIELD_PREP(REG14_TOL_MASK, 2) | - FIELD_PREP(REG14_RP_CODE_MASK, 2) | - FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), -- phy->regs + PHY_REG_14); -+ phy->regs + PHY_REG(14)); - } - - static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, -@@ -503,7 +456,7 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, - u8 val; - - /* HDMI PHY init */ -- writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); -+ writeb(REG33_FIX_DA, phy->regs + PHY_REG(33)); - - /* common PHY registers */ - for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) -@@ -511,14 +464,14 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, - - /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ - for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) -- writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4); -+ writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); - - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); - -- writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33); -+ writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); - -- ret = readb_poll_timeout(phy->regs + PHY_REG_34, val, -+ ret = readb_poll_timeout(phy->regs + PHY_REG(34), val, - val & REG34_PLL_LOCK, 50, 20000); - if (ret) - dev_err(phy->dev, "PLL failed to lock\n"); --- -2.39.5 - diff --git a/queue-6.12/phy-freescale-fsl-samsung-hdmi-simplify-reg21_pms_s_.patch b/queue-6.12/phy-freescale-fsl-samsung-hdmi-simplify-reg21_pms_s_.patch deleted file mode 100644 index 8bb3366e4b..0000000000 --- a/queue-6.12/phy-freescale-fsl-samsung-hdmi-simplify-reg21_pms_s_.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 568cf4e942f5ca79973de9e877e675c334a6683d Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 14 Sep 2024 06:27:46 -0500 -Subject: phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup - -From: Adam Ford - -[ Upstream commit 375ee44adb3640099508c5c0c01d86f0bdb16e97 ] - -The value of 'S' is writen to two places, PHY_REG3[7:4] and -PHY_REG21[3:0]. There is a lookup table which contains -the value of PHY_REG3. Rather than using a switch statement -based on the pixel clock to search for the value of 'S' again, -just shift the contents of PHY_REG3[7:4] >> 4 and place the value -in PHY_REG21[3:0]. Doing this can eliminate an entire function. - -Signed-off-by: Adam Ford -Reviewed-by: Marco Felsch -Reviewed-by: Frieder Schrempf -Tested-by: Frieder Schrempf -Reviewed-by: Dominique Martinet -Tested-by: Dominique Martinet -Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com -Signed-off-by: Vinod Koul -Stable-dep-of: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") -Signed-off-by: Sasha Levin ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 39 ++------------------ - 1 file changed, 4 insertions(+), 35 deletions(-) - -diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -index acea7008aefc5..4f6874226f9ab 100644 ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) - return container_of(hw, struct fsl_samsung_hdmi_phy, hw); - } - --static void --fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, -- const struct phy_config *cfg) --{ -- u8 div = 0x1; -- -- switch (cfg->pixclk) { -- case 22250000 ... 33750000: -- div = 0xf; -- break; -- case 35000000 ... 40000000: -- div = 0xb; -- break; -- case 43200000 ... 47500000: -- div = 0x9; -- break; -- case 50349650 ... 63500000: -- div = 0x7; -- break; -- case 67500000 ... 90000000: -- div = 0x5; -- break; -- case 94000000 ... 148500000: -- div = 0x3; -- break; -- case 154000000 ... 297000000: -- div = 0x1; -- break; -- } -- -- writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), -- phy->regs + PHY_REG(21)); --} -- - static void - fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) -@@ -466,7 +432,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, - for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) - writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); - -- fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); -+ /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ -+ writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, -+ cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); -+ - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); - - writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); --- -2.39.5 - diff --git a/queue-6.12/phy-freescale-fsl-samsung-hdmi-support-dynamic-integ.patch b/queue-6.12/phy-freescale-fsl-samsung-hdmi-support-dynamic-integ.patch deleted file mode 100644 index 6febfadb7a..0000000000 --- a/queue-6.12/phy-freescale-fsl-samsung-hdmi-support-dynamic-integ.patch +++ /dev/null @@ -1,666 +0,0 @@ -From af4a21b2e7c7923f662065d94fed5af5dc932509 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 14 Sep 2024 06:27:47 -0500 -Subject: phy: freescale: fsl-samsung-hdmi: Support dynamic integer - -From: Adam Ford - -[ Upstream commit 1951dbb41d1dff7c135eed4fa1a6330df6971549 ] - -There is currently a look-up table for a variety of resolutions. -Since the phy has the ability to dynamically calculate the values -necessary to use the intger divider which should allow more -resolutions without having to update the look-up-table. - -If the lookup table cannot find an exact match, fall back to the -dynamic calculator of the integer divider. - -Previously, the value of P was hard-coded to 1, this required an -update to the phy_pll_cfg table to add in the extra value into the -table, so if the value of P is calculated to be something else -by the PMS calculator, the calculated_phy_pll_cfg structure -can be used instead without having to keep track of which method -was used. - -Signed-off-by: Adam Ford -Reviewed-by: Dominique Martinet -Tested-by: Dominique Martinet -Reviewed-by: Frieder Schrempf -Link: https://lore.kernel.org/r/20240914112816.520224-4-aford173@gmail.com -Signed-off-by: Vinod Koul -Stable-dep-of: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") -Signed-off-by: Sasha Levin ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 377 +++++++++++++------ - 1 file changed, 270 insertions(+), 107 deletions(-) - -diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -index 4f6874226f9ab..029de69fbeaf4 100644 ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -16,6 +16,8 @@ - - #define PHY_REG(reg) (reg * 4) - -+#define REG01_PMS_P_MASK GENMASK(3, 0) -+#define REG03_PMS_S_MASK GENMASK(7, 4) - #define REG12_CK_DIV_MASK GENMASK(5, 4) - - #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) -@@ -38,281 +40,296 @@ - #define REG34_PLL_LOCK BIT(6) - #define REG34_PHY_CLK_READY BIT(5) - --#define PHY_PLL_DIV_REGS_NUM 6 -+#ifndef MHZ -+#define MHZ (1000UL * 1000UL) -+#endif -+ -+#define PHY_PLL_DIV_REGS_NUM 7 - - struct phy_config { - u32 pixclk; - u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; - }; - -+/* -+ * The calculated_phy_pll_cfg only handles integer divider for PMS, -+ * meaning the last four entries will be fixed, but the first three will -+ * be calculated by the PMS calculator. -+ */ -+static struct phy_config calculated_phy_pll_cfg = { -+ .pixclk = 0, -+ .pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, -+}; -+ -+/* The lookup table contains values for which the fractional divder is used */ - static const struct phy_config phy_pll_cfg[] = { - { - .pixclk = 22250000, -- .pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 23750000, -- .pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, - }, { - .pixclk = 24000000, -- .pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 24024000, -- .pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, - }, { - .pixclk = 25175000, -- .pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, - }, { - .pixclk = 25200000, -- .pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 26750000, -- .pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 27000000, -- .pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 27027000, -- .pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 29500000, -- .pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 30750000, -- .pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, - }, { - .pixclk = 30888000, -- .pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, - }, { - .pixclk = 33750000, -- .pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, - }, { - .pixclk = 35000000, -- .pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 36000000, -- .pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 36036000, -- .pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 40000000, -- .pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 43200000, -- .pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 43243200, -- .pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 44500000, -- .pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, - }, { - .pixclk = 47000000, -- .pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, - }, { - .pixclk = 47500000, -- .pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, - }, { - .pixclk = 50349650, -- .pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk = 50400000, -- .pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 53250000, -- .pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, - }, { - .pixclk = 53500000, -- .pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 54000000, -- .pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 54054000, -- .pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 59000000, -- .pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 59340659, -- .pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, -+ .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, - }, { - .pixclk = 59400000, -- .pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 61500000, -- .pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, - }, { - .pixclk = 63500000, -- .pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 67500000, -- .pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, - }, { - .pixclk = 70000000, -- .pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 72000000, -- .pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 72072000, -- .pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 74176000, -- .pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, - }, { - .pixclk = 74250000, -- .pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, - }, { - .pixclk = 78500000, -- .pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, - }, { - .pixclk = 80000000, -- .pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 82000000, -- .pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, - }, { - .pixclk = 82500000, -- .pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, -+ .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, - }, { - .pixclk = 89000000, -- .pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, - }, { - .pixclk = 90000000, -- .pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, - }, { - .pixclk = 94000000, -- .pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, - }, { - .pixclk = 95000000, -- .pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, - }, { - .pixclk = 98901099, -- .pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, -+ .pll_div_regs = { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, - }, { - .pixclk = 99000000, -- .pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, -+ .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, - }, { - .pixclk = 100699300, -- .pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk = 100800000, -- .pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 102500000, -- .pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, -+ .pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, - }, { - .pixclk = 104750000, -- .pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, -+ .pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, - }, { - .pixclk = 106500000, -- .pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, - }, { - .pixclk = 107000000, -- .pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 108000000, -- .pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 108108000, -- .pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 118000000, -- .pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 118800000, -- .pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 123000000, -- .pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, - }, { - .pixclk = 127000000, -- .pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 135000000, -- .pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, - }, { - .pixclk = 135580000, -- .pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, -+ .pll_div_regs = { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, - }, { - .pixclk = 137520000, -- .pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, - }, { - .pixclk = 138750000, -- .pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, -+ .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, - }, { - .pixclk = 140000000, -- .pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, - }, { - .pixclk = 144000000, -- .pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 148352000, -- .pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, - }, { - .pixclk = 148500000, -- .pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, - }, { - .pixclk = 154000000, -- .pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, - }, { - .pixclk = 157000000, -- .pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, - }, { - .pixclk = 160000000, -- .pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, - }, { - .pixclk = 162000000, -- .pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, -+ .pll_div_regs = { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, - }, { - .pixclk = 164000000, -- .pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, -+ .pll_div_regs = { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, - }, { - .pixclk = 165000000, -- .pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, -+ .pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, - }, { - .pixclk = 180000000, -- .pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 185625000, -- .pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, - }, { - .pixclk = 188000000, -- .pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, - }, { - .pixclk = 198000000, -- .pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, -+ .pll_div_regs = { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, - }, { - .pixclk = 205000000, -- .pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, -+ .pll_div_regs = { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, - }, { - .pixclk = 209500000, -- .pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, -+ .pll_div_regs = { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, - }, { - .pixclk = 213000000, -- .pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, -+ .pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, - }, { - .pixclk = 216000000, -- .pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 216216000, -- .pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 237600000, -- .pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 254000000, -- .pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, -+ .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 277500000, -- .pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, -+ .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, - }, { - .pixclk = 288000000, -- .pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, -+ .pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 297000000, -- .pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, -+ .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, - }, - }; - -@@ -322,7 +339,8 @@ struct reg_settings { - }; - - static const struct reg_settings common_phy_cfg[] = { -- { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, -+ { PHY_REG(0), 0x00 }, -+ /* PHY_REG(1-7) pix clk specific */ - { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, - { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, - /* REG12 pixclk specific */ -@@ -415,6 +433,83 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - phy->regs + PHY_REG(14)); - } - -+static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) -+{ -+ unsigned long best_freq = 0; -+ u32 min_delta = 0xffffffff; -+ u8 _p, best_p; -+ u16 _m, best_m; -+ u8 _s, best_s; -+ -+ /* -+ * Figure 13-78 of the reference manual states the PLL should be TMDS x 5 -+ * while the TMDS_CLKO should be the PLL / 5. So to calculate the PLL, -+ * take the pix clock x 5, then return the value of the PLL / 5. -+ */ -+ fout *= 5; -+ -+ /* The ref manual states the values of 'P' range from 1 to 11 */ -+ for (_p = 1; _p <= 11; ++_p) { -+ for (_s = 1; _s <= 16; ++_s) { -+ u64 tmp; -+ u32 delta; -+ -+ /* s must be one or even */ -+ if (_s > 1 && (_s & 0x01) == 1) -+ _s++; -+ -+ /* _s cannot be 14 per the TRM */ -+ if (_s == 14) -+ continue; -+ -+ /* -+ * TODO: Ref Manual doesn't state the range of _m -+ * so this should be further refined if possible. -+ * This range was set based on the original values -+ * in the lookup table -+ */ -+ tmp = (u64)fout * (_p * _s); -+ do_div(tmp, 24 * MHZ); -+ _m = tmp; -+ if (_m < 0x30 || _m > 0x7b) -+ continue; -+ -+ /* -+ * Rev 2 of the Ref Manual states the -+ * VCO can range between 750MHz and -+ * 3GHz. The VCO is assumed to be -+ * Fvco = (M * f_ref) / P, -+ * where f_ref is 24MHz. -+ */ -+ tmp = (u64)_m * 24 * MHZ; -+ do_div(tmp, _p); -+ if (tmp < 750 * MHZ || -+ tmp > 3000 * MHZ) -+ continue; -+ -+ /* Final frequency after post-divider */ -+ do_div(tmp, _s); -+ -+ delta = abs(fout - tmp); -+ if (delta < min_delta) { -+ best_p = _p; -+ best_s = _s; -+ best_m = _m; -+ min_delta = delta; -+ best_freq = tmp; -+ } -+ } -+ } -+ -+ if (best_freq) { -+ *p = best_p; -+ *m = best_m; -+ *s = best_s; -+ } -+ -+ return best_freq / 5; -+} -+ - static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) - { -@@ -428,13 +523,13 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, - for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) - writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); - -- /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ -+ /* set individual PLL registers PHY_REG1 ... PHY_REG7 */ - for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) -- writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); -+ writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4); - -- /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ -+ /* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */ - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, -- cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); -+ cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); - - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); - -@@ -459,34 +554,102 @@ static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, - return phy->cur_cfg->pixclk; - } - --static long phy_clk_round_rate(struct clk_hw *hw, -- unsigned long rate, unsigned long *parent_rate) -+/* Helper function to lookup the available fractional-divider rate */ -+static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate) - { - int i; - -+ /* Search the lookup table */ - for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) - if (phy_pll_cfg[i].pixclk <= rate) -- return phy_pll_cfg[i].pixclk; -+ break; -+ -+ return &phy_pll_cfg[i]; -+} -+ -+static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate, -+ u8 p, u16 m, u8 s) -+{ -+ cal_phy->pixclk = rate; -+ cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p); -+ cal_phy->pll_div_regs[1] = m; -+ cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1); -+ /* pll_div_regs 3-6 are fixed and pre-defined already */ -+} -+ -+static long phy_clk_round_rate(struct clk_hw *hw, -+ unsigned long rate, unsigned long *parent_rate) -+{ -+ const struct phy_config *fract_div_phy; -+ u32 int_div_clk; -+ u16 m; -+ u8 p, s; -+ -+ /* If the clock is out of range return error instead of searching */ -+ if (rate > 297000000 || rate < 22250000) -+ return -EINVAL; -+ -+ /* Search the fractional divider lookup table */ -+ fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); - -- return -EINVAL; -+ /* If the rate is an exact match, return that value */ -+ if (rate == fract_div_phy->pixclk) -+ return fract_div_phy->pixclk; -+ -+ /* If the exact match isn't found, calculate the integer divider */ -+ int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); -+ -+ /* If the int_div_clk rate is an exact match, return that value */ -+ if (int_div_clk == rate) -+ return int_div_clk; -+ -+ /* If neither rate is an exact match, use the value from the LUT */ -+ return fract_div_phy->pixclk; -+} -+ -+static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy) -+{ -+ phy->cur_cfg = fract_div_phy; -+ dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n", -+ phy->cur_cfg->pixclk); -+ return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); - } - - static int phy_clk_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) - { - struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); -- int i; -+ const struct phy_config *fract_div_phy; -+ u32 int_div_clk; -+ u16 m; -+ u8 p, s; - -- for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) -- if (phy_pll_cfg[i].pixclk <= rate) -- break; -+ /* Search the fractional divider lookup table */ -+ fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); - -- if (i < 0) -- return -EINVAL; -+ /* If the rate is an exact match, use that value */ -+ if (fract_div_phy->pixclk == rate) -+ return phy_use_fract_div(phy, fract_div_phy); - -- phy->cur_cfg = &phy_pll_cfg[i]; -+ /* -+ * If the rate from the fractional divider is not exact, check the integer divider, -+ * and use it if that value is an exact match. -+ */ -+ int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); -+ if (int_div_clk == rate) { -+ dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n", -+ int_div_clk); -+ -+ fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s); -+ phy->cur_cfg = &calculated_phy_pll_cfg; -+ return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); -+ } - -- return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); -+ /* -+ * If neither the fractional divider nor the integer divider can find an exact value -+ * fall back to using the fractional divider -+ */ -+ return phy_use_fract_div(phy, fract_div_phy); - } - - static const struct clk_ops phy_clk_ops = { --- -2.39.5 - diff --git a/queue-6.12/series b/queue-6.12/series index f33515e641..51f35ed148 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -458,10 +458,6 @@ xfrm-add-support-for-per-cpu-xfrm-state-handling.patch xfrm-cache-used-outbound-xfrm-states-at-the-policy.patch xfrm-add-an-inbound-percpu-state-cache.patch xfrm-state-fix-out-of-bounds-read-during-lookup.patch -phy-freescale-fsl-samsung-hdmi-replace-register-defi.patch -phy-freescale-fsl-samsung-hdmi-simplify-reg21_pms_s_.patch -phy-freescale-fsl-samsung-hdmi-support-dynamic-integ.patch -phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch dmaengine-ti-edma-fix-of-node-reference-leaks-in-edm.patch xfrm-delete-intermediate-secpath-entry-in-packet-off.patch rtc-tps6594-fix-integer-overflow-on-32bit-systems.patch @@ -576,7 +572,6 @@ dma-mapping-save-base-size-instead-of-pointer-to-shared-dma-pool.patch xfrm-add-error-handling-when-nla_put_u32-returns-an-error.patch xfrm-fix-acquire-state-insertion.patch ethtool-fix-access-to-uninitialized-fields-in-set-rxnfc-command.patch -phy-freescale-fsl-samsung-hdmi-fix-64-by-32-division-cocci-warnings.patch revert-s390-mm-allow-large-pages-for-kasan-shadow-mapping.patch selftests-bpf-add-test-to-verify-tailcall-and-freplace-restrictions.patch asoc-da7213-initialize-the-mutex.patch diff --git a/queue-6.13/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch b/queue-6.13/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch deleted file mode 100644 index c9935fa851..0000000000 --- a/queue-6.13/phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 9642b24932cbeada57c19fe2675b44661f90c2eb Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 26 Oct 2024 08:19:59 -0500 -Subject: phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation - -From: Adam Ford - -[ Upstream commit d567679f2b6a8bcea20589bbea6488c0236886cd ] - -Currently, the calcuation for fld_tg_code is based on a lookup table, -but there are gaps in the lookup table, and frequencies in these -gaps may not properly use the correct divider. Based on the description -of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz, -so directly calcuate the value of FLD_CK_DIV from pixclk. -This allow for proper calcuation of any pixel clock and eliminates a -few gaps in the LUT. - -Since the value of the int_pllclk is in Hz, do the fixed-point -math in Hz to achieve a more accurate value and reduces the complexity -of the caluation to 24MHz * (256 / int_pllclk). - -Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY") -Signed-off-by: Adam Ford -Reviewed-by: Frieder Schrempf -Link: https://lore.kernel.org/r/20241026132014.73050-3-aford173@gmail.com -Signed-off-by: Vinod Koul -Signed-off-by: Sasha Levin ---- - drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 32 +++++++------------- - 1 file changed, 11 insertions(+), 21 deletions(-) - -diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -index d3ccf547ba1c2..17c3786c2f667 100644 ---- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c -@@ -331,25 +331,17 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - { - u32 pclk = cfg->pixclk; - u32 fld_tg_code; -- u32 pclk_khz; -- u8 div = 1; -- -- switch (cfg->pixclk) { -- case 22250000 ... 47500000: -- div = 1; -- break; -- case 50349650 ... 99000000: -- div = 2; -- break; -- case 100699300 ... 198000000: -- div = 4; -- break; -- case 205000000 ... 297000000: -- div = 8; -- break; -+ u32 int_pllclk; -+ u8 div; -+ -+ /* Find int_pllclk speed */ -+ for (div = 0; div < 4; div++) { -+ int_pllclk = pclk / (1 << div); -+ if (int_pllclk < (50 * MHZ)) -+ break; - } - -- writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)); -+ writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); - - /* - * Calculation for the frequency lock detector target code (fld_tg_code) -@@ -362,10 +354,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, - * settings rounding up always too. TODO: Check if that is - * correct. - */ -- pclk /= div; -- pclk_khz = pclk / 1000; -- fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24; -- fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000); -+ -+ fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk); - - /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ - writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), --- -2.39.5 - diff --git a/queue-6.13/series b/queue-6.13/series index 3ce4040313..b92bc82a34 100644 --- a/queue-6.13/series +++ b/queue-6.13/series @@ -491,7 +491,6 @@ loongarch-fix-warnings-during-s3-suspend.patch tools-bootconfig-fix-the-wrong-format-specifier.patch xfrm-replay-fix-the-update-of-replay_esn-oseq_hi-for.patch xfrm-state-fix-out-of-bounds-read-during-lookup.patch -phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch dmaengine-ti-edma-fix-of-node-reference-leaks-in-edm.patch xfrm-delete-intermediate-secpath-entry-in-packet-off.patch rtc-tps6594-fix-integer-overflow-on-32bit-systems.patch -- 2.47.2