From d9812bd18965b1410d43879bb0c4868187626e1c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 15 Jul 2018 13:04:19 +0200 Subject: [PATCH] 4.4-stable patches added patches: x86-alternatives-add-an-auxilary-section.patch x86-alternatives-discard-dynamic-check-after-init.patch x86-boot-simplify-kernel-load-address-alignment-check.patch x86-cpu-add-detection-of-amd-ras-capabilities.patch x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch x86-cpufeature-add-helper-macro-for-mask-check-macros.patch x86-cpufeature-carve-out-x86_feature_.patch x86-cpufeature-cleanup-get_cpu_cap.patch x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch x86-cpufeature-speed-up-cpu_feature_enabled.patch x86-cpufeature-update-cpufeaure-macros.patch x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch x86-fpu-add-an-xstate_op-macro.patch x86-fpu-get-rid-of-xstate_fault.patch x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch x86-vdso-use-static_cpu_has.patch --- queue-4.4/series | 21 + ...alternatives-add-an-auxilary-section.patch | 59 + ...ves-discard-dynamic-check-after-init.patch | 115 ++ ...-kernel-load-address-alignment-check.patch | 57 + ...dd-detection-of-amd-ras-capabilities.patch | 108 ++ ...fig-option-to-disable-static_cpu_has.patch | 65 + ...d-helper-macro-for-mask-check-macros.patch | 150 ++ ...86-cpufeature-carve-out-x86_feature_.patch | 1251 +++++++++++++++++ .../x86-cpufeature-cleanup-get_cpu_cap.patch | 201 +++ ...-get-rid-of-the-non-asm-goto-variant.patch | 126 ++ ...disabled-required-macros-are-updated.patch | 99 ++ ...tered-feature-bits-to-x86_capability.patch | 178 +++ ...old-static_cpu_has-with-safe-variant.patch | 343 +++++ ...feature-speed-up-cpu_feature_enabled.patch | 62 + ...6-cpufeature-update-cpufeaure-macros.patch | 85 ++ ...ction-keys-related-cpuid-definitions.patch | 226 +++ ...oken-compile-time-disabling-of-pkeys.patch | 104 ++ .../x86-fpu-add-an-xstate_op-macro.patch | 163 +++ .../x86-fpu-get-rid-of-xstate_fault.patch | 185 +++ ...lude-asm-processor.h-in-asm-atomic.h.patch | 84 ++ ...smerge-of-protection-keys-cpuid-bits.patch | 82 ++ queue-4.4/x86-vdso-use-static_cpu_has.patch | 48 + 22 files changed, 3812 insertions(+) create mode 100644 queue-4.4/x86-alternatives-add-an-auxilary-section.patch create mode 100644 queue-4.4/x86-alternatives-discard-dynamic-check-after-init.patch create mode 100644 queue-4.4/x86-boot-simplify-kernel-load-address-alignment-check.patch create mode 100644 queue-4.4/x86-cpu-add-detection-of-amd-ras-capabilities.patch create mode 100644 queue-4.4/x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch create mode 100644 queue-4.4/x86-cpufeature-add-helper-macro-for-mask-check-macros.patch create mode 100644 queue-4.4/x86-cpufeature-carve-out-x86_feature_.patch create mode 100644 queue-4.4/x86-cpufeature-cleanup-get_cpu_cap.patch create mode 100644 queue-4.4/x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch create mode 100644 queue-4.4/x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch create mode 100644 queue-4.4/x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch create mode 100644 queue-4.4/x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch create mode 100644 queue-4.4/x86-cpufeature-speed-up-cpu_feature_enabled.patch create mode 100644 queue-4.4/x86-cpufeature-update-cpufeaure-macros.patch create mode 100644 queue-4.4/x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch create mode 100644 queue-4.4/x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch create mode 100644 queue-4.4/x86-fpu-add-an-xstate_op-macro.patch create mode 100644 queue-4.4/x86-fpu-get-rid-of-xstate_fault.patch create mode 100644 queue-4.4/x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch create mode 100644 queue-4.4/x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch create mode 100644 queue-4.4/x86-vdso-use-static_cpu_has.patch diff --git a/queue-4.4/series b/queue-4.4/series index 397e3b71a8a..03feb8f79ce 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -13,3 +13,24 @@ hid-usbhid-add-quirk-for-innomedia-innex-genesis-atari-adapter.patch fix-up-non-directory-creation-in-sgid-directories.patch tools-build-fix-escaping-in-.cmd-files-for-future-make.patch iw_cxgb4-correctly-enforce-the-max-reg_mr-depth.patch +x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch +x86-cpufeature-cleanup-get_cpu_cap.patch +x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch +x86-fpu-add-an-xstate_op-macro.patch +x86-fpu-get-rid-of-xstate_fault.patch +x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch +x86-cpufeature-carve-out-x86_feature_.patch +x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch +x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch +x86-alternatives-add-an-auxilary-section.patch +x86-alternatives-discard-dynamic-check-after-init.patch +x86-vdso-use-static_cpu_has.patch +x86-boot-simplify-kernel-load-address-alignment-check.patch +x86-cpufeature-speed-up-cpu_feature_enabled.patch +x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch +x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch +x86-cpu-add-detection-of-amd-ras-capabilities.patch +x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch +x86-cpufeature-update-cpufeaure-macros.patch +x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch +x86-cpufeature-add-helper-macro-for-mask-check-macros.patch diff --git a/queue-4.4/x86-alternatives-add-an-auxilary-section.patch b/queue-4.4/x86-alternatives-add-an-auxilary-section.patch new file mode 100644 index 00000000000..7dacabc8531 --- /dev/null +++ b/queue-4.4/x86-alternatives-add-an-auxilary-section.patch @@ -0,0 +1,59 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:19 -0700 +Subject: [PATCH 4.4.y 010/101] x86/alternatives: Add an auxilary section +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156043921.10043.8719390586881978294.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit 337e4cc84021212a87b04b77b65cccc49304909e upstream + +Add .altinstr_aux for additional instructions which will be used +before and/or during patching. All stuff which needs more +sophisticated patching should go there. See next patch. + +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1453842730-28463-8-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/kernel/vmlinux.lds.S | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/x86/kernel/vmlinux.lds.S ++++ b/arch/x86/kernel/vmlinux.lds.S +@@ -202,6 +202,17 @@ SECTIONS + :init + #endif + ++ /* ++ * Section for code used exclusively before alternatives are run. All ++ * references to such code must be patched out by alternatives, normally ++ * by using X86_FEATURE_ALWAYS CPU feature bit. ++ * ++ * See static_cpu_has() for an example. ++ */ ++ .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { ++ *(.altinstr_aux) ++ } ++ + INIT_DATA_SECTION(16) + + .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { diff --git a/queue-4.4/x86-alternatives-discard-dynamic-check-after-init.patch b/queue-4.4/x86-alternatives-discard-dynamic-check-after-init.patch new file mode 100644 index 00000000000..dbbed85b096 --- /dev/null +++ b/queue-4.4/x86-alternatives-discard-dynamic-check-after-init.patch @@ -0,0 +1,115 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:28 -0700 +Subject: [PATCH 4.4.y 011/101] x86/alternatives: Discard dynamic check after init +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Brian Gerst , Borislav Petkov , Andrew Morton , Andy Lutomirski , Andy Lutomirski , Boris Ostrovsky , Borislav Petkov , Dave Young , Denys Vlasenko , "H. Peter Anvin" , Kristen Carlson Accardi , Laura Abbott , Linus Torvalds , "Peter Zijlstra \(Intel\)" , Peter Zijlstra , Prarit Bhargava , Ross Zwisler , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156044794.10043.10074610002322426562.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Brian Gerst + +commit 2476f2fa20568bd5d9e09cd35bcd73e99a6f4cc6 upstream + +Move the code to do the dynamic check to the altinstr_aux +section so that it is discarded after alternatives have run and +a static branch has been chosen. + +This way we're changing the dynamic branch from C code to +assembly, which makes it *substantially* smaller while avoiding +a completely unnecessary call to an out of line function. + +Signed-off-by: Brian Gerst +[ Changed it to do TESTB, as hpa suggested. ] +Signed-off-by: Borislav Petkov +Cc: Andrew Morton +Cc: Andy Lutomirski +Cc: Andy Lutomirski +Cc: Boris Ostrovsky +Cc: Borislav Petkov +Cc: Dave Young +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Kristen Carlson Accardi +Cc: Laura Abbott +Cc: Linus Torvalds +Cc: Peter Zijlstra (Intel) +Cc: Peter Zijlstra +Cc: Prarit Bhargava +Cc: Ross Zwisler +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1452972124-7380-1-git-send-email-brgerst@gmail.com +Link: http://lkml.kernel.org/r/20160127084525.GC30712@pd.tnic +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 19 ++++++++++++------- + arch/x86/kernel/cpu/common.c | 6 ------ + 2 files changed, 12 insertions(+), 13 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -132,8 +132,6 @@ extern const char * const x86_bug_flags[ + */ + + #if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) +-extern bool __static_cpu_has(u16 bit); +- + /* + * Static testing of CPU features. Used the same as boot_cpu_has(). + * These will statically patch the target code for additional +@@ -141,7 +139,7 @@ extern bool __static_cpu_has(u16 bit); + */ + static __always_inline __pure bool _static_cpu_has(u16 bit) + { +- asm_volatile_goto("1: jmp %l[t_dynamic]\n" ++ asm_volatile_goto("1: jmp 6f\n" + "2:\n" + ".skip -(((5f-4f) - (2b-1b)) > 0) * " + "((5f-4f) - (2b-1b)),0x90\n" +@@ -166,13 +164,20 @@ static __always_inline __pure bool _stat + " .byte 0\n" /* repl len */ + " .byte 0\n" /* pad len */ + ".previous\n" +- : : "i" (bit), "i" (X86_FEATURE_ALWAYS) +- : : t_dynamic, t_no); ++ ".section .altinstr_aux,\"ax\"\n" ++ "6:\n" ++ " testb %[bitnum],%[cap_byte]\n" ++ " jnz %l[t_yes]\n" ++ " jmp %l[t_no]\n" ++ ".previous\n" ++ : : "i" (bit), "i" (X86_FEATURE_ALWAYS), ++ [bitnum] "i" (1 << (bit & 7)), ++ [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) ++ : : t_yes, t_no); ++ t_yes: + return true; + t_no: + return false; +- t_dynamic: +- return __static_cpu_has(bit); + } + + #define static_cpu_has(bit) \ +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -1576,12 +1576,6 @@ void cpu_init(void) + } + #endif + +-inline bool __static_cpu_has(u16 bit) +-{ +- return boot_cpu_has(bit); +-} +-EXPORT_SYMBOL_GPL(__static_cpu_has); +- + static void bsp_resume(void) + { + if (this_cpu->c_bsp_resume) diff --git a/queue-4.4/x86-boot-simplify-kernel-load-address-alignment-check.patch b/queue-4.4/x86-boot-simplify-kernel-load-address-alignment-check.patch new file mode 100644 index 00000000000..06741401902 --- /dev/null +++ b/queue-4.4/x86-boot-simplify-kernel-load-address-alignment-check.patch @@ -0,0 +1,57 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:46 -0700 +Subject: [PATCH 4.4.y 013/101] x86/boot: Simplify kernel load address alignment check +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Brian Gerst , Alexander Kuleshov , Borislav Petkov , Alexander Popov , Andrey Ryabinin , Andy Lutomirski , Andy Lutomirski , Borislav Petkov , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156046632.10043.12222368761298728509.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Alexander Kuleshov + +commit a4733143085d6c782ac1e6c85778655b6bac1d4e upstream + +We are using %rax as temporary register to check the kernel +address alignment. We don't really have to since the TEST +instruction does not clobber the destination operand. + +Suggested-by: Brian Gerst +Signed-off-by: Alexander Kuleshov +Signed-off-by: Borislav Petkov +Cc: Alexander Popov +Cc: Andrey Ryabinin +Cc: Andy Lutomirski +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1453531828-19291-1-git-send-email-kuleshovmail@gmail.com +Link: http://lkml.kernel.org/r/1453842730-28463-11-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/kernel/head_64.S | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/arch/x86/kernel/head_64.S ++++ b/arch/x86/kernel/head_64.S +@@ -76,9 +76,7 @@ startup_64: + subq $_text - __START_KERNEL_map, %rbp + + /* Is the address not 2M aligned? */ +- movq %rbp, %rax +- andl $~PMD_PAGE_MASK, %eax +- testl %eax, %eax ++ testl $~PMD_PAGE_MASK, %ebp + jnz bad_address + + /* diff --git a/queue-4.4/x86-cpu-add-detection-of-amd-ras-capabilities.patch b/queue-4.4/x86-cpu-add-detection-of-amd-ras-capabilities.patch new file mode 100644 index 00000000000..7864dc54a44 --- /dev/null +++ b/queue-4.4/x86-cpu-add-detection-of-amd-ras-capabilities.patch @@ -0,0 +1,108 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:21 -0700 +Subject: [PATCH 4.4.y 017/101] x86/cpu: Add detection of AMD RAS Capabilities +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Yazen Ghannam , Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Tony Luck , linux-edac , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156050185.10043.1813259649945748641.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Yazen Ghannam + +commit 71faad43060d3d2040583635fbf7d1bdb3d04118 upstream + +Add a new CPUID leaf to hold the contents of CPUID 0x80000007_EBX (RasCap). + +Define bits that are currently in use: + + Bit 0: McaOverflowRecov + Bit 1: SUCCOR + Bit 3: ScalableMca + +Signed-off-by: Yazen Ghannam +[ Shorten comment. ] +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Cc: Tony Luck +Cc: linux-edac +Link: http://lkml.kernel.org/r/1462971509-3856-5-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 1 + + arch/x86/include/asm/cpufeatures.h | 7 ++++++- + arch/x86/kernel/cpu/common.c | 10 +++++++--- + 3 files changed, 14 insertions(+), 4 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -27,6 +27,7 @@ enum cpuid_leafs + CPUID_6_EAX, + CPUID_8000_000A_EDX, + CPUID_7_ECX, ++ CPUID_8000_0007_EBX, + }; + + #ifdef CONFIG_X86_FEATURE_NAMES +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -12,7 +12,7 @@ + /* + * Defines x86 CPU feature bits + */ +-#define NCAPINTS 17 /* N 32-bit words worth of info */ ++#define NCAPINTS 18 /* N 32-bit words worth of info */ + #define NBUGINTS 1 /* N 32-bit bug flags */ + + /* +@@ -280,6 +280,11 @@ + #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ + #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ + ++/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ ++#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ ++#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ ++#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ ++ + /* + * BUG word(s) + */ +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -741,6 +741,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + } + } + ++ if (c->extended_cpuid_level >= 0x80000007) { ++ cpuid(0x80000007, &eax, &ebx, &ecx, &edx); ++ ++ c->x86_capability[CPUID_8000_0007_EBX] = ebx; ++ c->x86_power = edx; ++ } ++ + if (c->extended_cpuid_level >= 0x80000008) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + +@@ -753,9 +760,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + c->x86_phys_bits = 36; + #endif + +- if (c->extended_cpuid_level >= 0x80000007) +- c->x86_power = cpuid_edx(0x80000007); +- + if (c->extended_cpuid_level >= 0x8000000a) + c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); + diff --git a/queue-4.4/x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch b/queue-4.4/x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch new file mode 100644 index 00000000000..0e0c22d4739 --- /dev/null +++ b/queue-4.4/x86-cpu-provide-a-config-option-to-disable-static_cpu_has.patch @@ -0,0 +1,65 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:17 -0700 +Subject: [PATCH 4.4.y 003/101] x86/cpu: Provide a config option to disable static_cpu_has +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Josh Triplett , Thomas Gleixner , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156037706.10043.1500460832945981762.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit 6e1315fe82308cd29e7550eab967262e8bbc71a3 upstream + +This brings .text savings of about ~1.6K when building a tinyconfig. It +is off by default so nothing changes for the default. + +Kconfig help text from Josh. + +Signed-off-by: Borislav Petkov +Reviewed-by: Josh Triplett +Link: http://lkml.kernel.org/r/1449481182-27541-5-git-send-email-bp@alien8.de +Signed-off-by: Thomas Gleixner +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/Kconfig | 11 +++++++++++ + arch/x86/include/asm/cpufeature.h | 2 +- + 2 files changed, 12 insertions(+), 1 deletion(-) + +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -346,6 +346,17 @@ config X86_FEATURE_NAMES + + If in doubt, say Y. + ++config X86_FAST_FEATURE_TESTS ++ bool "Fast CPU feature tests" if EMBEDDED ++ default y ++ ---help--- ++ Some fast-paths in the kernel depend on the capabilities of the CPU. ++ Say Y here for the kernel to patch in the appropriate code at runtime ++ based on the capabilities of the CPU. The infrastructure for patching ++ code at runtime takes up some additional space; space-constrained ++ embedded systems may wish to say N here to produce smaller, slightly ++ slower code. ++ + config X86_X2APIC + bool "Support x2apic" + depends on X86_LOCAL_APIC && X86_64 && (IRQ_REMAP || HYPERVISOR_GUEST) +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -422,7 +422,7 @@ extern const char * const x86_bug_flags[ + * fast paths and boot_cpu_has() otherwise! + */ + +-#if __GNUC__ >= 4 ++#if __GNUC__ >= 4 && defined(CONFIG_X86_FAST_FEATURE_TESTS) + extern void warn_pre_alternatives(void); + extern bool __static_cpu_has_safe(u16 bit); + diff --git a/queue-4.4/x86-cpufeature-add-helper-macro-for-mask-check-macros.patch b/queue-4.4/x86-cpufeature-add-helper-macro-for-mask-check-macros.patch new file mode 100644 index 00000000000..e15b82bd82d --- /dev/null +++ b/queue-4.4/x86-cpufeature-add-helper-macro-for-mask-check-macros.patch @@ -0,0 +1,150 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:57 -0700 +Subject: [PATCH 4.4.y 021/101] x86/cpufeature: Add helper macro for mask check macros +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Dave Hansen , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , "H. Peter Anvin" , Josh Poimboeuf , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156053783.10043.15255144309203407957.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit 8eda072e9d7c3429a372e3635dc5851f4a42dee1 upstream + +Every time we add a word to our cpu features, we need to add +something like this in two places: + + (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) + +The trick is getting the "16" in this case in both places. I've +now screwed this up twice, so as pennance, I've come up with +this patch to keep me and other poor souls from doing the same. + +I also commented the logic behind the bit manipulation showcased +above. + +Signed-off-by: Dave Hansen +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Josh Poimboeuf +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/20160629200110.1BA8949E@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 90 +++++++++++++++++++++----------------- + 1 file changed, 50 insertions(+), 40 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -49,48 +49,58 @@ extern const char * const x86_bug_flags[ + #define test_cpu_cap(c, bit) \ + test_bit(bit, (unsigned long *)((c)->x86_capability)) + +-#define REQUIRED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) || \ +- (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) || \ +- (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \ +- (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ +- (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ +- (((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ +- (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) || \ +- (((bit)>>5)==17 && (1UL<<((bit)&31) & REQUIRED_MASK17)) || \ +- REQUIRED_MASK_CHECK || \ ++/* ++ * There are 32 bits/features in each mask word. The high bits ++ * (selected with (bit>>5) give us the word number and the low 5 ++ * bits give us the bit/feature number inside the word. ++ * (1UL<<((bit)&31) gives us a mask for the feature_bit so we can ++ * see if it is set in the mask word. ++ */ ++#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \ ++ (((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word )) ++ ++#define REQUIRED_MASK_BIT_SET(feature_bit) \ ++ ( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 2, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 3, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 4, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 5, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 6, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 7, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 8, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 9, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ ++ REQUIRED_MASK_CHECK || \ + BUILD_BUG_ON_ZERO(NCAPINTS != 18)) + +-#define DISABLED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) || \ +- (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) || \ +- (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \ +- (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ +- (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ +- (((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ +- (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) || \ +- (((bit)>>5)==17 && (1UL<<((bit)&31) & DISABLED_MASK17)) || \ +- DISABLED_MASK_CHECK || \ ++#define DISABLED_MASK_BIT_SET(feature_bit) \ ++ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 1, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 2, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 3, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 4, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 5, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 6, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 7, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 8, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 9, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ ++ DISABLED_MASK_CHECK || \ + BUILD_BUG_ON_ZERO(NCAPINTS != 18)) + + #define cpu_has(c, bit) \ diff --git a/queue-4.4/x86-cpufeature-carve-out-x86_feature_.patch b/queue-4.4/x86-cpufeature-carve-out-x86_feature_.patch new file mode 100644 index 00000000000..fd4ddaeaa26 --- /dev/null +++ b/queue-4.4/x86-cpufeature-carve-out-x86_feature_.patch @@ -0,0 +1,1251 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:52 -0700 +Subject: [PATCH 4.4.y 007/101] x86/cpufeature: Carve out X86_FEATURE_* +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: "H. Peter Anvin" , Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156041244.10043.15033365448770721155.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit cd4d09ec6f6c12a2cc3db5b7d8876a325a53545b upstream + +Move them to a separate header and have the following +dependency: + + x86/cpufeatures.h <- x86/processor.h <- x86/cpufeature.h + +This makes it easier to use the header in asm code and not +include the whole cpufeature.h and add guards for asm. + +Suggested-by: H. Peter Anvin +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1453842730-28463-5-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + Documentation/kernel-parameters.txt | 2 + arch/x86/boot/cpuflags.h | 2 + arch/x86/boot/mkcpustr.c | 2 + arch/x86/crypto/crc32-pclmul_glue.c | 2 + arch/x86/crypto/crc32c-intel_glue.c | 2 + arch/x86/crypto/crct10dif-pclmul_glue.c | 2 + arch/x86/entry/common.c | 1 + arch/x86/entry/entry_32.S | 2 + arch/x86/entry/vdso/vdso32-setup.c | 1 + arch/x86/entry/vdso/vdso32/system_call.S | 2 + arch/x86/entry/vdso/vma.c | 1 + arch/x86/include/asm/alternative.h | 6 + arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/arch_hweight.h | 2 + arch/x86/include/asm/cmpxchg.h | 1 + arch/x86/include/asm/cpufeature.h | 293 ------------------------------ + arch/x86/include/asm/cpufeatures.h | 297 +++++++++++++++++++++++++++++++ + arch/x86/include/asm/fpu/internal.h | 1 + arch/x86/include/asm/irq_work.h | 2 + arch/x86/include/asm/mwait.h | 2 + arch/x86/include/asm/nospec-branch.h | 2 + arch/x86/include/asm/processor.h | 3 + arch/x86/include/asm/smap.h | 2 + arch/x86/include/asm/smp.h | 1 + arch/x86/include/asm/thread_info.h | 2 + arch/x86/include/asm/tlbflush.h | 1 + arch/x86/include/asm/uaccess_64.h | 2 + arch/x86/kernel/cpu/Makefile | 2 + arch/x86/kernel/cpu/centaur.c | 2 + arch/x86/kernel/cpu/cyrix.c | 1 + arch/x86/kernel/cpu/intel.c | 2 + arch/x86/kernel/cpu/intel_cacheinfo.c | 2 + arch/x86/kernel/cpu/match.c | 2 + arch/x86/kernel/cpu/mkcapflags.sh | 6 + arch/x86/kernel/cpu/mtrr/main.c | 2 + arch/x86/kernel/cpu/transmeta.c | 2 + arch/x86/kernel/e820.c | 1 + arch/x86/kernel/head_32.S | 2 + arch/x86/kernel/hpet.c | 1 + arch/x86/kernel/msr.c | 2 + arch/x86/kernel/verify_cpu.S | 2 + arch/x86/lib/clear_page_64.S | 2 + arch/x86/lib/copy_page_64.S | 2 + arch/x86/lib/copy_user_64.S | 2 + arch/x86/lib/memcpy_64.S | 2 + arch/x86/lib/memmove_64.S | 2 + arch/x86/lib/memset_64.S | 2 + arch/x86/lib/retpoline.S | 2 + arch/x86/mm/setup_nx.c | 1 + arch/x86/oprofile/op_model_amd.c | 1 + arch/x86/um/asm/barrier.h | 2 + lib/atomic64_test.c | 2 + 52 files changed, 347 insertions(+), 339 deletions(-) + create mode 100644 arch/x86/include/asm/cpufeatures.h + +--- a/Documentation/kernel-parameters.txt ++++ b/Documentation/kernel-parameters.txt +@@ -652,7 +652,7 @@ bytes respectively. Such letter suffixes + + clearcpuid=BITNUM [X86] + Disable CPUID feature X for the kernel. See +- arch/x86/include/asm/cpufeature.h for the valid bit ++ arch/x86/include/asm/cpufeatures.h for the valid bit + numbers. Note the Linux specific bits are not necessarily + stable over kernel options, but the vendor specific + ones should be. +--- a/arch/x86/boot/cpuflags.h ++++ b/arch/x86/boot/cpuflags.h +@@ -1,7 +1,7 @@ + #ifndef BOOT_CPUFLAGS_H + #define BOOT_CPUFLAGS_H + +-#include ++#include + #include + + struct cpu_features { +--- a/arch/x86/boot/mkcpustr.c ++++ b/arch/x86/boot/mkcpustr.c +@@ -17,7 +17,7 @@ + + #include "../include/asm/required-features.h" + #include "../include/asm/disabled-features.h" +-#include "../include/asm/cpufeature.h" ++#include "../include/asm/cpufeatures.h" + #include "../kernel/cpu/capflags.c" + + int main(void) +--- a/arch/x86/crypto/crc32-pclmul_glue.c ++++ b/arch/x86/crypto/crc32-pclmul_glue.c +@@ -33,7 +33,7 @@ + #include + #include + +-#include ++#include + #include + #include + +--- a/arch/x86/crypto/crc32c-intel_glue.c ++++ b/arch/x86/crypto/crc32c-intel_glue.c +@@ -30,7 +30,7 @@ + #include + #include + +-#include ++#include + #include + #include + +--- a/arch/x86/crypto/crct10dif-pclmul_glue.c ++++ b/arch/x86/crypto/crct10dif-pclmul_glue.c +@@ -30,7 +30,7 @@ + #include + #include + #include +-#include ++#include + #include + + asmlinkage __u16 crc_t10dif_pcl(__u16 crc, const unsigned char *buf, +--- a/arch/x86/entry/common.c ++++ b/arch/x86/entry/common.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #define CREATE_TRACE_POINTS + #include +--- a/arch/x86/entry/entry_32.S ++++ b/arch/x86/entry/entry_32.S +@@ -40,7 +40,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include +--- a/arch/x86/entry/vdso/vdso32-setup.c ++++ b/arch/x86/entry/vdso/vdso32-setup.c +@@ -11,7 +11,6 @@ + #include + #include + +-#include + #include + #include + +--- a/arch/x86/entry/vdso/vdso32/system_call.S ++++ b/arch/x86/entry/vdso/vdso32/system_call.S +@@ -3,7 +3,7 @@ + */ + + #include +-#include ++#include + #include + + /* +--- a/arch/x86/entry/vdso/vma.c ++++ b/arch/x86/entry/vdso/vma.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + + #if defined(CONFIG_X86_64) + unsigned int __read_mostly vdso64_enabled = 1; +--- a/arch/x86/include/asm/alternative.h ++++ b/arch/x86/include/asm/alternative.h +@@ -154,12 +154,6 @@ static inline int alternatives_text_rese + ".popsection\n" + + /* +- * This must be included *after* the definition of ALTERNATIVE due to +- * +- */ +-#include +- +-/* + * Alternative instructions for different CPU types or capabilities. + * + * This allows to use optimized instructions even on generic binary +--- a/arch/x86/include/asm/apic.h ++++ b/arch/x86/include/asm/apic.h +@@ -6,7 +6,6 @@ + + #include + #include +-#include + #include + #include + #include +--- a/arch/x86/include/asm/arch_hweight.h ++++ b/arch/x86/include/asm/arch_hweight.h +@@ -1,6 +1,8 @@ + #ifndef _ASM_X86_HWEIGHT_H + #define _ASM_X86_HWEIGHT_H + ++#include ++ + #ifdef CONFIG_64BIT + /* popcnt %edi, %eax */ + #define POPCNT32 ".byte 0xf3,0x0f,0xb8,0xc7" +--- a/arch/x86/include/asm/cmpxchg.h ++++ b/arch/x86/include/asm/cmpxchg.h +@@ -2,6 +2,7 @@ + #define ASM_X86_CMPXCHG_H + + #include ++#include + #include /* Provides LOCK_PREFIX */ + + /* +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -1,298 +1,7 @@ +-/* +- * Defines x86 CPU feature bits +- */ + #ifndef _ASM_X86_CPUFEATURE_H + #define _ASM_X86_CPUFEATURE_H + +-#ifndef _ASM_X86_REQUIRED_FEATURES_H +-#include +-#endif +- +-#ifndef _ASM_X86_DISABLED_FEATURES_H +-#include +-#endif +- +-#define NCAPINTS 16 /* N 32-bit words worth of info */ +-#define NBUGINTS 1 /* N 32-bit bug flags */ +- +-/* +- * Note: If the comment begins with a quoted string, that string is used +- * in /proc/cpuinfo instead of the macro name. If the string is "", +- * this feature bit is not displayed in /proc/cpuinfo at all. +- */ +- +-/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ +-#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ +-#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ +-#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ +-#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ +-#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ +-#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ +-#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ +-#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ +-#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ +-#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ +-#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ +-#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ +-#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ +-#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ +-#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ +- /* (plus FCMOVcc, FCOMI with FPU) */ +-#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ +-#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ +-#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ +-#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ +-#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ +-#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ +-#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ +-#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ +-#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ +-#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ +-#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ +-#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ +-#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ +-#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ +-#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ +- +-/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ +-/* Don't duplicate feature flags which are redundant with Intel! */ +-#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ +-#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ +-#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ +-#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ +-#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ +-#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ +-#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ +-#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ +-#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ +-#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ +- +-/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ +-#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ +-#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ +-#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ +- +-/* Other features, Linux-defined mapping, word 3 */ +-/* This range is used for feature bits which conflict or are synthesized */ +-#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ +-#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ +-#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ +-#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ +-/* cpu types for specific tunings: */ +-#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ +-#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ +-#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ +-#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ +-#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ +-#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ +-/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ +-#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ +-#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ +-#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ +-#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ +-#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ +-#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ +-#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ +-#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ +-/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ +-#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ +-#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ +-#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ +-#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ +-#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ +-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +-#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ +-#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ +-#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ +-/* free, was #define X86_FEATURE_EAGER_FPU ( 3*32+29) * "eagerfpu" Non lazy FPU restore */ +-#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ +- +-/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ +-#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ +-#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ +-#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ +-#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ +-#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ +-#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ +-#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ +-#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ +-#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ +-#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ +-#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ +-#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ +-#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ +-#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ +-#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ +-#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ +-#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ +-#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ +-#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ +-#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ +-#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ +-#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ +-#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ +-#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ +-#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ +-#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ +-#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ +-#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ +-#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ +-#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ +-#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ +- +-/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ +-#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ +-#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ +-#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ +-#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ +-#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ +-#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ +-#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ +-#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ +-#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ +-#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ +- +-/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ +-#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ +-#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ +-#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ +-#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ +-#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ +-#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ +-#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ +-#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ +-#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ +-#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ +-#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ +-#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ +-#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ +-#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ +-#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ +-#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ +-#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ +-#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ +-#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ +-#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ +-#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ +-#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ +-#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ +-#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +-#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ +- +-/* +- * Auxiliary flags: Linux defined - For features scattered in various +- * CPUID levels like 0x6, 0xA etc, word 7. +- * +- * Reuse free bits when adding new feature flags! +- */ +- +-#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ +-#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +-#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */ +- +-#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ +-#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ +- +-#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ +-#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ +- +-#define X86_FEATURE_RETPOLINE ( 7*32+29) /* Generic Retpoline mitigation for Spectre variant 2 */ +-#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* AMD Retpoline mitigation for Spectre variant 2 */ +-/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ +-#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */ +- +-/* Virtualization flags: Linux defined, word 8 */ +-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ +-#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ +-#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ +-#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ +-#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ +- +-#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ +-#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ +- +- +-/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ +-#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ +-#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ +-#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ +-#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ +-#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ +-#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ +-#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ +-#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ +-#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ +-#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ +-#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ +-#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ +-#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ +-#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ +-#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ +-#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ +-#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ +-#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ +-#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ +-#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ +-#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ +-#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +-#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ +- +-/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ +-#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ +-#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ +-#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ +-#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ +- +-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ +-#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ +- +-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ +-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +- +-/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +-#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ +- +-/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ +-#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ +-#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ +-#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ +-#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ +-#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ +-#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ +-#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ +-#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ +-#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ +-#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ +- +-/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ +-#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ +-#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ +-#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ +-#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ +-#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ +-#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ +-#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ +-#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ +-#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ +-#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ +- +-/* +- * BUG word(s) +- */ +-#define X86_BUG(x) (NCAPINTS*32 + (x)) +- +-#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ +-#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ +-#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ +-#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ +-#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ +-#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ +-#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ +-#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ +-#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ +-#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ +-#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ +-#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ ++#include + + #if defined(__KERNEL__) && !defined(__ASSEMBLY__) + +--- /dev/null ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -0,0 +1,297 @@ ++#ifndef _ASM_X86_CPUFEATURES_H ++#define _ASM_X86_CPUFEATURES_H ++ ++#ifndef _ASM_X86_REQUIRED_FEATURES_H ++#include ++#endif ++ ++#ifndef _ASM_X86_DISABLED_FEATURES_H ++#include ++#endif ++ ++/* ++ * Defines x86 CPU feature bits ++ */ ++#define NCAPINTS 16 /* N 32-bit words worth of info */ ++#define NBUGINTS 1 /* N 32-bit bug flags */ ++ ++/* ++ * Note: If the comment begins with a quoted string, that string is used ++ * in /proc/cpuinfo instead of the macro name. If the string is "", ++ * this feature bit is not displayed in /proc/cpuinfo at all. ++ */ ++ ++/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ ++#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ ++#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ ++#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ ++#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ ++#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ ++#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ ++#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ ++#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ ++#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ ++#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ ++#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ ++#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ ++#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ ++#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ ++#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ ++ /* (plus FCMOVcc, FCOMI with FPU) */ ++#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ ++#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ ++#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ ++#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ ++#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ ++#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ ++#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ ++#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ ++#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ ++#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ ++#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ ++#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ ++#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ ++#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ ++#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ ++ ++/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ ++/* Don't duplicate feature flags which are redundant with Intel! */ ++#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ ++#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ ++#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ ++#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ ++#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ ++#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ ++#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ ++#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ ++#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ ++#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ ++ ++/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ ++#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ ++#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ ++#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ ++ ++/* Other features, Linux-defined mapping, word 3 */ ++/* This range is used for feature bits which conflict or are synthesized */ ++#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ ++#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ ++#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ ++#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ ++/* cpu types for specific tunings: */ ++#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ ++#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ ++#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ ++#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ ++#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ ++#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ ++/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ ++#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ ++#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ ++#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ ++#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ ++#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ ++#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ ++#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ ++#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ ++/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ ++#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ ++#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ ++#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ ++#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ ++#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ ++/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ ++#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ ++#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ ++#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ ++/* free, was #define X86_FEATURE_EAGER_FPU ( 3*32+29) * "eagerfpu" Non lazy FPU restore */ ++#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ ++ ++/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ ++#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ ++#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ ++#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ ++#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ ++#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ ++#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ ++#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ ++#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ ++#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ ++#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ ++#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ ++#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ ++#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ ++#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ ++#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ ++#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ ++#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ ++#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ ++#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ ++#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ ++#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ ++#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ ++#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ ++#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ ++#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ ++#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ ++#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ ++#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ ++#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ ++#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ ++#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ ++ ++/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ ++#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ ++#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ ++#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ ++#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ ++#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ ++#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ ++#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ ++#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ ++#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ ++#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ ++ ++/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ ++#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ ++#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ ++#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ ++#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ ++#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ ++#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ ++#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ ++#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ ++#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ ++#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ ++#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ ++#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ ++#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ ++#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ ++#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ ++#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ ++#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ ++#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ ++#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ ++#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ ++#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ ++#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ ++#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ ++#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ ++#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ ++ ++/* ++ * Auxiliary flags: Linux defined - For features scattered in various ++ * CPUID levels like 0x6, 0xA etc, word 7. ++ * ++ * Reuse free bits when adding new feature flags! ++ */ ++ ++#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ ++#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ ++#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */ ++ ++#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ ++#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ ++ ++#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ ++#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ ++ ++#define X86_FEATURE_RETPOLINE ( 7*32+29) /* Generic Retpoline mitigation for Spectre variant 2 */ ++#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* AMD Retpoline mitigation for Spectre variant 2 */ ++/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ ++#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */ ++ ++/* Virtualization flags: Linux defined, word 8 */ ++#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ ++#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ ++#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ ++#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ ++#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ ++ ++#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ ++#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ ++ ++ ++/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ ++#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ ++#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ ++#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ ++#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ ++#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ ++#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ ++#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ ++#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ ++#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ ++#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ ++#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ ++#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ ++#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ ++#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ ++#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ ++#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ ++#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ ++#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ ++#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ ++#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ ++#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ ++#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ ++#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ ++ ++/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ ++#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ ++#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ ++#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ ++#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ ++ ++/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ ++#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ ++ ++/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ ++#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ ++ ++/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ ++#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ ++ ++/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ ++#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ ++#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ ++#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ ++#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ ++#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ ++#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ ++#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ ++#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ ++#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ ++#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ ++ ++/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ ++#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ ++#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ ++#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ ++#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ ++#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ ++#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ ++#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ ++#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ ++#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ ++#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ ++ ++/* ++ * BUG word(s) ++ */ ++#define X86_BUG(x) (NCAPINTS*32 + (x)) ++ ++#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ ++#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ ++#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ ++#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ ++#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ ++#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ ++#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ ++#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ ++#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ ++#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ ++#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ ++#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ ++ ++#endif /* _ASM_X86_CPUFEATURES_H */ +--- a/arch/x86/include/asm/fpu/internal.h ++++ b/arch/x86/include/asm/fpu/internal.h +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + /* + * High level FPU state handling functions: +--- a/arch/x86/include/asm/irq_work.h ++++ b/arch/x86/include/asm/irq_work.h +@@ -1,7 +1,7 @@ + #ifndef _ASM_IRQ_WORK_H + #define _ASM_IRQ_WORK_H + +-#include ++#include + + static inline bool arch_irq_work_has_interrupt(void) + { +--- a/arch/x86/include/asm/mwait.h ++++ b/arch/x86/include/asm/mwait.h +@@ -3,6 +3,8 @@ + + #include + ++#include ++ + #define MWAIT_SUBSTATE_MASK 0xf + #define MWAIT_CSTATE_MASK 0xf + #define MWAIT_SUBSTATE_SIZE 4 +--- a/arch/x86/include/asm/nospec-branch.h ++++ b/arch/x86/include/asm/nospec-branch.h +@@ -5,7 +5,7 @@ + + #include + #include +-#include ++#include + + /* + * Fill the CPU return stack buffer. +--- a/arch/x86/include/asm/processor.h ++++ b/arch/x86/include/asm/processor.h +@@ -13,7 +13,7 @@ struct vm86; + #include + #include + #include +-#include ++#include + #include + #include + #include +@@ -24,7 +24,6 @@ struct vm86; + #include + + #include +-#include + #include + #include + #include +--- a/arch/x86/include/asm/smap.h ++++ b/arch/x86/include/asm/smap.h +@@ -15,7 +15,7 @@ + + #include + #include +-#include ++#include + + /* "Raw" instruction opcodes */ + #define __ASM_CLAC .byte 0x0f,0x01,0xca +--- a/arch/x86/include/asm/smp.h ++++ b/arch/x86/include/asm/smp.h +@@ -16,7 +16,6 @@ + #endif + #include + #include +-#include + + extern int smp_num_siblings; + extern unsigned int num_processors; +--- a/arch/x86/include/asm/thread_info.h ++++ b/arch/x86/include/asm/thread_info.h +@@ -49,7 +49,7 @@ + */ + #ifndef __ASSEMBLY__ + struct task_struct; +-#include ++#include + #include + + struct thread_info { +--- a/arch/x86/include/asm/tlbflush.h ++++ b/arch/x86/include/asm/tlbflush.h +@@ -5,6 +5,7 @@ + #include + + #include ++#include + #include + #include + +--- a/arch/x86/include/asm/uaccess_64.h ++++ b/arch/x86/include/asm/uaccess_64.h +@@ -8,7 +8,7 @@ + #include + #include + #include +-#include ++#include + #include + + /* +--- a/arch/x86/kernel/cpu/Makefile ++++ b/arch/x86/kernel/cpu/Makefile +@@ -62,7 +62,7 @@ ifdef CONFIG_X86_FEATURE_NAMES + quiet_cmd_mkcapflags = MKCAP $@ + cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@ + +-cpufeature = $(src)/../../include/asm/cpufeature.h ++cpufeature = $(src)/../../include/asm/cpufeatures.h + + targets += capflags.c + $(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE +--- a/arch/x86/kernel/cpu/centaur.c ++++ b/arch/x86/kernel/cpu/centaur.c +@@ -1,7 +1,7 @@ + #include + #include + +-#include ++#include + #include + #include + #include +--- a/arch/x86/kernel/cpu/cyrix.c ++++ b/arch/x86/kernel/cpu/cyrix.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + #include "cpu.h" + +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -8,7 +8,7 @@ + #include + #include + +-#include ++#include + #include + #include + #include +--- a/arch/x86/kernel/cpu/intel_cacheinfo.c ++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c +@@ -14,7 +14,7 @@ + #include + #include + +-#include ++#include + #include + #include + +--- a/arch/x86/kernel/cpu/match.c ++++ b/arch/x86/kernel/cpu/match.c +@@ -1,5 +1,5 @@ + #include +-#include ++#include + #include + #include + #include +--- a/arch/x86/kernel/cpu/mkcapflags.sh ++++ b/arch/x86/kernel/cpu/mkcapflags.sh +@@ -1,6 +1,6 @@ + #!/bin/sh + # +-# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeature.h ++# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeatures.h + # + + IN=$1 +@@ -49,8 +49,8 @@ dump_array() + trap 'rm "$OUT"' EXIT + + ( +- echo "#ifndef _ASM_X86_CPUFEATURE_H" +- echo "#include " ++ echo "#ifndef _ASM_X86_CPUFEATURES_H" ++ echo "#include " + echo "#endif" + echo "" + +--- a/arch/x86/kernel/cpu/mtrr/main.c ++++ b/arch/x86/kernel/cpu/mtrr/main.c +@@ -47,7 +47,7 @@ + #include + #include + +-#include ++#include + #include + #include + #include +--- a/arch/x86/kernel/cpu/transmeta.c ++++ b/arch/x86/kernel/cpu/transmeta.c +@@ -1,6 +1,6 @@ + #include + #include +-#include ++#include + #include + #include "cpu.h" + +--- a/arch/x86/kernel/e820.c ++++ b/arch/x86/kernel/e820.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + /* + * The e820 map is the map that gets modified e.g. with command line parameters +--- a/arch/x86/kernel/head_32.S ++++ b/arch/x86/kernel/head_32.S +@@ -19,7 +19,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include +--- a/arch/x86/kernel/hpet.c ++++ b/arch/x86/kernel/hpet.c +@@ -12,6 +12,7 @@ + #include + #include + ++#include + #include + #include + #include +--- a/arch/x86/kernel/msr.c ++++ b/arch/x86/kernel/msr.c +@@ -40,7 +40,7 @@ + #include + #include + +-#include ++#include + #include + + static struct class *msr_class; +--- a/arch/x86/kernel/verify_cpu.S ++++ b/arch/x86/kernel/verify_cpu.S +@@ -30,7 +30,7 @@ + * appropriately. Either display a message or halt. + */ + +-#include ++#include + #include + + verify_cpu: +--- a/arch/x86/lib/clear_page_64.S ++++ b/arch/x86/lib/clear_page_64.S +@@ -1,5 +1,5 @@ + #include +-#include ++#include + #include + + /* +--- a/arch/x86/lib/copy_page_64.S ++++ b/arch/x86/lib/copy_page_64.S +@@ -1,7 +1,7 @@ + /* Written 2003 by Andi Kleen, based on a kernel by Evandro Menezes */ + + #include +-#include ++#include + #include + + /* +--- a/arch/x86/lib/copy_user_64.S ++++ b/arch/x86/lib/copy_user_64.S +@@ -10,7 +10,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include +--- a/arch/x86/lib/memcpy_64.S ++++ b/arch/x86/lib/memcpy_64.S +@@ -1,7 +1,7 @@ + /* Copyright 2002 Andi Kleen */ + + #include +-#include ++#include + #include + + /* +--- a/arch/x86/lib/memmove_64.S ++++ b/arch/x86/lib/memmove_64.S +@@ -6,7 +6,7 @@ + * - Copyright 2011 Fenghua Yu + */ + #include +-#include ++#include + #include + + #undef memmove +--- a/arch/x86/lib/memset_64.S ++++ b/arch/x86/lib/memset_64.S +@@ -1,7 +1,7 @@ + /* Copyright 2002 Andi Kleen, SuSE Labs */ + + #include +-#include ++#include + #include + + .weak memset +--- a/arch/x86/lib/retpoline.S ++++ b/arch/x86/lib/retpoline.S +@@ -3,7 +3,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include +--- a/arch/x86/mm/setup_nx.c ++++ b/arch/x86/mm/setup_nx.c +@@ -4,6 +4,7 @@ + + #include + #include ++#include + + static int disable_nx; + +--- a/arch/x86/oprofile/op_model_amd.c ++++ b/arch/x86/oprofile/op_model_amd.c +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + + #include "op_x86_model.h" + #include "op_counter.h" +--- a/arch/x86/um/asm/barrier.h ++++ b/arch/x86/um/asm/barrier.h +@@ -3,7 +3,7 @@ + + #include + #include +-#include ++#include + #include + #include + +--- a/lib/atomic64_test.c ++++ b/lib/atomic64_test.c +@@ -17,7 +17,7 @@ + #include + + #ifdef CONFIG_X86 +-#include /* for boot_cpu_has below */ ++#include /* for boot_cpu_has below */ + #endif + + #define TEST(bit, op, c_op, val) \ diff --git a/queue-4.4/x86-cpufeature-cleanup-get_cpu_cap.patch b/queue-4.4/x86-cpufeature-cleanup-get_cpu_cap.patch new file mode 100644 index 00000000000..dd0f91146e9 --- /dev/null +++ b/queue-4.4/x86-cpufeature-cleanup-get_cpu_cap.patch @@ -0,0 +1,201 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:09 -0700 +Subject: [PATCH 4.4.y 002/101] x86/cpufeature: Cleanup get_cpu_cap() +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Thomas Gleixner , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156036919.10043.1680497411878315509.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit 39c06df4dc10a41de5fe706f4378ee5f09beba73 upstream + +Add an enum for the ->x86_capability array indices and cleanup +get_cpu_cap() by killing some redundant local vars. + +Signed-off-by: Borislav Petkov +Link: http://lkml.kernel.org/r/1449481182-27541-3-git-send-email-bp@alien8.de +Signed-off-by: Thomas Gleixner +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 20 ++++++++++++++++ + arch/x86/kernel/cpu/centaur.c | 2 - + arch/x86/kernel/cpu/common.c | 47 +++++++++++++++++--------------------- + arch/x86/kernel/cpu/transmeta.c | 4 +-- + 4 files changed, 45 insertions(+), 28 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -299,6 +299,26 @@ + #include + #include + ++enum cpuid_leafs ++{ ++ CPUID_1_EDX = 0, ++ CPUID_8000_0001_EDX, ++ CPUID_8086_0001_EDX, ++ CPUID_LNX_1, ++ CPUID_1_ECX, ++ CPUID_C000_0001_EDX, ++ CPUID_8000_0001_ECX, ++ CPUID_LNX_2, ++ CPUID_LNX_3, ++ CPUID_7_0_EBX, ++ CPUID_D_1_EAX, ++ CPUID_F_0_EDX, ++ CPUID_F_1_EDX, ++ CPUID_8000_0008_EBX, ++ CPUID_6_EAX, ++ CPUID_8000_000A_EDX, ++}; ++ + #ifdef CONFIG_X86_FEATURE_NAMES + extern const char * const x86_cap_flags[NCAPINTS*32]; + extern const char * const x86_power_flags[32]; +--- a/arch/x86/kernel/cpu/centaur.c ++++ b/arch/x86/kernel/cpu/centaur.c +@@ -43,7 +43,7 @@ static void init_c3(struct cpuinfo_x86 * + /* store Centaur Extended Feature Flags as + * word 5 of the CPU capability bit array + */ +- c->x86_capability[5] = cpuid_edx(0xC0000001); ++ c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); + } + #ifdef CONFIG_X86_32 + /* Cyrix III family needs CX8 & PGE explicitly enabled. */ +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -676,52 +676,47 @@ static void apply_forced_caps(struct cpu + + void get_cpu_cap(struct cpuinfo_x86 *c) + { +- u32 tfms, xlvl; +- u32 ebx; ++ u32 eax, ebx, ecx, edx; + + /* Intel-defined flags: level 0x00000001 */ + if (c->cpuid_level >= 0x00000001) { +- u32 capability, excap; ++ cpuid(0x00000001, &eax, &ebx, &ecx, &edx); + +- cpuid(0x00000001, &tfms, &ebx, &excap, &capability); +- c->x86_capability[0] = capability; +- c->x86_capability[4] = excap; ++ c->x86_capability[CPUID_1_ECX] = ecx; ++ c->x86_capability[CPUID_1_EDX] = edx; + } + + /* Additional Intel-defined flags: level 0x00000007 */ + if (c->cpuid_level >= 0x00000007) { +- u32 eax, ebx, ecx, edx; +- + cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); + +- c->x86_capability[9] = ebx; ++ c->x86_capability[CPUID_7_0_EBX] = ebx; + +- c->x86_capability[14] = cpuid_eax(0x00000006); ++ c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); + } + + /* Extended state features: level 0x0000000d */ + if (c->cpuid_level >= 0x0000000d) { +- u32 eax, ebx, ecx, edx; +- + cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); + +- c->x86_capability[10] = eax; ++ c->x86_capability[CPUID_D_1_EAX] = eax; + } + + /* Additional Intel-defined flags: level 0x0000000F */ + if (c->cpuid_level >= 0x0000000F) { +- u32 eax, ebx, ecx, edx; + + /* QoS sub-leaf, EAX=0Fh, ECX=0 */ + cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); +- c->x86_capability[11] = edx; ++ c->x86_capability[CPUID_F_0_EDX] = edx; ++ + if (cpu_has(c, X86_FEATURE_CQM_LLC)) { + /* will be overridden if occupancy monitoring exists */ + c->x86_cache_max_rmid = ebx; + + /* QoS sub-leaf, EAX=0Fh, ECX=1 */ + cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); +- c->x86_capability[12] = edx; ++ c->x86_capability[CPUID_F_1_EDX] = edx; ++ + if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { + c->x86_cache_max_rmid = ecx; + c->x86_cache_occ_scale = ebx; +@@ -733,22 +728,24 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + } + + /* AMD-defined flags: level 0x80000001 */ +- xlvl = cpuid_eax(0x80000000); +- c->extended_cpuid_level = xlvl; ++ eax = cpuid_eax(0x80000000); ++ c->extended_cpuid_level = eax; ++ ++ if ((eax & 0xffff0000) == 0x80000000) { ++ if (eax >= 0x80000001) { ++ cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + +- if ((xlvl & 0xffff0000) == 0x80000000) { +- if (xlvl >= 0x80000001) { +- c->x86_capability[1] = cpuid_edx(0x80000001); +- c->x86_capability[6] = cpuid_ecx(0x80000001); ++ c->x86_capability[CPUID_8000_0001_ECX] = ecx; ++ c->x86_capability[CPUID_8000_0001_EDX] = edx; + } + } + + if (c->extended_cpuid_level >= 0x80000008) { +- u32 eax = cpuid_eax(0x80000008); ++ cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + + c->x86_virt_bits = (eax >> 8) & 0xff; + c->x86_phys_bits = eax & 0xff; +- c->x86_capability[13] = cpuid_ebx(0x80000008); ++ c->x86_capability[CPUID_8000_0008_EBX] = ebx; + } + #ifdef CONFIG_X86_32 + else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) +@@ -759,7 +756,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + c->x86_power = cpuid_edx(0x80000007); + + if (c->extended_cpuid_level >= 0x8000000a) +- c->x86_capability[15] = cpuid_edx(0x8000000a); ++ c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); + + init_scattered_cpuid_features(c); + } +--- a/arch/x86/kernel/cpu/transmeta.c ++++ b/arch/x86/kernel/cpu/transmeta.c +@@ -12,7 +12,7 @@ static void early_init_transmeta(struct + xlvl = cpuid_eax(0x80860000); + if ((xlvl & 0xffff0000) == 0x80860000) { + if (xlvl >= 0x80860001) +- c->x86_capability[2] = cpuid_edx(0x80860001); ++ c->x86_capability[CPUID_8086_0001_EDX] = cpuid_edx(0x80860001); + } + } + +@@ -82,7 +82,7 @@ static void init_transmeta(struct cpuinf + /* Unhide possibly hidden capability flags */ + rdmsr(0x80860004, cap_mask, uk); + wrmsr(0x80860004, ~0, uk); +- c->x86_capability[0] = cpuid_edx(0x00000001); ++ c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001); + wrmsr(0x80860004, cap_mask, uk); + + /* All Transmeta CPUs have a constant TSC */ diff --git a/queue-4.4/x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch b/queue-4.4/x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch new file mode 100644 index 00000000000..15e423bd3e9 --- /dev/null +++ b/queue-4.4/x86-cpufeature-get-rid-of-the-non-asm-goto-variant.patch @@ -0,0 +1,126 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:10 -0700 +Subject: [PATCH 4.4.y 009/101] x86/cpufeature: Get rid of the non-asm goto variant +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: "H. Peter Anvin" , Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156043045.10043.1332068874731180029.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit a362bf9f5e7dd659b96d01382da7b855f4e5a7a1 upstream + +I can simply quote hpa from the mail: + + "Get rid of the non-asm goto variant and just fall back to + dynamic if asm goto is unavailable. It doesn't make any sense, + really, if it is supposed to be safe, and by now the asm + goto-capable gcc is in more wide use. (Originally the gcc 3.x + fallback to pure dynamic didn't exist, either.)" + +Booy, am I lazy. + +Cleanup the whole CC_HAVE_ASM_GOTO ifdeffery too, while at it. + +Suggested-by: H. Peter Anvin +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/20160127084325.GB30712@pd.tnic +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 49 +++----------------------------------- + 1 file changed, 5 insertions(+), 44 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -131,17 +131,16 @@ extern const char * const x86_bug_flags[ + * fast paths and boot_cpu_has() otherwise! + */ + +-#if __GNUC__ >= 4 && defined(CONFIG_X86_FAST_FEATURE_TESTS) ++#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) + extern bool __static_cpu_has(u16 bit); + + /* + * Static testing of CPU features. Used the same as boot_cpu_has(). +- * These are only valid after alternatives have run, but will statically +- * patch the target code for additional performance. ++ * These will statically patch the target code for additional ++ * performance. + */ + static __always_inline __pure bool _static_cpu_has(u16 bit) + { +-#ifdef CC_HAVE_ASM_GOTO + asm_volatile_goto("1: jmp %l[t_dynamic]\n" + "2:\n" + ".skip -(((5f-4f) - (2b-1b)) > 0) * " +@@ -174,45 +173,6 @@ static __always_inline __pure bool _stat + return false; + t_dynamic: + return __static_cpu_has(bit); +-#else +- u8 flag; +- /* Open-coded due to __stringify() in ALTERNATIVE() */ +- asm volatile("1: movb $2,%0\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" /* src offset */ +- " .long 3f - .\n" /* repl offset */ +- " .word %P2\n" /* always replace */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 4f - 3f\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "3: movb $0,%0\n" +- "4:\n" +- ".previous\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" /* src offset */ +- " .long 5f - .\n" /* repl offset */ +- " .word %P1\n" /* feature bit */ +- " .byte 4b - 3b\n" /* src len */ +- " .byte 6f - 5f\n" /* repl len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "5: movb $1,%0\n" +- "6:\n" +- ".previous\n" +- : "=qm" (flag) +- : "i" (bit), "i" (X86_FEATURE_ALWAYS)); +- return (flag == 2 ? __static_cpu_has(bit) : flag); +-#endif /* CC_HAVE_ASM_GOTO */ + } + + #define static_cpu_has(bit) \ +@@ -223,7 +183,8 @@ static __always_inline __pure bool _stat + ) + #else + /* +- * gcc 3.x is too stupid to do the static test; fall back to dynamic. ++ * Fall back to dynamic for gcc versions which don't support asm goto. Should be ++ * a minority now anyway. + */ + #define static_cpu_has(bit) boot_cpu_has(bit) + #endif diff --git a/queue-4.4/x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch b/queue-4.4/x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch new file mode 100644 index 00000000000..a4fb70baef1 --- /dev/null +++ b/queue-4.4/x86-cpufeature-make-sure-disabled-required-macros-are-updated.patch @@ -0,0 +1,99 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:49 -0700 +Subject: [PATCH 4.4.y 020/101] x86/cpufeature: Make sure DISABLED/REQUIRED macros are updated +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Dave Hansen , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , "H. Peter Anvin" , Josh Poimboeuf , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156052894.10043.16445037521492315697.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit 1e61f78baf893c7eb49f633d23ccbb420c8f808e upstream + +x86 has two macros which allow us to evaluate some CPUID-based +features at compile time: + + REQUIRED_MASK_BIT_SET() + DISABLED_MASK_BIT_SET() + +They're both defined by having the compiler check the bit +argument against some constant masks of features. + +But, when adding new CPUID leaves, we need to check new words +for these macros. So make sure that those macros and the +REQUIRED_MASK* and DISABLED_MASK* get updated when necessary. + +This looks kinda silly to have an open-coded value ("18" in +this case) open-coded in 5 places in the code. But, we really do +need 5 places updated when NCAPINTS gets bumped, so now we just +force the issue. + +Signed-off-by: Dave Hansen +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Josh Poimboeuf +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/20160629200108.92466F6F@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 8 ++++++-- + arch/x86/include/asm/disabled-features.h | 1 + + arch/x86/include/asm/required-features.h | 1 + + 3 files changed, 8 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -67,7 +67,9 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ + (((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ + (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) || \ +- (((bit)>>5)==17 && (1UL<<((bit)&31) & REQUIRED_MASK17))) ++ (((bit)>>5)==17 && (1UL<<((bit)&31) & REQUIRED_MASK17)) || \ ++ REQUIRED_MASK_CHECK || \ ++ BUILD_BUG_ON_ZERO(NCAPINTS != 18)) + + #define DISABLED_MASK_BIT_SET(bit) \ + ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ +@@ -87,7 +89,9 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ + (((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ + (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) || \ +- (((bit)>>5)==17 && (1UL<<((bit)&31) & DISABLED_MASK17))) ++ (((bit)>>5)==17 && (1UL<<((bit)&31) & DISABLED_MASK17)) || \ ++ DISABLED_MASK_CHECK || \ ++ BUILD_BUG_ON_ZERO(NCAPINTS != 18)) + + #define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ +--- a/arch/x86/include/asm/disabled-features.h ++++ b/arch/x86/include/asm/disabled-features.h +@@ -59,5 +59,6 @@ + #define DISABLED_MASK15 0 + #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) + #define DISABLED_MASK17 0 ++#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) + + #endif /* _ASM_X86_DISABLED_FEATURES_H */ +--- a/arch/x86/include/asm/required-features.h ++++ b/arch/x86/include/asm/required-features.h +@@ -100,5 +100,6 @@ + #define REQUIRED_MASK15 0 + #define REQUIRED_MASK16 0 + #define REQUIRED_MASK17 0 ++#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) + + #endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/queue-4.4/x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch b/queue-4.4/x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch new file mode 100644 index 00000000000..40e02f7c261 --- /dev/null +++ b/queue-4.4/x86-cpufeature-move-some-of-the-scattered-feature-bits-to-x86_capability.patch @@ -0,0 +1,178 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:01 -0700 +Subject: [PATCH 4.4.y 001/101] x86/cpufeature: Move some of the scattered feature bits to x86_capability +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Thomas Gleixner , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156036133.10043.7697291242387530023.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit 2ccd71f1b278d450a6f8c8c737c7fe237ca06dc6 upstream + +Turn the CPUID leafs which are proper CPUID feature bit leafs into +separate ->x86_capability words. + +Signed-off-by: Borislav Petkov +Link: http://lkml.kernel.org/r/1449481182-27541-2-git-send-email-bp@alien8.de +Signed-off-by: Thomas Gleixner +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 54 ++++++++++++++++++++++---------------- + arch/x86/kernel/cpu/common.c | 5 +++ + arch/x86/kernel/cpu/scattered.c | 20 -------------- + 3 files changed, 37 insertions(+), 42 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -12,7 +12,7 @@ + #include + #endif + +-#define NCAPINTS 14 /* N 32-bit words worth of info */ ++#define NCAPINTS 16 /* N 32-bit words worth of info */ + #define NBUGINTS 1 /* N 32-bit bug flags */ + + /* +@@ -181,23 +181,18 @@ + + /* + * Auxiliary flags: Linux defined - For features scattered in various +- * CPUID levels like 0x6, 0xA etc, word 7 ++ * CPUID levels like 0x6, 0xA etc, word 7. ++ * ++ * Reuse free bits when adding new feature flags! + */ +-#define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ +-#define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ ++ + #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ + #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ + #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */ +-#define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ +-#define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ +-#define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ ++ + #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ + #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ +-#define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ +-#define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ +-#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ +-#define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ +-#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ ++ + #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ + #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ + +@@ -212,16 +207,7 @@ + #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ + #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ + #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ +-#define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ +-#define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ +-#define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ +-#define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ +-#define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ +-#define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ +-#define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ +-#define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ +-#define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ +-#define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ ++ + #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ + #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ + +@@ -266,6 +252,30 @@ + /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ + #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ + ++/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ ++#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ ++#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ ++#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ ++#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ ++#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ ++#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ ++#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ ++#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ ++#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ ++#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ ++ ++/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ ++#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ ++#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ ++#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ ++#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ ++#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ ++#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ ++#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ ++#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ ++#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ ++#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ ++ + /* + * BUG word(s) + */ +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -695,6 +695,8 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); + + c->x86_capability[9] = ebx; ++ ++ c->x86_capability[14] = cpuid_eax(0x00000006); + } + + /* Extended state features: level 0x0000000d */ +@@ -756,6 +758,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + if (c->extended_cpuid_level >= 0x80000007) + c->x86_power = cpuid_edx(0x80000007); + ++ if (c->extended_cpuid_level >= 0x8000000a) ++ c->x86_capability[15] = cpuid_edx(0x8000000a); ++ + init_scattered_cpuid_features(c); + } + +--- a/arch/x86/kernel/cpu/scattered.c ++++ b/arch/x86/kernel/cpu/scattered.c +@@ -31,32 +31,12 @@ void init_scattered_cpuid_features(struc + const struct cpuid_bit *cb; + + static const struct cpuid_bit cpuid_bits[] = { +- { X86_FEATURE_DTHERM, CR_EAX, 0, 0x00000006, 0 }, +- { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006, 0 }, +- { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006, 0 }, +- { X86_FEATURE_PLN, CR_EAX, 4, 0x00000006, 0 }, +- { X86_FEATURE_PTS, CR_EAX, 6, 0x00000006, 0 }, +- { X86_FEATURE_HWP, CR_EAX, 7, 0x00000006, 0 }, +- { X86_FEATURE_HWP_NOTIFY, CR_EAX, 8, 0x00000006, 0 }, +- { X86_FEATURE_HWP_ACT_WINDOW, CR_EAX, 9, 0x00000006, 0 }, +- { X86_FEATURE_HWP_EPP, CR_EAX,10, 0x00000006, 0 }, +- { X86_FEATURE_HWP_PKG_REQ, CR_EAX,11, 0x00000006, 0 }, + { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, + { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, + { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, + { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, + { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, +- { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 }, +- { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 }, +- { X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 }, +- { X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a, 0 }, +- { X86_FEATURE_TSCRATEMSR, CR_EDX, 4, 0x8000000a, 0 }, +- { X86_FEATURE_VMCBCLEAN, CR_EDX, 5, 0x8000000a, 0 }, +- { X86_FEATURE_FLUSHBYASID, CR_EDX, 6, 0x8000000a, 0 }, +- { X86_FEATURE_DECODEASSISTS, CR_EDX, 7, 0x8000000a, 0 }, +- { X86_FEATURE_PAUSEFILTER, CR_EDX,10, 0x8000000a, 0 }, +- { X86_FEATURE_PFTHRESHOLD, CR_EDX,12, 0x8000000a, 0 }, + { 0, 0, 0, 0, 0 } + }; + diff --git a/queue-4.4/x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch b/queue-4.4/x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch new file mode 100644 index 00000000000..e87459a4e84 --- /dev/null +++ b/queue-4.4/x86-cpufeature-replace-the-old-static_cpu_has-with-safe-variant.patch @@ -0,0 +1,343 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:01 -0700 +Subject: [PATCH 4.4.y 008/101] x86/cpufeature: Replace the old static_cpu_has() with safe variant +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156042157.10043.10075641675916541541.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit bc696ca05f5a8927329ec276a892341e006b00ba upstream + +So the old one didn't work properly before alternatives had run. +And it was supposed to provide an optimized JMP because the +assumption was that the offset it is jumping to is within a +signed byte and thus a two-byte JMP. + +So I did an x86_64 allyesconfig build and dumped all possible +sites where static_cpu_has() was used. The optimization amounted +to all in all 12(!) places where static_cpu_has() had generated +a 2-byte JMP. Which has saved us a whopping 36 bytes! + +This clearly is not worth the trouble so we can remove it. The +only place where the optimization might count - in __switch_to() +- we will handle differently. But that's not subject of this +patch. + +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1453842730-28463-6-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/Kconfig.debug | 10 --- + arch/x86/include/asm/cpufeature.h | 100 ++--------------------------------- + arch/x86/include/asm/fpu/internal.h | 12 ++-- + arch/x86/kernel/apic/apic_numachip.c | 4 - + arch/x86/kernel/cpu/common.c | 12 ---- + arch/x86/kernel/vm86_32.c | 2 + fs/btrfs/disk-io.c | 2 + 7 files changed, 19 insertions(+), 123 deletions(-) + +--- a/arch/x86/Kconfig.debug ++++ b/arch/x86/Kconfig.debug +@@ -367,16 +367,6 @@ config DEBUG_IMR_SELFTEST + + If unsure say N here. + +-config X86_DEBUG_STATIC_CPU_HAS +- bool "Debug alternatives" +- depends on DEBUG_KERNEL +- ---help--- +- This option causes additional code to be generated which +- fails if static_cpu_has() is used before alternatives have +- run. +- +- If unsure, say N. +- + config X86_DEBUG_FPU + bool "Debug the x86 FPU code" + depends on DEBUG_KERNEL +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -127,103 +127,19 @@ extern const char * const x86_bug_flags[ + #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) + #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) + /* +- * Do not add any more of those clumsy macros - use static_cpu_has_safe() for ++ * Do not add any more of those clumsy macros - use static_cpu_has() for + * fast paths and boot_cpu_has() otherwise! + */ + + #if __GNUC__ >= 4 && defined(CONFIG_X86_FAST_FEATURE_TESTS) +-extern void warn_pre_alternatives(void); +-extern bool __static_cpu_has_safe(u16 bit); ++extern bool __static_cpu_has(u16 bit); + + /* + * Static testing of CPU features. Used the same as boot_cpu_has(). + * These are only valid after alternatives have run, but will statically + * patch the target code for additional performance. + */ +-static __always_inline __pure bool __static_cpu_has(u16 bit) +-{ +-#ifdef CC_HAVE_ASM_GOTO +- +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +- +- /* +- * Catch too early usage of this before alternatives +- * have run. +- */ +- asm_volatile_goto("1: jmp %l[t_warn]\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 0\n" /* no replacement */ +- " .word %P0\n" /* 1: do replace */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 0\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- /* skipping size check since replacement size = 0 */ +- : : "i" (X86_FEATURE_ALWAYS) : : t_warn); +- +-#endif +- +- asm_volatile_goto("1: jmp %l[t_no]\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 0\n" /* no replacement */ +- " .word %P0\n" /* feature bit */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 0\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- /* skipping size check since replacement size = 0 */ +- : : "i" (bit) : : t_no); +- return true; +- t_no: +- return false; +- +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +- t_warn: +- warn_pre_alternatives(); +- return false; +-#endif +- +-#else /* CC_HAVE_ASM_GOTO */ +- +- u8 flag; +- /* Open-coded due to __stringify() in ALTERNATIVE() */ +- asm volatile("1: movb $0,%0\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 3f - .\n" +- " .word %P1\n" /* feature bit */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 4f - 3f\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "3: movb $1,%0\n" +- "4:\n" +- ".previous\n" +- : "=qm" (flag) : "i" (bit)); +- return flag; +- +-#endif /* CC_HAVE_ASM_GOTO */ +-} +- +-#define static_cpu_has(bit) \ +-( \ +- __builtin_constant_p(boot_cpu_has(bit)) ? \ +- boot_cpu_has(bit) : \ +- __builtin_constant_p(bit) ? \ +- __static_cpu_has(bit) : \ +- boot_cpu_has(bit) \ +-) +- +-static __always_inline __pure bool _static_cpu_has_safe(u16 bit) ++static __always_inline __pure bool _static_cpu_has(u16 bit) + { + #ifdef CC_HAVE_ASM_GOTO + asm_volatile_goto("1: jmp %l[t_dynamic]\n" +@@ -257,7 +173,7 @@ static __always_inline __pure bool _stat + t_no: + return false; + t_dynamic: +- return __static_cpu_has_safe(bit); ++ return __static_cpu_has(bit); + #else + u8 flag; + /* Open-coded due to __stringify() in ALTERNATIVE() */ +@@ -295,22 +211,21 @@ static __always_inline __pure bool _stat + ".previous\n" + : "=qm" (flag) + : "i" (bit), "i" (X86_FEATURE_ALWAYS)); +- return (flag == 2 ? __static_cpu_has_safe(bit) : flag); ++ return (flag == 2 ? __static_cpu_has(bit) : flag); + #endif /* CC_HAVE_ASM_GOTO */ + } + +-#define static_cpu_has_safe(bit) \ ++#define static_cpu_has(bit) \ + ( \ + __builtin_constant_p(boot_cpu_has(bit)) ? \ + boot_cpu_has(bit) : \ +- _static_cpu_has_safe(bit) \ ++ _static_cpu_has(bit) \ + ) + #else + /* + * gcc 3.x is too stupid to do the static test; fall back to dynamic. + */ + #define static_cpu_has(bit) boot_cpu_has(bit) +-#define static_cpu_has_safe(bit) boot_cpu_has(bit) + #endif + + #define cpu_has_bug(c, bit) cpu_has(c, (bit)) +@@ -318,7 +233,6 @@ static __always_inline __pure bool _stat + #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) + + #define static_cpu_has_bug(bit) static_cpu_has((bit)) +-#define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) + #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) + + #define MAX_CPU_FEATURES (NCAPINTS * 32) +--- a/arch/x86/include/asm/fpu/internal.h ++++ b/arch/x86/include/asm/fpu/internal.h +@@ -64,17 +64,17 @@ static __always_inline __pure bool use_e + + static __always_inline __pure bool use_xsaveopt(void) + { +- return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); ++ return static_cpu_has(X86_FEATURE_XSAVEOPT); + } + + static __always_inline __pure bool use_xsave(void) + { +- return static_cpu_has_safe(X86_FEATURE_XSAVE); ++ return static_cpu_has(X86_FEATURE_XSAVE); + } + + static __always_inline __pure bool use_fxsr(void) + { +- return static_cpu_has_safe(X86_FEATURE_FXSR); ++ return static_cpu_has(X86_FEATURE_FXSR); + } + + /* +@@ -301,7 +301,7 @@ static inline void copy_xregs_to_kernel_ + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (static_cpu_has_safe(X86_FEATURE_XSAVES)) ++ if (static_cpu_has(X86_FEATURE_XSAVES)) + XSTATE_OP(XSAVES, xstate, lmask, hmask, err); + else + XSTATE_OP(XSAVE, xstate, lmask, hmask, err); +@@ -323,7 +323,7 @@ static inline void copy_kernel_to_xregs_ + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (static_cpu_has_safe(X86_FEATURE_XSAVES)) ++ if (static_cpu_has(X86_FEATURE_XSAVES)) + XSTATE_OP(XRSTORS, xstate, lmask, hmask, err); + else + XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); +@@ -461,7 +461,7 @@ static inline void copy_kernel_to_fpregs + * pending. Clear the x87 state here by setting it to fixed values. + * "m" is a random variable that should be in L1. + */ +- if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { ++ if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) { + asm volatile( + "fnclex\n\t" + "emms\n\t" +--- a/arch/x86/kernel/apic/apic_numachip.c ++++ b/arch/x86/kernel/apic/apic_numachip.c +@@ -30,7 +30,7 @@ static unsigned int numachip1_get_apic_i + unsigned long value; + unsigned int id = (x >> 24) & 0xff; + +- if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) { ++ if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { + rdmsrl(MSR_FAM10H_NODE_ID, value); + id |= (value << 2) & 0xff00; + } +@@ -178,7 +178,7 @@ static void fixup_cpu_id(struct cpuinfo_ + this_cpu_write(cpu_llc_id, node); + + /* Account for nodes per socket in multi-core-module processors */ +- if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) { ++ if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { + rdmsrl(MSR_FAM10H_NODE_ID, val); + nodes = ((val >> 3) & 7) + 1; + } +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -1576,19 +1576,11 @@ void cpu_init(void) + } + #endif + +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +-void warn_pre_alternatives(void) +-{ +- WARN(1, "You're using static_cpu_has before alternatives have run!\n"); +-} +-EXPORT_SYMBOL_GPL(warn_pre_alternatives); +-#endif +- +-inline bool __static_cpu_has_safe(u16 bit) ++inline bool __static_cpu_has(u16 bit) + { + return boot_cpu_has(bit); + } +-EXPORT_SYMBOL_GPL(__static_cpu_has_safe); ++EXPORT_SYMBOL_GPL(__static_cpu_has); + + static void bsp_resume(void) + { +--- a/arch/x86/kernel/vm86_32.c ++++ b/arch/x86/kernel/vm86_32.c +@@ -358,7 +358,7 @@ static long do_sys_vm86(struct vm86plus_ + /* make room for real-mode segments */ + tsk->thread.sp0 += 16; + +- if (static_cpu_has_safe(X86_FEATURE_SEP)) ++ if (static_cpu_has(X86_FEATURE_SEP)) + tsk->thread.sysenter_cs = 0; + + load_sp0(tss, &tsk->thread); +--- a/fs/btrfs/disk-io.c ++++ b/fs/btrfs/disk-io.c +@@ -923,7 +923,7 @@ static int check_async_write(struct inod + if (bio_flags & EXTENT_BIO_TREE_LOG) + return 0; + #ifdef CONFIG_X86 +- if (static_cpu_has_safe(X86_FEATURE_XMM4_2)) ++ if (static_cpu_has(X86_FEATURE_XMM4_2)) + return 0; + #endif + return 1; diff --git a/queue-4.4/x86-cpufeature-speed-up-cpu_feature_enabled.patch b/queue-4.4/x86-cpufeature-speed-up-cpu_feature_enabled.patch new file mode 100644 index 00000000000..a1c0312b90b --- /dev/null +++ b/queue-4.4/x86-cpufeature-speed-up-cpu_feature_enabled.patch @@ -0,0 +1,62 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:55 -0700 +Subject: [PATCH 4.4.y 014/101] x86/cpufeature: Speed up cpu_feature_enabled() +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Joerg Roedel , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156047551.10043.15245931405054039621.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit f2cc8e0791c70833758101d9756609a08dd601ec upstream + +When GCC cannot do constant folding for this macro, it falls back to +cpu_has(). But static_cpu_has() is optimal and it works at all times +now. So use it and speedup the fallback case. + +Before we had this: + + mov 0x99d674(%rip),%rdx # ffffffff81b0d9f4 + shr $0x2e,%rdx + and $0x1,%edx + jne ffffffff811704e9 + +After alternatives patching, it turns into: + + jmp 0xffffffff81170390 + nopl (%rax) + ... + callq ffffffff81056e00 +ffffffff81170390: mov 0x170(%r12),%rdi + +Signed-off-by: Borislav Petkov +Cc: Joerg Roedel +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1455578358-28347-1-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -88,8 +88,7 @@ extern const char * const x86_bug_flags[ + * is not relevant. + */ + #define cpu_feature_enabled(bit) \ +- (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ +- cpu_has(&boot_cpu_data, bit)) ++ (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit)) + + #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) + diff --git a/queue-4.4/x86-cpufeature-update-cpufeaure-macros.patch b/queue-4.4/x86-cpufeature-update-cpufeaure-macros.patch new file mode 100644 index 00000000000..e7676e188fb --- /dev/null +++ b/queue-4.4/x86-cpufeature-update-cpufeaure-macros.patch @@ -0,0 +1,85 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:40 -0700 +Subject: [PATCH 4.4.y 019/101] x86/cpufeature: Update cpufeaure macros +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Dave Hansen , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , "H. Peter Anvin" , Josh Poimboeuf , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156051993.10043.4437955688906865472.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit 6e17cb9c2d5efd8fcc3934e983733302b9912ff8 upstream + +We had a new CPUID "NCAPINT" word added, but the REQUIRED_MASK and +DISABLED_MASK macros did not get updated. Update them. + +None of the features was needed in these masks, so there was no +harm, but we should keep them updated anyway. + +Signed-off-by: Dave Hansen +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Josh Poimboeuf +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/20160629200107.8D3C9A31@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 6 ++++-- + arch/x86/include/asm/disabled-features.h | 1 + + arch/x86/include/asm/required-features.h | 1 + + 3 files changed, 6 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -66,7 +66,8 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ + (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ + (((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ +- (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) ++ (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) || \ ++ (((bit)>>5)==17 && (1UL<<((bit)&31) & REQUIRED_MASK17))) + + #define DISABLED_MASK_BIT_SET(bit) \ + ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ +@@ -85,7 +86,8 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ + (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ + (((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ +- (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) ++ (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) || \ ++ (((bit)>>5)==17 && (1UL<<((bit)&31) & DISABLED_MASK17))) + + #define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ +--- a/arch/x86/include/asm/disabled-features.h ++++ b/arch/x86/include/asm/disabled-features.h +@@ -58,5 +58,6 @@ + #define DISABLED_MASK14 0 + #define DISABLED_MASK15 0 + #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) ++#define DISABLED_MASK17 0 + + #endif /* _ASM_X86_DISABLED_FEATURES_H */ +--- a/arch/x86/include/asm/required-features.h ++++ b/arch/x86/include/asm/required-features.h +@@ -99,5 +99,6 @@ + #define REQUIRED_MASK14 0 + #define REQUIRED_MASK15 0 + #define REQUIRED_MASK16 0 ++#define REQUIRED_MASK17 0 + + #endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/queue-4.4/x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch b/queue-4.4/x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch new file mode 100644 index 00000000000..511149dfb92 --- /dev/null +++ b/queue-4.4/x86-cpufeature-x86-mm-pkeys-add-protection-keys-related-cpuid-definitions.patch @@ -0,0 +1,226 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:04 -0700 +Subject: [PATCH 4.4.y 015/101] x86/cpufeature, x86/mm/pkeys: Add protection keys related CPUID definitions +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Dave Hansen , Thomas Gleixner , Andrew Morton , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Rik van Riel , linux-mm@kvack.org, Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156048404.10043.9924019452796692128.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit dfb4a70f20c5b3880da56ee4c9484bdb4e8f1e65 upstream + +There are two CPUID bits for protection keys. One is for whether +the CPU contains the feature, and the other will appear set once +the OS enables protection keys. Specifically: + + Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable + Protection keys (and the RDPKRU/WRPKRU instructions) + +This is because userspace can not see CR4 contents, but it can +see CPUID contents. + +X86_FEATURE_PKU is referred to as "PKU" in the hardware documentation: + + CPUID.(EAX=07H,ECX=0H):ECX.PKU [bit 3] + +X86_FEATURE_OSPKE is "OSPKU": + + CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4] + +These are the first CPU features which need to look at the +ECX word in CPUID leaf 0x7, so this patch also includes +fetching that word in to the cpuinfo->x86_capability[] array. + +Add it to the disabled-features mask when its config option is +off. Even though we are not using it here, we also extend the +REQUIRED_MASK_BIT_SET() macro to keep it mirroring the +DISABLED_MASK_BIT_SET() version. + +This means that in almost all code, you should use: + + cpu_has(c, X86_FEATURE_PKU) + +and *not* the CONFIG option. + +Signed-off-by: Dave Hansen +Reviewed-by: Thomas Gleixner +Cc: Andrew Morton +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Rik van Riel +Cc: linux-mm@kvack.org +Link: http://lkml.kernel.org/r/20160212210201.7714C250@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 59 ++++++++++++++++++++----------- + arch/x86/include/asm/cpufeatures.h | 2 - + arch/x86/include/asm/disabled-features.h | 15 +++++++ + arch/x86/include/asm/required-features.h | 7 +++ + arch/x86/kernel/cpu/common.c | 1 + 5 files changed, 63 insertions(+), 21 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -26,6 +26,7 @@ enum cpuid_leafs + CPUID_8000_0008_EBX, + CPUID_6_EAX, + CPUID_8000_000A_EDX, ++ CPUID_7_ECX, + }; + + #ifdef CONFIG_X86_FEATURE_NAMES +@@ -48,28 +49,42 @@ extern const char * const x86_bug_flags[ + test_bit(bit, (unsigned long *)((c)->x86_capability)) + + #define REQUIRED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) ++ ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) || \ ++ (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) || \ ++ (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) || \ ++ (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) || \ ++ (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) || \ ++ (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) || \ ++ (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) || \ ++ (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) || \ ++ (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) || \ ++ (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) || \ ++ (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) || \ ++ (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \ ++ (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ ++ (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) + + #define DISABLED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) ++ ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ ++ (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) || \ ++ (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) || \ ++ (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) || \ ++ (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) || \ ++ (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) || \ ++ (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) || \ ++ (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) || \ ++ (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) || \ ++ (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) || \ ++ (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) || \ ++ (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \ ++ (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ ++ (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ ++ (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) + + #define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ +@@ -79,6 +94,10 @@ extern const char * const x86_bug_flags[ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ + x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) + ++/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ ++#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ ++#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ ++ + /* + * This macro is for detection of features which need kernel + * infrastructure to be used. It may *not* directly test the CPU +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -12,7 +12,7 @@ + /* + * Defines x86 CPU feature bits + */ +-#define NCAPINTS 16 /* N 32-bit words worth of info */ ++#define NCAPINTS 17 /* N 32-bit words worth of info */ + #define NBUGINTS 1 /* N 32-bit bug flags */ + + /* +--- a/arch/x86/include/asm/disabled-features.h ++++ b/arch/x86/include/asm/disabled-features.h +@@ -30,6 +30,14 @@ + # define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) + #endif /* CONFIG_X86_64 */ + ++#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS ++# define DISABLE_PKU (1<<(X86_FEATURE_PKU)) ++# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE)) ++#else ++# define DISABLE_PKU 0 ++# define DISABLE_OSPKE 0 ++#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ ++ + /* + * Make sure to add features to the correct mask + */ +@@ -43,5 +51,12 @@ + #define DISABLED_MASK7 0 + #define DISABLED_MASK8 0 + #define DISABLED_MASK9 (DISABLE_MPX) ++#define DISABLED_MASK10 0 ++#define DISABLED_MASK11 0 ++#define DISABLED_MASK12 0 ++#define DISABLED_MASK13 0 ++#define DISABLED_MASK14 0 ++#define DISABLED_MASK15 0 ++#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) + + #endif /* _ASM_X86_DISABLED_FEATURES_H */ +--- a/arch/x86/include/asm/required-features.h ++++ b/arch/x86/include/asm/required-features.h +@@ -92,5 +92,12 @@ + #define REQUIRED_MASK7 0 + #define REQUIRED_MASK8 0 + #define REQUIRED_MASK9 0 ++#define REQUIRED_MASK10 0 ++#define REQUIRED_MASK11 0 ++#define REQUIRED_MASK12 0 ++#define REQUIRED_MASK13 0 ++#define REQUIRED_MASK14 0 ++#define REQUIRED_MASK15 0 ++#define REQUIRED_MASK16 0 + + #endif /* _ASM_X86_REQUIRED_FEATURES_H */ +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -693,6 +693,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + c->x86_capability[CPUID_7_0_EBX] = ebx; + + c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); ++ c->x86_capability[CPUID_7_ECX] = ecx; + } + + /* Extended state features: level 0x0000000d */ diff --git a/queue-4.4/x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch b/queue-4.4/x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch new file mode 100644 index 00000000000..f6c797edd3f --- /dev/null +++ b/queue-4.4/x86-cpufeature-x86-mm-pkeys-fix-broken-compile-time-disabling-of-pkeys.patch @@ -0,0 +1,104 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:30 -0700 +Subject: [PATCH 4.4.y 018/101] x86/cpufeature, x86/mm/pkeys: Fix broken compile-time disabling of pkeys +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Dave Hansen , Alexander Shishkin , Arnaldo Carvalho de Melo , Dave Hansen , Jiri Olsa , Linus Torvalds , Peter Zijlstra , Stephane Eranian , Thomas Gleixner , Vince Weaver , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156051091.10043.5709673765592963402.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit e8df1a95b685af84a81698199ee206e0e66a8b44 upstream + +When I added support for the Memory Protection Keys processor +feature, I had to reindent the REQUIRED/DISABLED_MASK macros, and +also consult the later cpufeature words. + +I'm not quite sure how I bungled it, but I consulted the wrong +word at the end. This only affected required or disabled cpu +features in cpufeature words 14, 15 and 16. So, only Protection +Keys itself was screwed over here. + +The result was that if you disabled pkeys in your .config, you +might still see some code show up that should have been compiled +out. There should be no functional problems, though. + +In verifying this patch I also realized that the DISABLE_PKU/OSPKE +macros were defined backwards and that the cpu_has() check in +setup_pku() was not doing the compile-time disabled checks. + +So also fix the macro for DISABLE_PKU/OSPKE and add a compile-time +check for pkeys being enabled in setup_pku(). + +Signed-off-by: Dave Hansen +Cc: +Cc: Alexander Shishkin +Cc: Arnaldo Carvalho de Melo +Cc: Dave Hansen +Cc: Jiri Olsa +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Fixes: dfb4a70f20c5 ("x86/cpufeature, x86/mm/pkeys: Add protection keys related CPUID definitions") +Link: http://lkml.kernel.org/r/20160513221328.C200930B@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 12 ++++++------ + arch/x86/include/asm/disabled-features.h | 6 +++--- + 2 files changed, 9 insertions(+), 9 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -64,9 +64,9 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \ + (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \ + (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ +- (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) ++ (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ ++ (((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ ++ (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) + + #define DISABLED_MASK_BIT_SET(bit) \ + ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ +@@ -83,9 +83,9 @@ extern const char * const x86_bug_flags[ + (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \ + (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \ + (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ +- (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ +- (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) ++ (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ ++ (((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ ++ (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) + + #define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ +--- a/arch/x86/include/asm/disabled-features.h ++++ b/arch/x86/include/asm/disabled-features.h +@@ -31,11 +31,11 @@ + #endif /* CONFIG_X86_64 */ + + #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS +-# define DISABLE_PKU (1<<(X86_FEATURE_PKU)) +-# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE)) +-#else + # define DISABLE_PKU 0 + # define DISABLE_OSPKE 0 ++#else ++# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) ++# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) + #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ + + /* diff --git a/queue-4.4/x86-fpu-add-an-xstate_op-macro.patch b/queue-4.4/x86-fpu-add-an-xstate_op-macro.patch new file mode 100644 index 00000000000..cbc8cc5c4ca --- /dev/null +++ b/queue-4.4/x86-fpu-add-an-xstate_op-macro.patch @@ -0,0 +1,163 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:25 -0700 +Subject: [PATCH 4.4.y 004/101] x86/fpu: Add an XSTATE_OP() macro +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , Fenghua Yu , "H. Peter Anvin" , Linus Torvalds , Oleg Nesterov , Peter Zijlstra , Quentin Casasnovas , Rik van Riel , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156038502.10043.6744477109477993360.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit b74a0cf1b3db30173eefa00c411775d2b1697700 upstream + +Add an XSTATE_OP() macro which contains the XSAVE* fault handling +and replace all non-alternatives users of xstate_fault() with +it. + +This fixes also the buglet in copy_xregs_to_user() and +copy_user_to_xregs() where the inline asm didn't have @xstate as +memory reference and thus potentially causing unwanted +reordering of accesses to the extended state. + +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: Fenghua Yu +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Oleg Nesterov +Cc: Peter Zijlstra +Cc: Quentin Casasnovas +Cc: Rik van Riel +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1447932326-4371-2-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/fpu/internal.h | 68 ++++++++++++++++-------------------- + 1 file changed, 31 insertions(+), 37 deletions(-) + +--- a/arch/x86/include/asm/fpu/internal.h ++++ b/arch/x86/include/asm/fpu/internal.h +@@ -238,6 +238,20 @@ static inline void copy_fxregs_to_kernel + _ASM_EXTABLE(1b, 3b) \ + : [_err] "=r" (__err) + ++#define XSTATE_OP(op, st, lmask, hmask, err) \ ++ asm volatile("1:" op "\n\t" \ ++ "xor %[err], %[err]\n" \ ++ "2:\n\t" \ ++ ".pushsection .fixup,\"ax\"\n\t" \ ++ "3: movl $-2,%[err]\n\t" \ ++ "jmp 2b\n\t" \ ++ ".popsection\n\t" \ ++ _ASM_EXTABLE(1b, 3b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") ++ ++ + /* + * This function is called only during boot time when x86 caps are not set + * up and alternative can not be used yet. +@@ -247,22 +261,14 @@ static inline void copy_xregs_to_kernel_ + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (boot_cpu_has(X86_FEATURE_XSAVES)) +- asm volatile("1:"XSAVES"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ if (static_cpu_has_safe(X86_FEATURE_XSAVES)) ++ XSTATE_OP(XSAVES, xstate, lmask, hmask, err); + else +- asm volatile("1:"XSAVE"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ XSTATE_OP(XSAVE, xstate, lmask, hmask, err); + + /* We should never fault when copying to a kernel buffer: */ + WARN_ON_FPU(err); +@@ -277,22 +283,14 @@ static inline void copy_kernel_to_xregs_ + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (boot_cpu_has(X86_FEATURE_XSAVES)) +- asm volatile("1:"XRSTORS"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ if (static_cpu_has_safe(X86_FEATURE_XSAVES)) ++ XSTATE_OP(XRSTORS, xstate, lmask, hmask, err); + else +- asm volatile("1:"XRSTOR"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); + + /* We should never fault when copying from a kernel buffer: */ + WARN_ON_FPU(err); +@@ -389,12 +387,10 @@ static inline int copy_xregs_to_user(str + if (unlikely(err)) + return -EFAULT; + +- __asm__ __volatile__(ASM_STAC "\n" +- "1:"XSAVE"\n" +- "2: " ASM_CLAC "\n" +- xstate_fault(err) +- : "D" (buf), "a" (-1), "d" (-1), "0" (err) +- : "memory"); ++ stac(); ++ XSTATE_OP(XSAVE, buf, -1, -1, err); ++ clac(); ++ + return err; + } + +@@ -406,14 +402,12 @@ static inline int copy_user_to_xregs(str + struct xregs_state *xstate = ((__force struct xregs_state *)buf); + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; ++ ++ stac(); ++ XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); ++ clac(); + +- __asm__ __volatile__(ASM_STAC "\n" +- "1:"XRSTOR"\n" +- "2: " ASM_CLAC "\n" +- xstate_fault(err) +- : "D" (xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); /* memory required? */ + return err; + } + diff --git a/queue-4.4/x86-fpu-get-rid-of-xstate_fault.patch b/queue-4.4/x86-fpu-get-rid-of-xstate_fault.patch new file mode 100644 index 00000000000..c9e9f5a3040 --- /dev/null +++ b/queue-4.4/x86-fpu-get-rid-of-xstate_fault.patch @@ -0,0 +1,185 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:34 -0700 +Subject: [PATCH 4.4.y 005/101] x86/fpu: Get rid of xstate_fault() +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Dave Hansen , Denys Vlasenko , Fenghua Yu , "H. Peter Anvin" , Linus Torvalds , Oleg Nesterov , Peter Zijlstra , Quentin Casasnovas , Rik van Riel , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156039429.10043.7505731411744407133.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit b7106fa0f29f9fd83d2d1905ab690d334ef855c1 upstream + +Add macros for the alternative XSAVE*/XRSTOR* operations which +contain the fault handling and use them. Kill xstate_fault(). + +Also, copy_xregs_to_kernel() didn't have the extended state as +memory reference in the asm. + +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Dave Hansen +Cc: Denys Vlasenko +Cc: Fenghua Yu +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Oleg Nesterov +Cc: Peter Zijlstra +Cc: Quentin Casasnovas +Cc: Rik van Riel +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1447932326-4371-3-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/fpu/internal.h | 105 +++++++++++++++++------------------- + 1 file changed, 52 insertions(+), 53 deletions(-) + +--- a/arch/x86/include/asm/fpu/internal.h ++++ b/arch/x86/include/asm/fpu/internal.h +@@ -225,19 +225,6 @@ static inline void copy_fxregs_to_kernel + #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" + #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" + +-/* xstate instruction fault handler: */ +-#define xstate_fault(__err) \ +- \ +- ".section .fixup,\"ax\"\n" \ +- \ +- "3: movl $-2,%[_err]\n" \ +- " jmp 2b\n" \ +- \ +- ".previous\n" \ +- \ +- _ASM_EXTABLE(1b, 3b) \ +- : [_err] "=r" (__err) +- + #define XSTATE_OP(op, st, lmask, hmask, err) \ + asm volatile("1:" op "\n\t" \ + "xor %[err], %[err]\n" \ +@@ -251,6 +238,54 @@ static inline void copy_fxregs_to_kernel + : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ + : "memory") + ++/* ++ * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact ++ * format and supervisor states in addition to modified optimization in ++ * XSAVEOPT. ++ * ++ * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT ++ * supports modified optimization which is not supported by XSAVE. ++ * ++ * We use XSAVE as a fallback. ++ * ++ * The 661 label is defined in the ALTERNATIVE* macros as the address of the ++ * original instruction which gets replaced. We need to use it here as the ++ * address of the instruction where we might get an exception at. ++ */ ++#define XSTATE_XSAVE(st, lmask, hmask, err) \ ++ asm volatile(ALTERNATIVE_2(XSAVE, \ ++ XSAVEOPT, X86_FEATURE_XSAVEOPT, \ ++ XSAVES, X86_FEATURE_XSAVES) \ ++ "\n" \ ++ "xor %[err], %[err]\n" \ ++ "3:\n" \ ++ ".pushsection .fixup,\"ax\"\n" \ ++ "4: movl $-2, %[err]\n" \ ++ "jmp 3b\n" \ ++ ".popsection\n" \ ++ _ASM_EXTABLE(661b, 4b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") ++ ++/* ++ * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact ++ * XSAVE area format. ++ */ ++#define XSTATE_XRESTORE(st, lmask, hmask, err) \ ++ asm volatile(ALTERNATIVE(XRSTOR, \ ++ XRSTORS, X86_FEATURE_XSAVES) \ ++ "\n" \ ++ "xor %[err], %[err]\n" \ ++ "3:\n" \ ++ ".pushsection .fixup,\"ax\"\n" \ ++ "4: movl $-2, %[err]\n" \ ++ "jmp 3b\n" \ ++ ".popsection\n" \ ++ _ASM_EXTABLE(661b, 4b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") + + /* + * This function is called only during boot time when x86 caps are not set +@@ -304,33 +339,11 @@ static inline void copy_xregs_to_kernel( + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(!alternatives_patched); + +- /* +- * If xsaves is enabled, xsaves replaces xsaveopt because +- * it supports compact format and supervisor states in addition to +- * modified optimization in xsaveopt. +- * +- * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave +- * because xsaveopt supports modified optimization which is not +- * supported by xsave. +- * +- * If none of xsaves and xsaveopt is enabled, use xsave. +- */ +- alternative_input_2( +- "1:"XSAVE, +- XSAVEOPT, +- X86_FEATURE_XSAVEOPT, +- XSAVES, +- X86_FEATURE_XSAVES, +- [xstate] "D" (xstate), "a" (lmask), "d" (hmask) : +- "memory"); +- asm volatile("2:\n\t" +- xstate_fault(err) +- : "0" (err) +- : "memory"); ++ XSTATE_XSAVE(xstate, lmask, hmask, err); + + /* We should never fault when copying to a kernel buffer: */ + WARN_ON_FPU(err); +@@ -343,23 +356,9 @@ static inline void copy_kernel_to_xregs( + { + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + +- /* +- * Use xrstors to restore context if it is enabled. xrstors supports +- * compacted format of xsave area which is not supported by xrstor. +- */ +- alternative_input( +- "1: " XRSTOR, +- XRSTORS, +- X86_FEATURE_XSAVES, +- "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask) +- : "memory"); +- +- asm volatile("2:\n" +- xstate_fault(err) +- : "0" (err) +- : "memory"); ++ XSTATE_XRESTORE(xstate, lmask, hmask, err); + + /* We should never fault when copying from a kernel buffer: */ + WARN_ON_FPU(err); diff --git a/queue-4.4/x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch b/queue-4.4/x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch new file mode 100644 index 00000000000..8917596faff --- /dev/null +++ b/queue-4.4/x86-headers-don-t-include-asm-processor.h-in-asm-atomic.h.patch @@ -0,0 +1,84 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:26:43 -0700 +Subject: [PATCH 4.4.y 006/101] x86/headers: Don't include asm/processor.h in asm/atomic.h +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Andi Kleen , "Peter Zijlstra \(Intel\)" , Arnaldo Carvalho de Melo , Jiri Olsa , Linus Torvalds , Mike Galbraith , Peter Zijlstra , Stephane Eranian , Thomas Gleixner , Vince Weaver , rostedt@goodmis.org, Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156040369.10043.18369040639751112888.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Andi Kleen + +commit 153a4334c439cfb62e1d31cee0c790ba4157813d upstream + +asm/atomic.h doesn't really need asm/processor.h anymore. Everything +it uses has moved to other header files. So remove that include. + +processor.h is a nasty header that includes lots of +other headers and makes it prone to include loops. Removing the +include here makes asm/atomic.h a "leaf" header that can +be safely included in most other headers. + +The only fallout is in the lib/atomic tester which relied on +this implicit include. Give it an explicit include. +(the include is in ifdef because the user is also in ifdef) + +Signed-off-by: Andi Kleen +Signed-off-by: Peter Zijlstra (Intel) +Cc: Arnaldo Carvalho de Melo +Cc: Jiri Olsa +Cc: Linus Torvalds +Cc: Mike Galbraith +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Cc: rostedt@goodmis.org +Link: http://lkml.kernel.org/r/1449018060-1742-1-git-send-email-andi@firstfloor.org +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/atomic.h | 1 - + arch/x86/include/asm/atomic64_32.h | 1 - + lib/atomic64_test.c | 4 ++++ + 3 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/atomic.h ++++ b/arch/x86/include/asm/atomic.h +@@ -3,7 +3,6 @@ + + #include + #include +-#include + #include + #include + #include +--- a/arch/x86/include/asm/atomic64_32.h ++++ b/arch/x86/include/asm/atomic64_32.h +@@ -3,7 +3,6 @@ + + #include + #include +-#include + //#include + + /* An 64bit atomic type */ +--- a/lib/atomic64_test.c ++++ b/lib/atomic64_test.c +@@ -16,6 +16,10 @@ + #include + #include + ++#ifdef CONFIG_X86 ++#include /* for boot_cpu_has below */ ++#endif ++ + #define TEST(bit, op, c_op, val) \ + do { \ + atomic##bit##_set(&v, v0); \ diff --git a/queue-4.4/x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch b/queue-4.4/x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch new file mode 100644 index 00000000000..8767fcc93be --- /dev/null +++ b/queue-4.4/x86-mm-pkeys-fix-mismerge-of-protection-keys-cpuid-bits.patch @@ -0,0 +1,82 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:28:13 -0700 +Subject: [PATCH 4.4.y 016/101] x86/mm/pkeys: Fix mismerge of protection keys CPUID bits +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: "Kirill A. Shutemov" , Dave Hansen , Borislav Petkov , Andy Lutomirski , Dave Hansen , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156049323.10043.9371293766744304252.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Dave Hansen + +commit 0d47638f80a02b15869f1fe1fc09e5bf996750fd upstream + +Kirill Shutemov pointed this out to me. + +The tip tree currently has commit: + + dfb4a70f2 [x86/cpufeature, x86/mm/pkeys: Add protection keys related CPUID definitions] + +whioch added support for two new CPUID bits: X86_FEATURE_PKU and +X86_FEATURE_OSPKE. But, those bits were mis-merged and put in +cpufeature.h instead of cpufeatures.h. + +This didn't cause any breakage *except* it keeps the "ospke" and +"pku" bits from showing up in cpuinfo. + +Now cpuinfo has the two new flags: + + flags : ... pku ospke + +BTW, is it really wise to have cpufeature.h and cpufeatures.h? +It seems like they can only cause confusion and mahem with tab +completion. + +Reported-by: Kirill A. Shutemov +Signed-off-by: Dave Hansen +Acked-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Dave Hansen +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/20160310221213.06F9DB53@viggo.jf.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/include/asm/cpufeature.h | 4 ---- + arch/x86/include/asm/cpufeatures.h | 4 ++++ + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -94,10 +94,6 @@ extern const char * const x86_bug_flags[ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ + x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) + +-/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ +-#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ +-#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ +- + /* + * This macro is for detection of features which need kernel + * infrastructure to be used. It may *not* directly test the CPU +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -276,6 +276,10 @@ + #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ + #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ + ++/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ ++#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ ++#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ ++ + /* + * BUG word(s) + */ diff --git a/queue-4.4/x86-vdso-use-static_cpu_has.patch b/queue-4.4/x86-vdso-use-static_cpu_has.patch new file mode 100644 index 00000000000..e11203ae3a9 --- /dev/null +++ b/queue-4.4/x86-vdso-use-static_cpu_has.patch @@ -0,0 +1,48 @@ +From foo@baz Sun Jul 15 12:18:31 CEST 2018 +From: "Srivatsa S. Bhat" +Date: Sat, 14 Jul 2018 02:27:37 -0700 +Subject: [PATCH 4.4.y 012/101] x86/vdso: Use static_cpu_has() +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Borislav Petkov , Andy Lutomirski , Borislav Petkov , Brian Gerst , Denys Vlasenko , "H. Peter Anvin" , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , "Matt Helsley \(VMware\)" , Alexey Makhalov , Bo Gan , matt.helsley@gmail.com, rostedt@goodmis.org, amakhalov@vmware.com, ganb@vmware.com, srivatsa@csail.mit.edu, srivatsab@vmware.com +Message-ID: <153156045756.10043.9363216199766022343.stgit@srivatsa-ubuntu> + +From: "Srivatsa S. Bhat" + +From: Borislav Petkov + +commit 8c725306993198f845038dc9e45a1267099867a6 upstream + +... and simplify and speed up a tad. + +Signed-off-by: Borislav Petkov +Cc: Andy Lutomirski +Cc: Borislav Petkov +Cc: Brian Gerst +Cc: Denys Vlasenko +Cc: H. Peter Anvin +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Link: http://lkml.kernel.org/r/1453842730-28463-10-git-send-email-bp@alien8.de +Signed-off-by: Ingo Molnar +Signed-off-by: Srivatsa S. Bhat +Reviewed-by: Matt Helsley (VMware) +Reviewed-by: Alexey Makhalov +Reviewed-by: Bo Gan +Signed-off-by: Greg Kroah-Hartman +--- + + arch/x86/entry/vdso/vma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/entry/vdso/vma.c ++++ b/arch/x86/entry/vdso/vma.c +@@ -255,7 +255,7 @@ static void vgetcpu_cpu_init(void *arg) + #ifdef CONFIG_NUMA + node = cpu_to_node(cpu); + #endif +- if (cpu_has(&cpu_data(cpu), X86_FEATURE_RDTSCP)) ++ if (static_cpu_has(X86_FEATURE_RDTSCP)) + write_rdtscp_aux((node << 12) | cpu); + + /* -- 2.47.3