From de197188f91d20cd7b2450db609696e77c78dfb4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 10 Aug 2018 16:19:37 +0200 Subject: [PATCH] 4.14-stable patches added patches: parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch parisc-enable-config_mlongcalls-by-default.patch --- queue-3.18/series | 0 ...rriers-to-assembler-unlock-sequences.patch | 129 ++++++++++++++++++ ...-enable-config_mlongcalls-by-default.patch | 32 +++++ queue-4.14/series | 2 + queue-4.17/series | 2 + queue-4.4/series | 6 + queue-4.9/series | 4 + 7 files changed, 175 insertions(+) create mode 100644 queue-3.18/series create mode 100644 queue-4.14/parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch create mode 100644 queue-4.14/parisc-enable-config_mlongcalls-by-default.patch create mode 100644 queue-4.14/series create mode 100644 queue-4.17/series create mode 100644 queue-4.4/series create mode 100644 queue-4.9/series diff --git a/queue-3.18/series b/queue-3.18/series new file mode 100644 index 00000000000..e69de29bb2d diff --git a/queue-4.14/parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch b/queue-4.14/parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch new file mode 100644 index 00000000000..f5141b99877 --- /dev/null +++ b/queue-4.14/parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch @@ -0,0 +1,129 @@ +From fedb8da96355f5f64353625bf96dc69423ad1826 Mon Sep 17 00:00:00 2001 +From: John David Anglin +Date: Sun, 5 Aug 2018 13:30:31 -0400 +Subject: parisc: Define mb() and add memory barriers to assembler unlock sequences +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: John David Anglin + +commit fedb8da96355f5f64353625bf96dc69423ad1826 upstream. + +For years I thought all parisc machines executed loads and stores in +order. However, Jeff Law recently indicated on gcc-patches that this is +not correct. There are various degrees of out-of-order execution all the +way back to the PA7xxx processor series (hit-under-miss). The PA8xxx +series has full out-of-order execution for both integer operations, and +loads and stores. + +This is described in the following article: +http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml + +For this reason, we need to define mb() and to insert a memory barrier +before the store unlocking spinlocks. This ensures that all memory +accesses are complete prior to unlocking. The ldcw instruction performs +the same function on entry. + +Signed-off-by: John David Anglin +Cc: stable@vger.kernel.org # 4.0+ +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/parisc/include/asm/barrier.h | 32 ++++++++++++++++++++++++++++++++ + arch/parisc/kernel/entry.S | 2 ++ + arch/parisc/kernel/pacache.S | 1 + + arch/parisc/kernel/syscall.S | 4 ++++ + 4 files changed, 39 insertions(+) + +--- /dev/null ++++ b/arch/parisc/include/asm/barrier.h +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __ASM_BARRIER_H ++#define __ASM_BARRIER_H ++ ++#ifndef __ASSEMBLY__ ++ ++/* The synchronize caches instruction executes as a nop on systems in ++ which all memory references are performed in order. */ ++#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory") ++ ++#if defined(CONFIG_SMP) ++#define mb() do { synchronize_caches(); } while (0) ++#define rmb() mb() ++#define wmb() mb() ++#define dma_rmb() mb() ++#define dma_wmb() mb() ++#else ++#define mb() barrier() ++#define rmb() barrier() ++#define wmb() barrier() ++#define dma_rmb() barrier() ++#define dma_wmb() barrier() ++#endif ++ ++#define __smp_mb() mb() ++#define __smp_rmb() mb() ++#define __smp_wmb() mb() ++ ++#include ++ ++#endif /* !__ASSEMBLY__ */ ++#endif /* __ASM_BARRIER_H */ +--- a/arch/parisc/kernel/entry.S ++++ b/arch/parisc/kernel/entry.S +@@ -482,6 +482,8 @@ + .macro tlb_unlock0 spc,tmp + #ifdef CONFIG_SMP + or,COND(=) %r0,\spc,%r0 ++ sync ++ or,COND(=) %r0,\spc,%r0 + stw \spc,0(\tmp) + #endif + .endm +--- a/arch/parisc/kernel/pacache.S ++++ b/arch/parisc/kernel/pacache.S +@@ -354,6 +354,7 @@ ENDPROC_CFI(flush_data_cache_local) + .macro tlb_unlock la,flags,tmp + #ifdef CONFIG_SMP + ldi 1,\tmp ++ sync + stw \tmp,0(\la) + mtsm \flags + #endif +--- a/arch/parisc/kernel/syscall.S ++++ b/arch/parisc/kernel/syscall.S +@@ -633,6 +633,7 @@ cas_action: + sub,<> %r28, %r25, %r0 + 2: stw,ma %r24, 0(%r26) + /* Free lock */ ++ sync + stw,ma %r20, 0(%sr2,%r20) + #if ENABLE_LWS_DEBUG + /* Clear thread register indicator */ +@@ -647,6 +648,7 @@ cas_action: + 3: + /* Error occurred on load or store */ + /* Free lock */ ++ sync + stw %r20, 0(%sr2,%r20) + #if ENABLE_LWS_DEBUG + stw %r0, 4(%sr2,%r20) +@@ -848,6 +850,7 @@ cas2_action: + + cas2_end: + /* Free lock */ ++ sync + stw,ma %r20, 0(%sr2,%r20) + /* Enable interrupts */ + ssm PSW_SM_I, %r0 +@@ -858,6 +861,7 @@ cas2_end: + 22: + /* Error occurred on load or store */ + /* Free lock */ ++ sync + stw %r20, 0(%sr2,%r20) + ssm PSW_SM_I, %r0 + ldo 1(%r0),%r28 diff --git a/queue-4.14/parisc-enable-config_mlongcalls-by-default.patch b/queue-4.14/parisc-enable-config_mlongcalls-by-default.patch new file mode 100644 index 00000000000..bec013ea209 --- /dev/null +++ b/queue-4.14/parisc-enable-config_mlongcalls-by-default.patch @@ -0,0 +1,32 @@ +From 66509a276c8c1d19ee3f661a41b418d101c57d29 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Sat, 28 Jul 2018 11:47:17 +0200 +Subject: parisc: Enable CONFIG_MLONGCALLS by default + +From: Helge Deller + +commit 66509a276c8c1d19ee3f661a41b418d101c57d29 upstream. + +Enable the -mlong-calls compiler option by default, because otherwise in most +cases linking the vmlinux binary fails due to truncations of R_PARISC_PCREL22F +relocations. This fixes building the 64-bit defconfig. + +Cc: stable@vger.kernel.org # 4.0+ +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/parisc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/parisc/Kconfig ++++ b/arch/parisc/Kconfig +@@ -201,7 +201,7 @@ config PREFETCH + + config MLONGCALLS + bool "Enable the -mlong-calls compiler option for big kernels" +- def_bool y if (!MODULES) ++ default y + depends on PA8X00 + help + If you configure the kernel to include many drivers built-in instead diff --git a/queue-4.14/series b/queue-4.14/series new file mode 100644 index 00000000000..2ff105343f4 --- /dev/null +++ b/queue-4.14/series @@ -0,0 +1,2 @@ +parisc-enable-config_mlongcalls-by-default.patch +parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch diff --git a/queue-4.17/series b/queue-4.17/series new file mode 100644 index 00000000000..2ff105343f4 --- /dev/null +++ b/queue-4.17/series @@ -0,0 +1,2 @@ +parisc-enable-config_mlongcalls-by-default.patch +parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch diff --git a/queue-4.4/series b/queue-4.4/series new file mode 100644 index 00000000000..9e499bce787 --- /dev/null +++ b/queue-4.4/series @@ -0,0 +1,6 @@ +ext4-fix-check-to-prevent-initializing-reserved-inodes.patch +tpm-fix-race-condition-in-tpm_common_write.patch +ipv4-ipv6-make-inet-_esp-select-crypto_echainiv.patch +fork-unconditionally-clear-stack-on-fork.patch +parisc-enable-config_mlongcalls-by-default.patch +parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch diff --git a/queue-4.9/series b/queue-4.9/series new file mode 100644 index 00000000000..0a33f24af49 --- /dev/null +++ b/queue-4.9/series @@ -0,0 +1,4 @@ +ext4-fix-check-to-prevent-initializing-reserved-inodes.patch +tpm-fix-race-condition-in-tpm_common_write.patch +parisc-enable-config_mlongcalls-by-default.patch +parisc-define-mb-and-add-memory-barriers-to-assembler-unlock-sequences.patch -- 2.47.3