From de1ddfd749b3390be1200a5593bf3cea3050efc4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 23 Jun 2020 13:36:40 +0200 Subject: [PATCH] drop 6 i915 patches --- ...rom-init_clock_gating-to-workarounds.patch | 111 ---------- ...rom-init_clock_gating-to-workarounds.patch | 152 -------------- ...rom-init_clock_gating-to-workarounds.patch | 75 ------- ...rom-init_clock_gating-to-workarounds.patch | 192 ----------------- ...rom-init_clock_gating-to-workarounds.patch | 132 ------------ ...rom-init_clock_gating-to-workarounds.patch | 197 ------------------ queue-5.4/series | 6 - 7 files changed, 865 deletions(-) delete mode 100644 queue-5.4/drm-i915-gt-move-gen4-gt-workarounds-from-init_clock_gating-to-workarounds.patch delete mode 100644 queue-5.4/drm-i915-gt-move-hsw-gt-workarounds-from-init_clock_gating-to-workarounds.patch delete mode 100644 queue-5.4/drm-i915-gt-move-ilk-gt-workarounds-from-init_clock_gating-to-workarounds.patch delete mode 100644 queue-5.4/drm-i915-gt-move-ivb-gt-workarounds-from-init_clock_gating-to-workarounds.patch delete mode 100644 queue-5.4/drm-i915-gt-move-snb-gt-workarounds-from-init_clock_gating-to-workarounds.patch delete mode 100644 queue-5.4/drm-i915-gt-move-vlv-gt-workarounds-from-init_clock_gating-to-workarounds.patch diff --git a/queue-5.4/drm-i915-gt-move-gen4-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-gen4-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index 934fd691f42..00000000000 --- a/queue-5.4/drm-i915-gt-move-gen4-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 27582a9c917940bc71c0df0b8e022cbde8d735d2 Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 09:01:40 +0100 -Subject: drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit 27582a9c917940bc71c0df0b8e022cbde8d735d2 upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -Signed-off-by: Chris Wilson -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-6-chris@chris-wilson.co.uk -(cherry picked from commit 2bcefd0d263ab4a72f0d61921ae6b0dc81606551) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++++++++++++++++++++++----- - drivers/gpu/drm/i915/intel_pm.c | 15 --------------- - 2 files changed, 22 insertions(+), 20 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -656,15 +656,28 @@ int intel_engine_emit_ctx_wa(struct i915 - } - - static void --ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+gen4_gt_workarounds_init(struct drm_i915_private *i915, -+ struct i915_wa_list *wal) - { -- wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); -+ /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ -+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); -+} -+ -+static void -+g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ gen4_gt_workarounds_init(i915, wal); - -- /* WaDisableRenderCachePipelinedFlush:ilk */ -+ /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ - wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); -+} - -- /* WaDisable_RenderCache_OperationalFlush:ilk */ -- wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); -+static void -+ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ g4x_gt_workarounds_init(i915, wal); -+ -+ wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); - } - - static void -@@ -1140,6 +1153,10 @@ gt_init_workarounds(struct drm_i915_priv - snb_gt_workarounds_init(i915, wal); - else if (IS_GEN(i915, 5)) - ilk_gt_workarounds_init(i915, wal); -+ else if (IS_G4X(i915)) -+ g4x_gt_workarounds_init(i915, wal); -+ else if (IS_GEN(i915, 4)) -+ gen4_gt_workarounds_init(i915, wal); - else if (INTEL_GEN(i915) <= 8) - return; - else ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -9425,13 +9425,6 @@ static void g4x_init_clock_gating(struct - dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, dspclk_gate); - -- /* WaDisableRenderCachePipelinedFlush */ -- I915_WRITE(CACHE_MODE_0, -- _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:g4x */ -- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); -- - g4x_disable_trickle_feed(dev_priv); - } - -@@ -9447,11 +9440,6 @@ static void i965gm_init_clock_gating(str - intel_uncore_write(uncore, - MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:gen4 */ -- intel_uncore_write(uncore, -- CACHE_MODE_0, -- _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - } - - static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) -@@ -9464,9 +9452,6 @@ static void i965g_init_clock_gating(stru - I915_WRITE(RENCLK_GATE_D2, 0); - I915_WRITE(MI_ARB_STATE, - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:gen4 */ -- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - } - - static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) diff --git a/queue-5.4/drm-i915-gt-move-hsw-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-hsw-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index 568fd8d24b8..00000000000 --- a/queue-5.4/drm-i915-gt-move-hsw-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,152 +0,0 @@ -From ef50fa9bd17d13d0611e39e13b37bbd3e1ea50bf Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 10:30:15 +0100 -Subject: drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit ef50fa9bd17d13d0611e39e13b37bbd3e1ea50bf upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable -bit. - -Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011 -Signed-off-by: Chris Wilson -Cc: Mika Kuoppala -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611093015.11370-1-chris@chris-wilson.co.uk -(cherry picked from commit f93ec5fb563779bda4501890b1854526de58e0f1) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++++++++++++++++++++++++++++ - drivers/gpu/drm/i915/intel_pm.c | 39 +--------------------- - 2 files changed, 50 insertions(+), 37 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -160,6 +160,12 @@ wa_write_masked_or(struct i915_wa_list * - } - - static void -+wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) -+{ -+ wa_write_masked_or(wal, reg, clr, 0); -+} -+ -+static void - wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) - { - wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val)); -@@ -650,6 +656,46 @@ int intel_engine_emit_ctx_wa(struct i915 - } - - static void -+hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ /* L3 caching of data atomics doesn't work -- disable it. */ -+ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); -+ -+ wa_add(wal, -+ HSW_ROW_CHICKEN3, 0, -+ _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), -+ 0 /* XXX does this reg exist? */); -+ -+ /* WaVSRefCountFullforceMissDisable:hsw */ -+ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); -+ -+ wa_masked_dis(wal, -+ CACHE_MODE_0_GEN7, -+ /* WaDisable_RenderCache_OperationalFlush:hsw */ -+ RC_OP_FLUSH_ENABLE | -+ /* enable HiZ Raw Stall Optimization */ -+ HIZ_RAW_STALL_OPT_DISABLE); -+ -+ /* WaDisable4x2SubspanOptimization:hsw */ -+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); -+ -+ /* -+ * BSpec recommends 8x4 when MSAA is used, -+ * however in practice 16x4 seems fastest. -+ * -+ * Note that PS/WM thread counts depend on the WIZ hashing -+ * disable bit, which we don't touch here, but it's good -+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -+ */ -+ wa_add(wal, GEN7_GT_MODE, 0, -+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), -+ GEN6_WIZ_HASHING_16x4); -+ -+ /* WaSampleCChickenBitEnable:hsw */ -+ wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); -+} -+ -+static void - gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) - { - /* WaDisableKillLogic:bxt,skl,kbl */ -@@ -916,6 +962,8 @@ gt_init_workarounds(struct drm_i915_priv - bxt_gt_workarounds_init(i915, wal); - else if (IS_SKYLAKE(i915)) - skl_gt_workarounds_init(i915, wal); -+ else if (IS_HASWELL(i915)) -+ hsw_gt_workarounds_init(i915, wal); - else if (INTEL_GEN(i915) <= 8) - return; - else ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -9347,45 +9347,10 @@ static void bdw_init_clock_gating(struct - - static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) - { -- /* L3 caching of data atomics doesn't work -- disable it. */ -- I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); -- I915_WRITE(HSW_ROW_CHICKEN3, -- _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); -- - /* This is required by WaCatErrorRejectionIssue:hsw */ - I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, -- I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | -- GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); -- -- /* WaVSRefCountFullforceMissDisable:hsw */ -- I915_WRITE(GEN7_FF_THREAD_MODE, -- I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); -- -- /* WaDisable_RenderCache_OperationalFlush:hsw */ -- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); -- -- /* enable HiZ Raw Stall Optimization */ -- I915_WRITE(CACHE_MODE_0_GEN7, -- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); -- -- /* WaDisable4x2SubspanOptimization:hsw */ -- I915_WRITE(CACHE_MODE_1, -- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- -- /* -- * BSpec recommends 8x4 when MSAA is used, -- * however in practice 16x4 seems fastest. -- * -- * Note that PS/WM thread counts depend on the WIZ hashing -- * disable bit, which we don't touch here, but it's good -- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -- */ -- I915_WRITE(GEN7_GT_MODE, -- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); -- -- /* WaSampleCChickenBitEnable:hsw */ -- I915_WRITE(HALF_SLICE_CHICKEN3, -- _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); -+ I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | -+ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - - /* WaSwitchSolVfFArbitrationPriority:hsw */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); diff --git a/queue-5.4/drm-i915-gt-move-ilk-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-ilk-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index 9db097b7f2a..00000000000 --- a/queue-5.4/drm-i915-gt-move-ilk-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,75 +0,0 @@ -From eacf21040aa97fd1b3c6bb201bfd43820e1c49be Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 09:01:39 +0100 -Subject: drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit eacf21040aa97fd1b3c6bb201bfd43820e1c49be upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -Signed-off-by: Chris Wilson -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-5-chris@chris-wilson.co.uk -(cherry picked from commit 806a45c0838d253e306a6384057e851b65d11099) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++ - drivers/gpu/drm/i915/intel_pm.c | 10 ---------- - 2 files changed, 14 insertions(+), 10 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -656,6 +656,18 @@ int intel_engine_emit_ctx_wa(struct i915 - } - - static void -+ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); -+ -+ /* WaDisableRenderCachePipelinedFlush:ilk */ -+ wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); -+ -+ /* WaDisable_RenderCache_OperationalFlush:ilk */ -+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); -+} -+ -+static void - snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) - { - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ -@@ -1067,6 +1079,8 @@ gt_init_workarounds(struct drm_i915_priv - ivb_gt_workarounds_init(i915, wal); - else if (IS_GEN(i915, 6)) - snb_gt_workarounds_init(i915, wal); -+ else if (IS_GEN(i915, 5)) -+ ilk_gt_workarounds_init(i915, wal); - else if (INTEL_GEN(i915) <= 8) - return; - else ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -8958,16 +8958,6 @@ static void ilk_init_clock_gating(struct - I915_WRITE(ILK_DISPLAY_CHICKEN2, - I915_READ(ILK_DISPLAY_CHICKEN2) | - ILK_ELPIN_409_SELECT); -- I915_WRITE(_3D_CHICKEN2, -- _3D_CHICKEN2_WM_READ_PIPELINED << 16 | -- _3D_CHICKEN2_WM_READ_PIPELINED); -- -- /* WaDisableRenderCachePipelinedFlush:ilk */ -- I915_WRITE(CACHE_MODE_0, -- _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:ilk */ -- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - g4x_disable_trickle_feed(dev_priv); - diff --git a/queue-5.4/drm-i915-gt-move-ivb-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-ivb-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index 2124495eb78..00000000000 --- a/queue-5.4/drm-i915-gt-move-ivb-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,192 +0,0 @@ -From 7237b190add0794bd95979018a23eda698f2705d Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 09:01:36 +0100 -Subject: drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit 7237b190add0794bd95979018a23eda698f2705d upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -Signed-off-by: Chris Wilson -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-2-chris@chris-wilson.co.uk -(cherry picked from commit 19f1f627b33385a2f0855cbc7d33d86d7f4a1e78) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 ++++++++++++++++++++++++++++ - drivers/gpu/drm/i915/i915_reg.h | 2 - drivers/gpu/drm/i915/intel_pm.c | 48 --------------------- - 3 files changed, 63 insertions(+), 49 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -656,6 +656,66 @@ int intel_engine_emit_ctx_wa(struct i915 - } - - static void -+ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ /* WaDisableEarlyCull:ivb */ -+ wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); -+ -+ /* WaDisablePSDDualDispatchEnable:ivb */ -+ if (IS_IVB_GT1(i915)) -+ wa_masked_en(wal, -+ GEN7_HALF_SLICE_CHICKEN1, -+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); -+ -+ /* WaDisable_RenderCache_OperationalFlush:ivb */ -+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); -+ -+ /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ -+ wa_masked_dis(wal, -+ GEN7_COMMON_SLICE_CHICKEN1, -+ GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); -+ -+ /* WaApplyL3ControlAndL3ChickenMode:ivb */ -+ wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); -+ wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); -+ -+ /* WaForceL3Serialization:ivb */ -+ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); -+ -+ /* -+ * WaVSThreadDispatchOverride:ivb,vlv -+ * -+ * This actually overrides the dispatch -+ * mode for all thread types. -+ */ -+ wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, -+ GEN7_FF_SCHED_MASK, -+ GEN7_FF_TS_SCHED_HW | -+ GEN7_FF_VS_SCHED_HW | -+ GEN7_FF_DS_SCHED_HW); -+ -+ if (0) { /* causes HiZ corruption on ivb:gt1 */ -+ /* enable HiZ Raw Stall Optimization */ -+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); -+ } -+ -+ /* WaDisable4x2SubspanOptimization:ivb */ -+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); -+ -+ /* -+ * BSpec recommends 8x4 when MSAA is used, -+ * however in practice 16x4 seems fastest. -+ * -+ * Note that PS/WM thread counts depend on the WIZ hashing -+ * disable bit, which we don't touch here, but it's good -+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -+ */ -+ wa_add(wal, GEN7_GT_MODE, 0, -+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), -+ GEN6_WIZ_HASHING_16x4); -+} -+ -+static void - hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) - { - /* L3 caching of data atomics doesn't work -- disable it. */ -@@ -964,6 +1024,8 @@ gt_init_workarounds(struct drm_i915_priv - skl_gt_workarounds_init(i915, wal); - else if (IS_HASWELL(i915)) - hsw_gt_workarounds_init(i915, wal); -+ else if (IS_IVYBRIDGE(i915)) -+ ivb_gt_workarounds_init(i915, wal); - else if (INTEL_GEN(i915) <= 8) - return; - else ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -7636,7 +7636,7 @@ enum { - - /* GEN7 chicken */ - #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) -- #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) -+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) - #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) - - #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -9364,32 +9364,11 @@ static void ivb_init_clock_gating(struct - - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); - -- /* WaDisableEarlyCull:ivb */ -- I915_WRITE(_3D_CHICKEN3, -- _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); -- - /* WaDisableBackToBackFlipFix:ivb */ - I915_WRITE(IVB_CHICKEN3, - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | - CHICKEN3_DGMG_DONE_FIX_DISABLE); - -- /* WaDisablePSDDualDispatchEnable:ivb */ -- if (IS_IVB_GT1(dev_priv)) -- I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, -- _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:ivb */ -- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); -- -- /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ -- I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, -- GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); -- -- /* WaApplyL3ControlAndL3ChickenMode:ivb */ -- I915_WRITE(GEN7_L3CNTLREG1, -- GEN7_WA_FOR_GEN7_L3_CONTROL); -- I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, -- GEN7_WA_L3_CHICKEN_MODE); - if (IS_IVB_GT1(dev_priv)) - I915_WRITE(GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); -@@ -9401,10 +9380,6 @@ static void ivb_init_clock_gating(struct - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - } - -- /* WaForceL3Serialization:ivb */ -- I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & -- ~L3SQ_URB_READ_CAM_MATCH_DISABLE); -- - /* - * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating:ivb workaround. -@@ -9419,29 +9394,6 @@ static void ivb_init_clock_gating(struct - - g4x_disable_trickle_feed(dev_priv); - -- gen7_setup_fixed_func_scheduler(dev_priv); -- -- if (0) { /* causes HiZ corruption on ivb:gt1 */ -- /* enable HiZ Raw Stall Optimization */ -- I915_WRITE(CACHE_MODE_0_GEN7, -- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); -- } -- -- /* WaDisable4x2SubspanOptimization:ivb */ -- I915_WRITE(CACHE_MODE_1, -- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- -- /* -- * BSpec recommends 8x4 when MSAA is used, -- * however in practice 16x4 seems fastest. -- * -- * Note that PS/WM thread counts depend on the WIZ hashing -- * disable bit, which we don't touch here, but it's good -- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -- */ -- I915_WRITE(GEN7_GT_MODE, -- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); -- - snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); - snpcr &= ~GEN6_MBC_SNPCR_MASK; - snpcr |= GEN6_MBC_SNPCR_MED; diff --git a/queue-5.4/drm-i915-gt-move-snb-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-snb-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index 5b66be7832e..00000000000 --- a/queue-5.4/drm-i915-gt-move-snb-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,132 +0,0 @@ -From fd2599bda5a989c3332f4956fd7760ec32bd51ee Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 09:01:38 +0100 -Subject: drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit fd2599bda5a989c3332f4956fd7760ec32bd51ee upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -Signed-off-by: Chris Wilson -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-4-chris@chris-wilson.co.uk -(cherry picked from commit c3b93a943f2c9ee4a106db100a2fc3b2f126bfc5) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 ++++++++++++++++++++++++++++ - drivers/gpu/drm/i915/intel_pm.c | 33 ---------------------- - 2 files changed, 41 insertions(+), 33 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -656,6 +656,45 @@ int intel_engine_emit_ctx_wa(struct i915 - } - - static void -+snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ -+ wa_masked_en(wal, -+ _3D_CHICKEN, -+ _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); -+ -+ /* WaDisable_RenderCache_OperationalFlush:snb */ -+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); -+ -+ /* -+ * BSpec recommends 8x4 when MSAA is used, -+ * however in practice 16x4 seems fastest. -+ * -+ * Note that PS/WM thread counts depend on the WIZ hashing -+ * disable bit, which we don't touch here, but it's good -+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -+ */ -+ wa_add(wal, -+ GEN6_GT_MODE, 0, -+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), -+ GEN6_WIZ_HASHING_16x4); -+ -+ wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); -+ -+ wa_masked_en(wal, -+ _3D_CHICKEN3, -+ /* WaStripsFansDisableFastClipPerformanceFix:snb */ -+ _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | -+ /* -+ * Bspec says: -+ * "This bit must be set if 3DSTATE_CLIP clip mode is set -+ * to normal and 3DSTATE_SF number of SF output attributes -+ * is more than 16." -+ */ -+ _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); -+} -+ -+static void - ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) - { - /* WaDisableEarlyCull:ivb */ -@@ -1026,6 +1065,8 @@ gt_init_workarounds(struct drm_i915_priv - hsw_gt_workarounds_init(i915, wal); - else if (IS_IVYBRIDGE(i915)) - ivb_gt_workarounds_init(i915, wal); -+ else if (IS_GEN(i915, 6)) -+ snb_gt_workarounds_init(i915, wal); - else if (INTEL_GEN(i915) <= 8) - return; - else ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -9030,27 +9030,6 @@ static void gen6_init_clock_gating(struc - I915_READ(ILK_DISPLAY_CHICKEN2) | - ILK_ELPIN_409_SELECT); - -- /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ -- I915_WRITE(_3D_CHICKEN, -- _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); -- -- /* WaDisable_RenderCache_OperationalFlush:snb */ -- I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); -- -- /* -- * BSpec recoomends 8x4 when MSAA is used, -- * however in practice 16x4 seems fastest. -- * -- * Note that PS/WM thread counts depend on the WIZ hashing -- * disable bit, which we don't touch here, but it's good -- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -- */ -- I915_WRITE(GEN6_GT_MODE, -- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); -- -- I915_WRITE(CACHE_MODE_0, -- _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); -- - I915_WRITE(GEN6_UCGCTL1, - I915_READ(GEN6_UCGCTL1) | - GEN6_BLBUNIT_CLOCK_GATE_DISABLE | -@@ -9073,18 +9052,6 @@ static void gen6_init_clock_gating(struc - GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | - GEN6_RCCUNIT_CLOCK_GATE_DISABLE); - -- /* WaStripsFansDisableFastClipPerformanceFix:snb */ -- I915_WRITE(_3D_CHICKEN3, -- _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); -- -- /* -- * Bspec says: -- * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and -- * 3DSTATE_SF number of SF output attributes is more than 16." -- */ -- I915_WRITE(_3D_CHICKEN3, -- _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); -- - /* - * According to the spec the following bits should be - * set in order to enable memory self-refresh and fbc: diff --git a/queue-5.4/drm-i915-gt-move-vlv-gt-workarounds-from-init_clock_gating-to-workarounds.patch b/queue-5.4/drm-i915-gt-move-vlv-gt-workarounds-from-init_clock_gating-to-workarounds.patch deleted file mode 100644 index f806f9bffb5..00000000000 --- a/queue-5.4/drm-i915-gt-move-vlv-gt-workarounds-from-init_clock_gating-to-workarounds.patch +++ /dev/null @@ -1,197 +0,0 @@ -From 695a2b11649e99bbf15d278042247042c42b8728 Mon Sep 17 00:00:00 2001 -From: Chris Wilson -Date: Thu, 11 Jun 2020 09:01:37 +0100 -Subject: drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds - -From: Chris Wilson - -commit 695a2b11649e99bbf15d278042247042c42b8728 upstream. - -Rescue the GT workarounds from being buried inside init_clock_gating so -that we remember to apply them after a GT reset, and that they are -included in our verification that the workarounds are applied. - -Signed-off-by: Chris Wilson -Reviewed-by: Mika Kuoppala -Cc: stable@vger.kernel.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-3-chris@chris-wilson.co.uk -(cherry picked from commit 7331c356b6d2d8a01422cacab27478a1dba9fa2a) -Signed-off-by: Joonas Lahtinen -Signed-off-by: Greg Kroah-Hartman - ---- - drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 +++++++++++++++++++++++++++ - drivers/gpu/drm/i915/intel_pm.c | 61 ---------------------------- - 2 files changed, 59 insertions(+), 61 deletions(-) - ---- a/drivers/gpu/drm/i915/gt/intel_workarounds.c -+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c -@@ -767,6 +767,63 @@ ivb_gt_workarounds_init(struct drm_i915_ - } - - static void -+vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) -+{ -+ /* WaDisableEarlyCull:vlv */ -+ wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); -+ -+ /* WaPsdDispatchEnable:vlv */ -+ /* WaDisablePSDDualDispatchEnable:vlv */ -+ wa_masked_en(wal, -+ GEN7_HALF_SLICE_CHICKEN1, -+ GEN7_MAX_PS_THREAD_DEP | -+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); -+ -+ /* WaDisable_RenderCache_OperationalFlush:vlv */ -+ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); -+ -+ /* WaForceL3Serialization:vlv */ -+ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); -+ -+ /* -+ * WaVSThreadDispatchOverride:ivb,vlv -+ * -+ * This actually overrides the dispatch -+ * mode for all thread types. -+ */ -+ wa_write_masked_or(wal, -+ GEN7_FF_THREAD_MODE, -+ GEN7_FF_SCHED_MASK, -+ GEN7_FF_TS_SCHED_HW | -+ GEN7_FF_VS_SCHED_HW | -+ GEN7_FF_DS_SCHED_HW); -+ -+ /* -+ * BSpec says this must be set, even though -+ * WaDisable4x2SubspanOptimization isn't listed for VLV. -+ */ -+ wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); -+ -+ /* -+ * BSpec recommends 8x4 when MSAA is used, -+ * however in practice 16x4 seems fastest. -+ * -+ * Note that PS/WM thread counts depend on the WIZ hashing -+ * disable bit, which we don't touch here, but it's good -+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -+ */ -+ wa_add(wal, GEN7_GT_MODE, 0, -+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), -+ GEN6_WIZ_HASHING_16x4); -+ -+ /* -+ * WaIncreaseL3CreditsForVLVB0:vlv -+ * This is the hardware default actually. -+ */ -+ wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); -+} -+ -+static void - hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) - { - /* L3 caching of data atomics doesn't work -- disable it. */ -@@ -1075,6 +1132,8 @@ gt_init_workarounds(struct drm_i915_priv - skl_gt_workarounds_init(i915, wal); - else if (IS_HASWELL(i915)) - hsw_gt_workarounds_init(i915, wal); -+ else if (IS_VALLEYVIEW(i915)) -+ vlv_gt_workarounds_init(i915, wal); - else if (IS_IVYBRIDGE(i915)) - ivb_gt_workarounds_init(i915, wal); - else if (IS_GEN(i915, 6)) ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -9071,24 +9071,6 @@ static void gen6_init_clock_gating(struc - gen6_check_mch_setup(dev_priv); - } - --static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) --{ -- u32 reg = I915_READ(GEN7_FF_THREAD_MODE); -- -- /* -- * WaVSThreadDispatchOverride:ivb,vlv -- * -- * This actually overrides the dispatch -- * mode for all thread types. -- */ -- reg &= ~GEN7_FF_SCHED_MASK; -- reg |= GEN7_FF_TS_SCHED_HW; -- reg |= GEN7_FF_VS_SCHED_HW; -- reg |= GEN7_FF_DS_SCHED_HW; -- -- I915_WRITE(GEN7_FF_THREAD_MODE, reg); --} -- - static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) - { - /* -@@ -9364,28 +9346,11 @@ static void ivb_init_clock_gating(struct - - static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) - { -- /* WaDisableEarlyCull:vlv */ -- I915_WRITE(_3D_CHICKEN3, -- _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); -- - /* WaDisableBackToBackFlipFix:vlv */ - I915_WRITE(IVB_CHICKEN3, - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | - CHICKEN3_DGMG_DONE_FIX_DISABLE); - -- /* WaPsdDispatchEnable:vlv */ -- /* WaDisablePSDDualDispatchEnable:vlv */ -- I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, -- _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | -- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); -- -- /* WaDisable_RenderCache_OperationalFlush:vlv */ -- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); -- -- /* WaForceL3Serialization:vlv */ -- I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & -- ~L3SQ_URB_READ_CAM_MATCH_DISABLE); -- - /* WaDisableDopClockGating:vlv */ - I915_WRITE(GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); -@@ -9395,8 +9360,6 @@ static void vlv_init_clock_gating(struct - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - -- gen7_setup_fixed_func_scheduler(dev_priv); -- - /* - * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating:vlv workaround. -@@ -9411,30 +9374,6 @@ static void vlv_init_clock_gating(struct - I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); - - /* -- * BSpec says this must be set, even though -- * WaDisable4x2SubspanOptimization isn't listed for VLV. -- */ -- I915_WRITE(CACHE_MODE_1, -- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- -- /* -- * BSpec recommends 8x4 when MSAA is used, -- * however in practice 16x4 seems fastest. -- * -- * Note that PS/WM thread counts depend on the WIZ hashing -- * disable bit, which we don't touch here, but it's good -- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). -- */ -- I915_WRITE(GEN7_GT_MODE, -- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); -- -- /* -- * WaIncreaseL3CreditsForVLVB0:vlv -- * This is the hardware default actually. -- */ -- I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); -- -- /* - * WaDisableVLVClockGating_VBIIssue:vlv - * Disable clock gating on th GCFG unit to prevent a delay - * in the reporting of vblank events. diff --git a/queue-5.4/series b/queue-5.4/series index 101282e5998..1a29d837ec3 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -301,9 +301,3 @@ drm-i915-whitelist-context-local-timestamp-in-the-gen9-cmdparser.patch drm-connector-notify-userspace-on-hotplug-after-register-complete.patch drm-amd-display-use-kvfree-to-free-coeff-in-build_regamma.patch drm-i915-icl-fix-hotplug-interrupt-disabling-after-storm-detection.patch -drm-i915-gt-move-hsw-gt-workarounds-from-init_clock_gating-to-workarounds.patch -drm-i915-gt-move-ivb-gt-workarounds-from-init_clock_gating-to-workarounds.patch -drm-i915-gt-move-snb-gt-workarounds-from-init_clock_gating-to-workarounds.patch -drm-i915-gt-move-ilk-gt-workarounds-from-init_clock_gating-to-workarounds.patch -drm-i915-gt-move-vlv-gt-workarounds-from-init_clock_gating-to-workarounds.patch -drm-i915-gt-move-gen4-gt-workarounds-from-init_clock_gating-to-workarounds.patch -- 2.47.3