From e361e1caed1458057ee0bc9d36462a207cb36e1c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 28 Oct 2025 09:35:10 +0100 Subject: [PATCH] drop some 5.10 and 5.15 riscv patches that break the build --- ...correctly-print-supported-extensions.patch | 70 ----- ..._of_parent_hartid-for-disabled-harts.patch | 51 ---- ...print-details-of-cpus-disabled-in-dt.patch | 46 ---- ...minimal-parser-for-riscv-isa-strings.patch | 145 ---------- ...cpu-add-64bit-hartid-support-on-rv64.patch | 260 ------------------ queue-5.10/riscv-use-of_get_cpu_hwid.patch | 41 --- queue-5.10/series | 6 - ...correctly-print-supported-extensions.patch | 70 ----- ..._of_parent_hartid-for-disabled-harts.patch | 51 ---- ...print-details-of-cpus-disabled-in-dt.patch | 46 ---- ...minimal-parser-for-riscv-isa-strings.patch | 145 ---------- ...cpu-add-64bit-hartid-support-on-rv64.patch | 260 ------------------ queue-5.15/riscv-use-of_get_cpu_hwid.patch | 41 --- queue-5.15/series | 6 - 14 files changed, 1238 deletions(-) delete mode 100644 queue-5.10/risc-v-correctly-print-supported-extensions.patch delete mode 100644 queue-5.10/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch delete mode 100644 queue-5.10/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch delete mode 100644 queue-5.10/risc-v-minimal-parser-for-riscv-isa-strings.patch delete mode 100644 queue-5.10/riscv-cpu-add-64bit-hartid-support-on-rv64.patch delete mode 100644 queue-5.10/riscv-use-of_get_cpu_hwid.patch delete mode 100644 queue-5.15/risc-v-correctly-print-supported-extensions.patch delete mode 100644 queue-5.15/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch delete mode 100644 queue-5.15/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch delete mode 100644 queue-5.15/risc-v-minimal-parser-for-riscv-isa-strings.patch delete mode 100644 queue-5.15/riscv-cpu-add-64bit-hartid-support-on-rv64.patch delete mode 100644 queue-5.15/riscv-use-of_get_cpu_hwid.patch diff --git a/queue-5.10/risc-v-correctly-print-supported-extensions.patch b/queue-5.10/risc-v-correctly-print-supported-extensions.patch deleted file mode 100644 index 88b28e02e7..0000000000 --- a/queue-5.10/risc-v-correctly-print-supported-extensions.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 93ed5cf563a402e786e8eeedc6f4ad5a7c4ef7af Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 14 Mar 2022 13:38:40 -0700 -Subject: RISC-V: Correctly print supported extensions - -From: Tsukasa OI - -[ Upstream commit 58004f266918912771ee71f46bfb92bf64ab9108 ] - -This commit replaces BITS_PER_LONG with number of alphabet letters. - -Current ISA pretty-printing code expects extension 'a' (bit 0) through -'z' (bit 25). Although bit 26 and higher is not currently used (thus never -cause an issue in practice), it will be an annoying problem if we start to -use those in the future. - -This commit disables printing high bits for now. - -Reviewed-by: Anup Patel -Tested-by: Heiko Stuebner -Signed-off-by: Tsukasa OI -Signed-off-by: Atish Patra -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpufeature.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index ac202f44a6702..ece126dad3547 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -13,6 +13,8 @@ - #include - #include - -+#define NUM_ALPHA_EXTS ('z' - 'a' + 1) -+ - unsigned long elf_hwcap __read_mostly; - - /* Host ISA bitmap */ -@@ -63,7 +65,7 @@ void riscv_fill_hwcap(void) - { - struct device_node *node; - const char *isa; -- char print_str[BITS_PER_LONG + 1]; -+ char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; - static unsigned long isa2hwcap[256] = {0}; - -@@ -133,13 +135,13 @@ void riscv_fill_hwcap(void) - } - - memset(print_str, 0, sizeof(print_str)); -- for (i = 0, j = 0; i < BITS_PER_LONG; i++) -+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) - if (riscv_isa[0] & BIT_MASK(i)) - print_str[j++] = (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); - - memset(print_str, 0, sizeof(print_str)); -- for (i = 0, j = 0; i < BITS_PER_LONG; i++) -+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) - if (elf_hwcap & BIT_MASK(i)) - print_str[j++] = (char)('a' + i); - pr_info("riscv: ELF capabilities %s\n", print_str); --- -2.51.0 - diff --git a/queue-5.10/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch b/queue-5.10/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch deleted file mode 100644 index 62c00fcb73..0000000000 --- a/queue-5.10/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c4676f8dc1e12e68d6511f9ed89707fdad4c962c Mon Sep 17 00:00:00 2001 -From: Anup Patel -Date: Fri, 27 Oct 2023 21:12:53 +0530 -Subject: RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs - -From: Anup Patel - -commit c4676f8dc1e12e68d6511f9ed89707fdad4c962c upstream. - -The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails -for HARTs disabled in the DT. This results in the following warning -thrown by the RISC-V INTC driver for the E-core on SiFive boards: - -[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller - -The riscv_of_parent_hartid() is only expected to read the hartid -from the DT so we directly call of_get_cpu_hwid() instead of calling -riscv_of_processor_hartid(). - -Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64") -Signed-off-by: Anup Patel -Reviewed-by: Atish Patra -Link: https://lore.kernel.org/r/20231027154254.355853-2-apatel@ventanamicro.com -Signed-off-by: Palmer Dabbelt -Signed-off-by: Greg Kroah-Hartman ---- - arch/riscv/kernel/cpu.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -50,13 +50,14 @@ int riscv_of_processor_hartid(struct dev - */ - int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) - { -- int rc; -- - for (; node; node = node->parent) { - if (of_device_is_compatible(node, "riscv")) { -- rc = riscv_of_processor_hartid(node, hartid); -- if (!rc) -- return 0; -+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0); -+ if (*hartid == ~0UL) { -+ pr_warn("Found CPU without hart ID\n"); -+ return -ENODEV; -+ } -+ return 0; - } - } - diff --git a/queue-5.10/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch b/queue-5.10/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch deleted file mode 100644 index 9e5abfeb43..0000000000 --- a/queue-5.10/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch +++ /dev/null @@ -1,46 +0,0 @@ -From b18c59a5af52f5e6fec761e22d9f630db10a7786 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 14 Oct 2025 22:00:09 +0530 -Subject: RISC-V: Don't print details of CPUs disabled in DT - -From: Anup Patel - -[ Upstream commit d2721bb165b3ee00dd23525885381af07fec852a ] - -Early boot stages may disable CPU DT nodes for unavailable -CPUs based on SKU, pinstraps, eFuse, etc. Currently, the -riscv_early_of_processor_hartid() prints details of a CPU -if it is disabled in DT which has no value and gives a -false impression to the users that there some issue with -the CPU. - -Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled") -Signed-off-by: Anup Patel -Reviewed-by: Andrew Jones -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20251014163009.182381-1-apatel@ventanamicro.com -Signed-off-by: Paul Walmsley -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpu.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index 11d6d6cc61d51..39013aedbe0ab 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -27,10 +27,8 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) - return -ENODEV; - } - -- if (!of_device_is_available(node)) { -- pr_info("CPU with hartid=%lu is not available\n", *hart); -+ if (!of_device_is_available(node)) - return -ENODEV; -- } - - if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); --- -2.51.0 - diff --git a/queue-5.10/risc-v-minimal-parser-for-riscv-isa-strings.patch b/queue-5.10/risc-v-minimal-parser-for-riscv-isa-strings.patch deleted file mode 100644 index 5abf257998..0000000000 --- a/queue-5.10/risc-v-minimal-parser-for-riscv-isa-strings.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 37334339e71c5a10f92eacdeead0a897538672ec Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 14 Mar 2022 13:38:41 -0700 -Subject: RISC-V: Minimal parser for "riscv, isa" strings - -From: Tsukasa OI - -[ Upstream commit 2a31c54be097c74344b4fab20ea6104012d2cb8b ] - -Current hart ISA ("riscv,isa") parser don't correctly parse: - -1. Multi-letter extensions -2. Version numbers - -All ISA extensions ratified recently has multi-letter extensions -(except 'H'). The current "riscv,isa" parser that is easily confused -by multi-letter extensions and "p" in version numbers can be a huge -problem for adding new extensions through the device tree. - -Leaving it would create incompatible hacks and would make "riscv,isa" -value unreliable. - -This commit implements minimal parser for "riscv,isa" strings. With this, -we can safely ignore multi-letter extensions and version numbers. - -[Improved commit text and fixed a bug around 's' in base extension] -Signed-off-by: Atish Patra -[Fixed workaround for QEMU] -Signed-off-by: Tsukasa OI -Tested-by: Heiko Stuebner -Reviewed-by: Anup Patel -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------ - 1 file changed, 61 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index ece126dad3547..54d230bdaf976 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -7,6 +7,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -66,7 +67,7 @@ void riscv_fill_hwcap(void) - struct device_node *node; - const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; -- size_t i, j, isa_len; -+ int i, j; - static unsigned long isa2hwcap[256] = {0}; - - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; -@@ -92,23 +93,72 @@ void riscv_fill_hwcap(void) - continue; - } - -- i = 0; -- isa_len = strlen(isa); - #if IS_ENABLED(CONFIG_32BIT) - if (!strncmp(isa, "rv32", 4)) -- i += 4; -+ isa += 4; - #elif IS_ENABLED(CONFIG_64BIT) - if (!strncmp(isa, "rv64", 4)) -- i += 4; -+ isa += 4; - #endif -- for (; i < isa_len; ++i) { -- this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; -+ for (; *isa; ++isa) { -+ const char *ext = isa++; -+ const char *ext_end = isa; -+ bool ext_long = false, ext_err = false; -+ -+ switch (*ext) { -+ case 's': -+ /** -+ * Workaround for invalid single-letter 's' & 'u'(QEMU). -+ * No need to set the bit in riscv_isa as 's' & 'u' are -+ * not valid ISA extensions. It works until multi-letter -+ * extension starting with "Su" appears. -+ */ -+ if (ext[-1] != '_' && ext[1] == 'u') { -+ ++isa; -+ ext_err = true; -+ break; -+ } -+ fallthrough; -+ case 'x': -+ case 'z': -+ ext_long = true; -+ /* Multi-letter extension must be delimited */ -+ for (; *isa && *isa != '_'; ++isa) -+ if (!islower(*isa) && !isdigit(*isa)) -+ ext_err = true; -+ break; -+ default: -+ if (unlikely(!islower(*ext))) { -+ ext_err = true; -+ break; -+ } -+ /* Find next extension */ -+ if (!isdigit(*isa)) -+ break; -+ /* Skip the minor version */ -+ while (isdigit(*++isa)) -+ ; -+ if (*isa != 'p') -+ break; -+ if (!isdigit(*++isa)) { -+ --isa; -+ break; -+ } -+ /* Skip the major version */ -+ while (isdigit(*++isa)) -+ ; -+ break; -+ } -+ if (*isa != '_') -+ --isa; - /* -- * TODO: X, Y and Z extension parsing for Host ISA -- * bitmap will be added in-future. -+ * TODO: Full version-aware handling including -+ * multi-letter extensions will be added in-future. - */ -- if ('a' <= isa[i] && isa[i] < 'x') -- this_isa |= (1UL << (isa[i] - 'a')); -+ if (ext_err || ext_long) -+ continue; -+ this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; -+ this_isa |= (1UL << (*ext - 'a')); - } - - /* --- -2.51.0 - diff --git a/queue-5.10/riscv-cpu-add-64bit-hartid-support-on-rv64.patch b/queue-5.10/riscv-cpu-add-64bit-hartid-support-on-rv64.patch deleted file mode 100644 index 8522a44abc..0000000000 --- a/queue-5.10/riscv-cpu-add-64bit-hartid-support-on-rv64.patch +++ /dev/null @@ -1,260 +0,0 @@ -From 76b3881905903f8e8a1af4fb33bfab80b1998b8e Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 27 May 2022 10:47:42 +0530 -Subject: riscv: cpu: Add 64bit hartid support on RV64 - -From: Sunil V L - -[ Upstream commit ad635e723e17379b192a5ba9c182e3eedfc24d16 ] - -The hartid can be a 64bit value on RV64 platforms. - -Add support for 64bit hartid in riscv_of_processor_hartid() and -update its callers. - -Signed-off-by: Sunil V L -Reviewed-by: Atish Patra -Link: https://lore.kernel.org/r/20220527051743.2829940-5-sunilvl@ventanamicro.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/include/asm/processor.h | 4 ++-- - arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- - arch/riscv/kernel/cpufeature.c | 6 ++++-- - arch/riscv/kernel/smpboot.c | 9 +++++---- - drivers/clocksource/timer-riscv.c | 15 ++++++++------- - drivers/irqchip/irq-riscv-intc.c | 7 ++++--- - drivers/irqchip/irq-sifive-plic.c | 7 ++++--- - 7 files changed, 42 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h -index bdddcd5c1b71d..b5295806643b1 100644 ---- a/arch/riscv/include/asm/processor.h -+++ b/arch/riscv/include/asm/processor.h -@@ -66,8 +66,8 @@ static inline void wait_for_interrupt(void) - } - - struct device_node; --int riscv_of_processor_hartid(struct device_node *node); --int riscv_of_parent_hartid(struct device_node *node); -+int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); -+int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); - - extern void riscv_fill_hwcap(void); - -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index f13b2c9ea912d..11d6d6cc61d51 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -12,37 +12,36 @@ - * Returns the hart ID of the given device tree node, or -ENODEV if the node - * isn't an enabled and valid RISC-V hart node. - */ --int riscv_of_processor_hartid(struct device_node *node) -+int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) - { - const char *isa; -- u32 hart; - - if (!of_device_is_compatible(node, "riscv")) { - pr_warn("Found incompatible CPU\n"); - return -ENODEV; - } - -- hart = of_get_cpu_hwid(node, 0); -- if (hart == ~0U) { -+ *hart = (unsigned long) of_get_cpu_hwid(node, 0); -+ if (*hart == ~0UL) { - pr_warn("Found CPU without hart ID\n"); - return -ENODEV; - } - - if (!of_device_is_available(node)) { -- pr_info("CPU with hartid=%d is not available\n", hart); -+ pr_info("CPU with hartid=%lu is not available\n", *hart); - return -ENODEV; - } - - if (of_property_read_string(node, "riscv,isa", &isa)) { -- pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); -+ pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); - return -ENODEV; - } - if (isa[0] != 'r' || isa[1] != 'v') { -- pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); -+ pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); - return -ENODEV; - } - -- return hart; -+ return 0; - } - - /* -@@ -51,11 +50,16 @@ int riscv_of_processor_hartid(struct device_node *node) - * To achieve this, we walk up the DT tree until we find an active - * RISC-V core (HART) node and extract the cpuid from it. - */ --int riscv_of_parent_hartid(struct device_node *node) -+int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) - { -+ int rc; -+ - for (; node; node = node->parent) { -- if (of_device_is_compatible(node, "riscv")) -- return riscv_of_processor_hartid(node); -+ if (of_device_is_compatible(node, "riscv")) { -+ rc = riscv_of_processor_hartid(node, hartid); -+ if (!rc) -+ return 0; -+ } - } - - return -1; -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index 54d230bdaf976..f46efff26e3dc 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -67,8 +67,9 @@ void riscv_fill_hwcap(void) - struct device_node *node; - const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; -- int i, j; -+ int i, j, rc; - static unsigned long isa2hwcap[256] = {0}; -+ unsigned long hartid; - - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; -@@ -85,7 +86,8 @@ void riscv_fill_hwcap(void) - unsigned long this_hwcap = 0; - unsigned long this_isa = 0; - -- if (riscv_of_processor_hartid(node) < 0) -+ rc = riscv_of_processor_hartid(node, &hartid); -+ if (rc < 0) - continue; - - if (of_property_read_string(node, "riscv,isa", &isa)) { -diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c -index 0e0aed380e281..9df6413771923 100644 ---- a/arch/riscv/kernel/smpboot.c -+++ b/arch/riscv/kernel/smpboot.c -@@ -67,15 +67,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) - void __init setup_smp(void) - { - struct device_node *dn; -- int hart; -+ unsigned long hart; - bool found_boot_cpu = false; - int cpuid = 1; -+ int rc; - - cpu_set_ops(0); - - for_each_of_cpu_node(dn) { -- hart = riscv_of_processor_hartid(dn); -- if (hart < 0) -+ rc = riscv_of_processor_hartid(dn, &hart); -+ if (rc < 0) - continue; - - if (hart == cpuid_to_hartid_map(0)) { -@@ -84,7 +85,7 @@ void __init setup_smp(void) - continue; - } - if (cpuid >= NR_CPUS) { -- pr_warn("Invalid cpuid [%d] for hartid [%d]\n", -+ pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", - cpuid, hart); - break; - } -diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c -index c51c5ed15aa75..4930d08c9374a 100644 ---- a/drivers/clocksource/timer-riscv.c -+++ b/drivers/clocksource/timer-riscv.c -@@ -92,20 +92,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) - - static int __init riscv_timer_init_dt(struct device_node *n) - { -- int cpuid, hartid, error; -+ int cpuid, error; -+ unsigned long hartid; - struct device_node *child; - struct irq_domain *domain; - -- hartid = riscv_of_processor_hartid(n); -- if (hartid < 0) { -- pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", -+ error = riscv_of_processor_hartid(n, &hartid); -+ if (error < 0) { -+ pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); -- return hartid; -+ return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { -- pr_warn("Invalid cpuid for hartid [%d]\n", hartid); -+ pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - -@@ -131,7 +132,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) - return -ENODEV; - } - -- pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", -+ pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); - error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); - if (error) { -diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c -index 8017f6d32d52b..edbf90a7565f6 100644 ---- a/drivers/irqchip/irq-riscv-intc.c -+++ b/drivers/irqchip/irq-riscv-intc.c -@@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { - static int __init riscv_intc_init(struct device_node *node, - struct device_node *parent) - { -- int rc, hartid; -+ int rc; -+ unsigned long hartid; - -- hartid = riscv_of_parent_hartid(node); -- if (hartid < 0) { -+ rc = riscv_of_parent_hartid(node, &hartid); -+ if (rc < 0) { - pr_warn("unable to find hart id for %pOF\n", node); - return 0; - } -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index bd99ee0ae433d..5fdf0eae48f7d 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -315,7 +315,8 @@ static int __init plic_init(struct device_node *node, - for (i = 0; i < nr_contexts; i++) { - struct of_phandle_args parent; - irq_hw_number_t hwirq; -- int cpu, hartid; -+ int cpu; -+ unsigned long hartid; - - if (of_irq_parse_one(node, i, &parent)) { - pr_err("failed to parse parent for context %d.\n", i); -@@ -329,8 +330,8 @@ static int __init plic_init(struct device_node *node, - if (parent.args[0] != RV_IRQ_EXT) - continue; - -- hartid = riscv_of_parent_hartid(parent.np); -- if (hartid < 0) { -+ error = riscv_of_parent_hartid(parent.np, &hartid); -+ if (error < 0) { - pr_warn("failed to parse hart ID for context %d.\n", i); - continue; - } --- -2.51.0 - diff --git a/queue-5.10/riscv-use-of_get_cpu_hwid.patch b/queue-5.10/riscv-use-of_get_cpu_hwid.patch deleted file mode 100644 index 053db28579..0000000000 --- a/queue-5.10/riscv-use-of_get_cpu_hwid.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b49cf4ec68dc8e5e449aa8e460f26ad74c390c6b Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 6 Oct 2021 11:43:28 -0500 -Subject: riscv: Use of_get_cpu_hwid() - -From: Rob Herring - -[ Upstream commit bd2259ee458e299ec14061da7faddcfb0d54d154 ] - -Replace open coded parsing of CPU nodes' 'reg' property with -of_get_cpu_hwid(). - -Cc: Paul Walmsley -Cc: Palmer Dabbelt -Cc: Albert Ou -Cc: linux-riscv@lists.infradead.org -Signed-off-by: Rob Herring -Link: https://lore.kernel.org/r/20211006164332.1981454-9-robh@kernel.org -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpu.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index 6d59e6906fddf..f13b2c9ea912d 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -22,7 +22,8 @@ int riscv_of_processor_hartid(struct device_node *node) - return -ENODEV; - } - -- if (of_property_read_u32(node, "reg", &hart)) { -+ hart = of_get_cpu_hwid(node, 0); -+ if (hart == ~0U) { - pr_warn("Found CPU without hart ID\n"); - return -ENODEV; - } --- -2.51.0 - diff --git a/queue-5.10/series b/queue-5.10/series index a3dc27daa8..36b81ba27a 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -283,11 +283,6 @@ mips-malta-fix-keyboard-resource-preventing-i8042-driver-from-registering.patch ocfs2-clear-extent-cache-after-moving-defragmenting-extents.patch net-usb-rtl8150-fix-frame-padding.patch net-ravb-ensure-memory-write-completes-before-ringing-tx-doorbell.patch -riscv-use-of_get_cpu_hwid.patch -risc-v-correctly-print-supported-extensions.patch -risc-v-minimal-parser-for-riscv-isa-strings.patch -riscv-cpu-add-64bit-hartid-support-on-rv64.patch -risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch usb-serial-option-add-unisoc-uis7720.patch usb-serial-option-add-quectel-rg255c.patch usb-serial-option-add-telit-fn920c04-ecm-compositions.patch @@ -328,5 +323,4 @@ nfsd-define-a-proc_layoutcommit-for-the-flexfiles-layout-type.patch fuse-fix-livelock-in-synchronous-file-put-from-fuseblk-workers.patch arch_topology-fix-incorrect-error-check-in-topology_parse_cpu_capacity.patch net-rtnetlink-fix-module-reference-count-leak-issue-in-rtnetlink_rcv_msg.patch -risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch fsdax-fix-infinite-loop-in-dax_iomap_rw.patch diff --git a/queue-5.15/risc-v-correctly-print-supported-extensions.patch b/queue-5.15/risc-v-correctly-print-supported-extensions.patch deleted file mode 100644 index 84fba001fc..0000000000 --- a/queue-5.15/risc-v-correctly-print-supported-extensions.patch +++ /dev/null @@ -1,70 +0,0 @@ -From ddcb73be11eb65f25d9bffed15064862f48c79e0 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 14 Mar 2022 13:38:40 -0700 -Subject: RISC-V: Correctly print supported extensions - -From: Tsukasa OI - -[ Upstream commit 58004f266918912771ee71f46bfb92bf64ab9108 ] - -This commit replaces BITS_PER_LONG with number of alphabet letters. - -Current ISA pretty-printing code expects extension 'a' (bit 0) through -'z' (bit 25). Although bit 26 and higher is not currently used (thus never -cause an issue in practice), it will be an annoying problem if we start to -use those in the future. - -This commit disables printing high bits for now. - -Reviewed-by: Anup Patel -Tested-by: Heiko Stuebner -Signed-off-by: Tsukasa OI -Signed-off-by: Atish Patra -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpufeature.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index d959d207a40d6..dd3d57eb4eead 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -13,6 +13,8 @@ - #include - #include - -+#define NUM_ALPHA_EXTS ('z' - 'a' + 1) -+ - unsigned long elf_hwcap __read_mostly; - - /* Host ISA bitmap */ -@@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) - { - struct device_node *node; - const char *isa; -- char print_str[BITS_PER_LONG + 1]; -+ char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; - static unsigned long isa2hwcap[256] = {0}; - -@@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) - } - - memset(print_str, 0, sizeof(print_str)); -- for (i = 0, j = 0; i < BITS_PER_LONG; i++) -+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) - if (riscv_isa[0] & BIT_MASK(i)) - print_str[j++] = (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); - - memset(print_str, 0, sizeof(print_str)); -- for (i = 0, j = 0; i < BITS_PER_LONG; i++) -+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) - if (elf_hwcap & BIT_MASK(i)) - print_str[j++] = (char)('a' + i); - pr_info("riscv: ELF capabilities %s\n", print_str); --- -2.51.0 - diff --git a/queue-5.15/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch b/queue-5.15/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch deleted file mode 100644 index 62c00fcb73..0000000000 --- a/queue-5.15/risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c4676f8dc1e12e68d6511f9ed89707fdad4c962c Mon Sep 17 00:00:00 2001 -From: Anup Patel -Date: Fri, 27 Oct 2023 21:12:53 +0530 -Subject: RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs - -From: Anup Patel - -commit c4676f8dc1e12e68d6511f9ed89707fdad4c962c upstream. - -The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails -for HARTs disabled in the DT. This results in the following warning -thrown by the RISC-V INTC driver for the E-core on SiFive boards: - -[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller - -The riscv_of_parent_hartid() is only expected to read the hartid -from the DT so we directly call of_get_cpu_hwid() instead of calling -riscv_of_processor_hartid(). - -Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64") -Signed-off-by: Anup Patel -Reviewed-by: Atish Patra -Link: https://lore.kernel.org/r/20231027154254.355853-2-apatel@ventanamicro.com -Signed-off-by: Palmer Dabbelt -Signed-off-by: Greg Kroah-Hartman ---- - arch/riscv/kernel/cpu.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -50,13 +50,14 @@ int riscv_of_processor_hartid(struct dev - */ - int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) - { -- int rc; -- - for (; node; node = node->parent) { - if (of_device_is_compatible(node, "riscv")) { -- rc = riscv_of_processor_hartid(node, hartid); -- if (!rc) -- return 0; -+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0); -+ if (*hartid == ~0UL) { -+ pr_warn("Found CPU without hart ID\n"); -+ return -ENODEV; -+ } -+ return 0; - } - } - diff --git a/queue-5.15/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch b/queue-5.15/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch deleted file mode 100644 index b15dc80af4..0000000000 --- a/queue-5.15/risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 9618dd476d86fea6ef9c76c7106555e01910677d Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 14 Oct 2025 22:00:09 +0530 -Subject: RISC-V: Don't print details of CPUs disabled in DT - -From: Anup Patel - -[ Upstream commit d2721bb165b3ee00dd23525885381af07fec852a ] - -Early boot stages may disable CPU DT nodes for unavailable -CPUs based on SKU, pinstraps, eFuse, etc. Currently, the -riscv_early_of_processor_hartid() prints details of a CPU -if it is disabled in DT which has no value and gives a -false impression to the users that there some issue with -the CPU. - -Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled") -Signed-off-by: Anup Patel -Reviewed-by: Andrew Jones -Reviewed-by: Conor Dooley -Link: https://lore.kernel.org/r/20251014163009.182381-1-apatel@ventanamicro.com -Signed-off-by: Paul Walmsley -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpu.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index 11d6d6cc61d51..39013aedbe0ab 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -27,10 +27,8 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) - return -ENODEV; - } - -- if (!of_device_is_available(node)) { -- pr_info("CPU with hartid=%lu is not available\n", *hart); -+ if (!of_device_is_available(node)) - return -ENODEV; -- } - - if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); --- -2.51.0 - diff --git a/queue-5.15/risc-v-minimal-parser-for-riscv-isa-strings.patch b/queue-5.15/risc-v-minimal-parser-for-riscv-isa-strings.patch deleted file mode 100644 index 648ca5ba82..0000000000 --- a/queue-5.15/risc-v-minimal-parser-for-riscv-isa-strings.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 2908b9be2d473ce179ad478adc64fa0e1ee11007 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 14 Mar 2022 13:38:41 -0700 -Subject: RISC-V: Minimal parser for "riscv, isa" strings - -From: Tsukasa OI - -[ Upstream commit 2a31c54be097c74344b4fab20ea6104012d2cb8b ] - -Current hart ISA ("riscv,isa") parser don't correctly parse: - -1. Multi-letter extensions -2. Version numbers - -All ISA extensions ratified recently has multi-letter extensions -(except 'H'). The current "riscv,isa" parser that is easily confused -by multi-letter extensions and "p" in version numbers can be a huge -problem for adding new extensions through the device tree. - -Leaving it would create incompatible hacks and would make "riscv,isa" -value unreliable. - -This commit implements minimal parser for "riscv,isa" strings. With this, -we can safely ignore multi-letter extensions and version numbers. - -[Improved commit text and fixed a bug around 's' in base extension] -Signed-off-by: Atish Patra -[Fixed workaround for QEMU] -Signed-off-by: Tsukasa OI -Tested-by: Heiko Stuebner -Reviewed-by: Anup Patel -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------ - 1 file changed, 61 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index dd3d57eb4eead..72c5f6ef56b5a 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -7,6 +7,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) - struct device_node *node; - const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; -- size_t i, j, isa_len; -+ int i, j; - static unsigned long isa2hwcap[256] = {0}; - - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; -@@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void) - continue; - } - -- i = 0; -- isa_len = strlen(isa); - #if IS_ENABLED(CONFIG_32BIT) - if (!strncmp(isa, "rv32", 4)) -- i += 4; -+ isa += 4; - #elif IS_ENABLED(CONFIG_64BIT) - if (!strncmp(isa, "rv64", 4)) -- i += 4; -+ isa += 4; - #endif -- for (; i < isa_len; ++i) { -- this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; -+ for (; *isa; ++isa) { -+ const char *ext = isa++; -+ const char *ext_end = isa; -+ bool ext_long = false, ext_err = false; -+ -+ switch (*ext) { -+ case 's': -+ /** -+ * Workaround for invalid single-letter 's' & 'u'(QEMU). -+ * No need to set the bit in riscv_isa as 's' & 'u' are -+ * not valid ISA extensions. It works until multi-letter -+ * extension starting with "Su" appears. -+ */ -+ if (ext[-1] != '_' && ext[1] == 'u') { -+ ++isa; -+ ext_err = true; -+ break; -+ } -+ fallthrough; -+ case 'x': -+ case 'z': -+ ext_long = true; -+ /* Multi-letter extension must be delimited */ -+ for (; *isa && *isa != '_'; ++isa) -+ if (!islower(*isa) && !isdigit(*isa)) -+ ext_err = true; -+ break; -+ default: -+ if (unlikely(!islower(*ext))) { -+ ext_err = true; -+ break; -+ } -+ /* Find next extension */ -+ if (!isdigit(*isa)) -+ break; -+ /* Skip the minor version */ -+ while (isdigit(*++isa)) -+ ; -+ if (*isa != 'p') -+ break; -+ if (!isdigit(*++isa)) { -+ --isa; -+ break; -+ } -+ /* Skip the major version */ -+ while (isdigit(*++isa)) -+ ; -+ break; -+ } -+ if (*isa != '_') -+ --isa; - /* -- * TODO: X, Y and Z extension parsing for Host ISA -- * bitmap will be added in-future. -+ * TODO: Full version-aware handling including -+ * multi-letter extensions will be added in-future. - */ -- if ('a' <= isa[i] && isa[i] < 'x') -- this_isa |= (1UL << (isa[i] - 'a')); -+ if (ext_err || ext_long) -+ continue; -+ this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; -+ this_isa |= (1UL << (*ext - 'a')); - } - - /* --- -2.51.0 - diff --git a/queue-5.15/riscv-cpu-add-64bit-hartid-support-on-rv64.patch b/queue-5.15/riscv-cpu-add-64bit-hartid-support-on-rv64.patch deleted file mode 100644 index dab23038d2..0000000000 --- a/queue-5.15/riscv-cpu-add-64bit-hartid-support-on-rv64.patch +++ /dev/null @@ -1,260 +0,0 @@ -From 5d6448e7ba77a1095d44c6dddc519f41301ff78a Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 27 May 2022 10:47:42 +0530 -Subject: riscv: cpu: Add 64bit hartid support on RV64 - -From: Sunil V L - -[ Upstream commit ad635e723e17379b192a5ba9c182e3eedfc24d16 ] - -The hartid can be a 64bit value on RV64 platforms. - -Add support for 64bit hartid in riscv_of_processor_hartid() and -update its callers. - -Signed-off-by: Sunil V L -Reviewed-by: Atish Patra -Link: https://lore.kernel.org/r/20220527051743.2829940-5-sunilvl@ventanamicro.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/include/asm/processor.h | 4 ++-- - arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- - arch/riscv/kernel/cpufeature.c | 6 ++++-- - arch/riscv/kernel/smpboot.c | 9 +++++---- - drivers/clocksource/timer-riscv.c | 15 ++++++++------- - drivers/irqchip/irq-riscv-intc.c | 7 ++++--- - drivers/irqchip/irq-sifive-plic.c | 7 ++++--- - 7 files changed, 42 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h -index 0749924d9e552..99fae93985062 100644 ---- a/arch/riscv/include/asm/processor.h -+++ b/arch/riscv/include/asm/processor.h -@@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void) - } - - struct device_node; --int riscv_of_processor_hartid(struct device_node *node); --int riscv_of_parent_hartid(struct device_node *node); -+int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); -+int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); - - extern void riscv_fill_hwcap(void); - extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index f13b2c9ea912d..11d6d6cc61d51 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -12,37 +12,36 @@ - * Returns the hart ID of the given device tree node, or -ENODEV if the node - * isn't an enabled and valid RISC-V hart node. - */ --int riscv_of_processor_hartid(struct device_node *node) -+int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) - { - const char *isa; -- u32 hart; - - if (!of_device_is_compatible(node, "riscv")) { - pr_warn("Found incompatible CPU\n"); - return -ENODEV; - } - -- hart = of_get_cpu_hwid(node, 0); -- if (hart == ~0U) { -+ *hart = (unsigned long) of_get_cpu_hwid(node, 0); -+ if (*hart == ~0UL) { - pr_warn("Found CPU without hart ID\n"); - return -ENODEV; - } - - if (!of_device_is_available(node)) { -- pr_info("CPU with hartid=%d is not available\n", hart); -+ pr_info("CPU with hartid=%lu is not available\n", *hart); - return -ENODEV; - } - - if (of_property_read_string(node, "riscv,isa", &isa)) { -- pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); -+ pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); - return -ENODEV; - } - if (isa[0] != 'r' || isa[1] != 'v') { -- pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); -+ pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); - return -ENODEV; - } - -- return hart; -+ return 0; - } - - /* -@@ -51,11 +50,16 @@ int riscv_of_processor_hartid(struct device_node *node) - * To achieve this, we walk up the DT tree until we find an active - * RISC-V core (HART) node and extract the cpuid from it. - */ --int riscv_of_parent_hartid(struct device_node *node) -+int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) - { -+ int rc; -+ - for (; node; node = node->parent) { -- if (of_device_is_compatible(node, "riscv")) -- return riscv_of_processor_hartid(node); -+ if (of_device_is_compatible(node, "riscv")) { -+ rc = riscv_of_processor_hartid(node, hartid); -+ if (!rc) -+ return 0; -+ } - } - - return -1; -diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c -index 72c5f6ef56b5a..5d1af366116b0 100644 ---- a/arch/riscv/kernel/cpufeature.c -+++ b/arch/riscv/kernel/cpufeature.c -@@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void) - struct device_node *node; - const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; -- int i, j; -+ int i, j, rc; - static unsigned long isa2hwcap[256] = {0}; -+ unsigned long hartid; - - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; -@@ -85,7 +86,8 @@ void __init riscv_fill_hwcap(void) - unsigned long this_hwcap = 0; - unsigned long this_isa = 0; - -- if (riscv_of_processor_hartid(node) < 0) -+ rc = riscv_of_processor_hartid(node, &hartid); -+ if (rc < 0) - continue; - - if (of_property_read_string(node, "riscv,isa", &isa)) { -diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c -index 0f323e935dd89..3d3def84f81c1 100644 ---- a/arch/riscv/kernel/smpboot.c -+++ b/arch/riscv/kernel/smpboot.c -@@ -77,15 +77,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) - void __init setup_smp(void) - { - struct device_node *dn; -- int hart; -+ unsigned long hart; - bool found_boot_cpu = false; - int cpuid = 1; -+ int rc; - - cpu_set_ops(0); - - for_each_of_cpu_node(dn) { -- hart = riscv_of_processor_hartid(dn); -- if (hart < 0) -+ rc = riscv_of_processor_hartid(dn, &hart); -+ if (rc < 0) - continue; - - if (hart == cpuid_to_hartid_map(0)) { -@@ -95,7 +96,7 @@ void __init setup_smp(void) - continue; - } - if (cpuid >= NR_CPUS) { -- pr_warn("Invalid cpuid [%d] for hartid [%d]\n", -+ pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", - cpuid, hart); - break; - } -diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c -index c51c5ed15aa75..4930d08c9374a 100644 ---- a/drivers/clocksource/timer-riscv.c -+++ b/drivers/clocksource/timer-riscv.c -@@ -92,20 +92,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) - - static int __init riscv_timer_init_dt(struct device_node *n) - { -- int cpuid, hartid, error; -+ int cpuid, error; -+ unsigned long hartid; - struct device_node *child; - struct irq_domain *domain; - -- hartid = riscv_of_processor_hartid(n); -- if (hartid < 0) { -- pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", -+ error = riscv_of_processor_hartid(n, &hartid); -+ if (error < 0) { -+ pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); -- return hartid; -+ return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { -- pr_warn("Invalid cpuid for hartid [%d]\n", hartid); -+ pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - -@@ -131,7 +132,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) - return -ENODEV; - } - -- pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", -+ pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); - error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); - if (error) { -diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c -index 54c99441c1b54..ff4a69d276ca6 100644 ---- a/drivers/irqchip/irq-riscv-intc.c -+++ b/drivers/irqchip/irq-riscv-intc.c -@@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { - static int __init riscv_intc_init(struct device_node *node, - struct device_node *parent) - { -- int rc, hartid; -+ int rc; -+ unsigned long hartid; - -- hartid = riscv_of_parent_hartid(node); -- if (hartid < 0) { -+ rc = riscv_of_parent_hartid(node, &hartid); -+ if (rc < 0) { - pr_warn("unable to find hart id for %pOF\n", node); - return 0; - } -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 09cc98266d30f..00b64fb882b18 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -313,7 +313,8 @@ static int __init plic_init(struct device_node *node, - for (i = 0; i < nr_contexts; i++) { - struct of_phandle_args parent; - irq_hw_number_t hwirq; -- int cpu, hartid; -+ int cpu; -+ unsigned long hartid; - - if (of_irq_parse_one(node, i, &parent)) { - pr_err("failed to parse parent for context %d.\n", i); -@@ -327,8 +328,8 @@ static int __init plic_init(struct device_node *node, - if (parent.args[0] != RV_IRQ_EXT) - continue; - -- hartid = riscv_of_parent_hartid(parent.np); -- if (hartid < 0) { -+ error = riscv_of_parent_hartid(parent.np, &hartid); -+ if (error < 0) { - pr_warn("failed to parse hart ID for context %d.\n", i); - continue; - } --- -2.51.0 - diff --git a/queue-5.15/riscv-use-of_get_cpu_hwid.patch b/queue-5.15/riscv-use-of_get_cpu_hwid.patch deleted file mode 100644 index 6b16896ae3..0000000000 --- a/queue-5.15/riscv-use-of_get_cpu_hwid.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 39a229d1aca075a66b8f8e81cf91fea61a85f1ac Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 6 Oct 2021 11:43:28 -0500 -Subject: riscv: Use of_get_cpu_hwid() - -From: Rob Herring - -[ Upstream commit bd2259ee458e299ec14061da7faddcfb0d54d154 ] - -Replace open coded parsing of CPU nodes' 'reg' property with -of_get_cpu_hwid(). - -Cc: Paul Walmsley -Cc: Palmer Dabbelt -Cc: Albert Ou -Cc: linux-riscv@lists.infradead.org -Signed-off-by: Rob Herring -Link: https://lore.kernel.org/r/20211006164332.1981454-9-robh@kernel.org -Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cpu.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c -index 6d59e6906fddf..f13b2c9ea912d 100644 ---- a/arch/riscv/kernel/cpu.c -+++ b/arch/riscv/kernel/cpu.c -@@ -22,7 +22,8 @@ int riscv_of_processor_hartid(struct device_node *node) - return -ENODEV; - } - -- if (of_property_read_u32(node, "reg", &hart)) { -+ hart = of_get_cpu_hwid(node, 0); -+ if (hart == ~0U) { - pr_warn("Found CPU without hart ID\n"); - return -ENODEV; - } --- -2.51.0 - diff --git a/queue-5.15/series b/queue-5.15/series index 272dd7b608..d3a94458b6 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -67,11 +67,6 @@ ocfs2-clear-extent-cache-after-moving-defragmenting-extents.patch vsock-fix-lock-inversion-in-vsock_assign_transport.patch net-usb-rtl8150-fix-frame-padding.patch net-ravb-ensure-memory-write-completes-before-ringing-tx-doorbell.patch -riscv-use-of_get_cpu_hwid.patch -risc-v-correctly-print-supported-extensions.patch -risc-v-minimal-parser-for-riscv-isa-strings.patch -riscv-cpu-add-64bit-hartid-support-on-rv64.patch -risc-v-don-t-print-details-of-cpus-disabled-in-dt.patch usb-serial-option-add-unisoc-uis7720.patch usb-serial-option-add-quectel-rg255c.patch usb-serial-option-add-telit-fn920c04-ecm-compositions.patch @@ -120,4 +115,3 @@ usb-gadget-f_ncm-refactor-bind-path-to-use-__free.patch usb-gadget-f_acm-refactor-bind-path-to-use-__free.patch net-rtnetlink-fix-module-reference-count-leak-issue-in-rtnetlink_rcv_msg.patch pci-rcar-demote-warn-to-dev_warn_ratelimited-in-rcar_pcie_wakeup.patch -risc-v-don-t-fail-in-riscv_of_parent_hartid-for-disabled-harts.patch -- 2.47.3