From e4a7c22de9279174bbba7f11f4fc366307369ab6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 4 Jun 2016 10:06:31 -0700 Subject: [PATCH] 4.4-stable patches added patches: mips-math-emu-fix-jalr-emulation-when-rd-0.patch mips-msa-fix-a-link-error-on-_init_msa_upper-with-older-gcc.patch mips64-r6-r2-emulation-bugfix.patch --- ...ath-emu-fix-jalr-emulation-when-rd-0.patch | 48 ++++ ...or-on-_init_msa_upper-with-older-gcc.patch | 87 +++++++ queue-4.4/mips64-r6-r2-emulation-bugfix.patch | 229 ++++++++++++++++++ 3 files changed, 364 insertions(+) create mode 100644 queue-4.4/mips-math-emu-fix-jalr-emulation-when-rd-0.patch create mode 100644 queue-4.4/mips-msa-fix-a-link-error-on-_init_msa_upper-with-older-gcc.patch create mode 100644 queue-4.4/mips64-r6-r2-emulation-bugfix.patch diff --git a/queue-4.4/mips-math-emu-fix-jalr-emulation-when-rd-0.patch b/queue-4.4/mips-math-emu-fix-jalr-emulation-when-rd-0.patch new file mode 100644 index 00000000000..10aa00a7aed --- /dev/null +++ b/queue-4.4/mips-math-emu-fix-jalr-emulation-when-rd-0.patch @@ -0,0 +1,48 @@ +From ab4a92e66741b35ca12f8497896bafbe579c28a1 Mon Sep 17 00:00:00 2001 +From: Paul Burton +Date: Thu, 21 Apr 2016 14:04:55 +0100 +Subject: MIPS: math-emu: Fix jalr emulation when rd == $0 + +From: Paul Burton + +commit ab4a92e66741b35ca12f8497896bafbe579c28a1 upstream. + +When emulating a jalr instruction with rd == $0, the code in +isBranchInstr was incorrectly writing to GPR $0 which should actually +always remain zeroed. This would lead to any further instructions +emulated which use $0 operating on a bogus value until the task is next +context switched, at which point the value of $0 in the task context +would be restored to the correct zero by a store in SAVE_SOME. Fix this +by not writing to rd if it is $0. + +Fixes: 102cedc32a6e ("MIPS: microMIPS: Floating point support.") +Signed-off-by: Paul Burton +Cc: Maciej W. Rozycki +Cc: James Hogan +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/13160/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/math-emu/cp1emu.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/arch/mips/math-emu/cp1emu.c ++++ b/arch/mips/math-emu/cp1emu.c +@@ -445,9 +445,11 @@ static int isBranchInstr(struct pt_regs + case spec_op: + switch (insn.r_format.func) { + case jalr_op: +- regs->regs[insn.r_format.rd] = +- regs->cp0_epc + dec_insn.pc_inc + +- dec_insn.next_pc_inc; ++ if (insn.r_format.rd != 0) { ++ regs->regs[insn.r_format.rd] = ++ regs->cp0_epc + dec_insn.pc_inc + ++ dec_insn.next_pc_inc; ++ } + /* Fall through */ + case jr_op: + /* For R6, JR already emulated in jalr_op */ diff --git a/queue-4.4/mips-msa-fix-a-link-error-on-_init_msa_upper-with-older-gcc.patch b/queue-4.4/mips-msa-fix-a-link-error-on-_init_msa_upper-with-older-gcc.patch new file mode 100644 index 00000000000..3a7fd543fd0 --- /dev/null +++ b/queue-4.4/mips-msa-fix-a-link-error-on-_init_msa_upper-with-older-gcc.patch @@ -0,0 +1,87 @@ +From e49d38488515057dba8f0c2ba4cfde5be4a7281f Mon Sep 17 00:00:00 2001 +From: "Maciej W. Rozycki" +Date: Tue, 17 May 2016 06:12:27 +0100 +Subject: MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC + +From: Maciej W. Rozycki + +commit e49d38488515057dba8f0c2ba4cfde5be4a7281f upstream. + +Fix a build regression from commit c9017757c532 ("MIPS: init upper 64b +of vector registers when MSA is first used"): + +arch/mips/built-in.o: In function `enable_restore_fp_context': +traps.c:(.text+0xbb90): undefined reference to `_init_msa_upper' +traps.c:(.text+0xbb90): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' +traps.c:(.text+0xbef0): undefined reference to `_init_msa_upper' +traps.c:(.text+0xbef0): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' + +to !CONFIG_CPU_HAS_MSA configurations with older GCC versions, which are +unable to figure out that calls to `_init_msa_upper' are indeed dead. +Of the many ways to tackle this failure choose the approach we have +already taken in `thread_msa_context_live'. + +[ralf@linux-mips.org: Drop patch segment to junk file.] + +Signed-off-by: Maciej W. Rozycki +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/13271/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/include/asm/msa.h | 13 +++++++++++++ + arch/mips/kernel/traps.c | 6 +++--- + 2 files changed, 16 insertions(+), 3 deletions(-) + +--- a/arch/mips/include/asm/msa.h ++++ b/arch/mips/include/asm/msa.h +@@ -147,6 +147,19 @@ static inline void restore_msa(struct ta + _restore_msa(t); + } + ++static inline void init_msa_upper(void) ++{ ++ /* ++ * Check cpu_has_msa only if it's a constant. This will allow the ++ * compiler to optimise out code for CPUs without MSA without adding ++ * an extra redundant check for CPUs with MSA. ++ */ ++ if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa) ++ return; ++ ++ _init_msa_upper(); ++} ++ + #ifdef TOOLCHAIN_SUPPORTS_MSA + + #define __BUILD_MSA_CTL_REG(name, cs) \ +--- a/arch/mips/kernel/traps.c ++++ b/arch/mips/kernel/traps.c +@@ -1241,7 +1241,7 @@ static int enable_restore_fp_context(int + err = init_fpu(); + if (msa && !err) { + enable_msa(); +- _init_msa_upper(); ++ init_msa_upper(); + set_thread_flag(TIF_USEDMSA); + set_thread_flag(TIF_MSA_CTX_LIVE); + } +@@ -1304,7 +1304,7 @@ static int enable_restore_fp_context(int + */ + prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); + if (!prior_msa && was_fpu_owner) { +- _init_msa_upper(); ++ init_msa_upper(); + + goto out; + } +@@ -1321,7 +1321,7 @@ static int enable_restore_fp_context(int + * of each vector register such that it cannot see data left + * behind by another task. + */ +- _init_msa_upper(); ++ init_msa_upper(); + } else { + /* We need to restore the vector context. */ + restore_msa(current); diff --git a/queue-4.4/mips64-r6-r2-emulation-bugfix.patch b/queue-4.4/mips64-r6-r2-emulation-bugfix.patch new file mode 100644 index 00000000000..6a729b31106 --- /dev/null +++ b/queue-4.4/mips64-r6-r2-emulation-bugfix.patch @@ -0,0 +1,229 @@ +From 41fa29e4d8cf4150568a0fe9bb4d62229f9caed5 Mon Sep 17 00:00:00 2001 +From: Leonid Yegoshin +Date: Tue, 28 Apr 2015 12:53:35 -0700 +Subject: MIPS64: R6: R2 emulation bugfix + +From: Leonid Yegoshin + +commit 41fa29e4d8cf4150568a0fe9bb4d62229f9caed5 upstream. + +Error recovery pointers for fixups was improperly set as ".word" +which is unsuitable for MIPS64. + +Replaced by STR(PTR) + +[ralf@linux-mips.org: Apply changes as requested in the review process.] + +Signed-off-by: Leonid Yegoshin +Reviewed-by: James Hogan +Reviewed-by: Markos Chandras +Fixes: b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") +Cc: macro@linux-mips.org +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/9911/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/kernel/mips-r2-to-r6-emul.c | 105 +++++++++++++++++----------------- + 1 file changed, 53 insertions(+), 52 deletions(-) + +--- a/arch/mips/kernel/mips-r2-to-r6-emul.c ++++ b/arch/mips/kernel/mips-r2-to-r6-emul.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -1251,10 +1252,10 @@ fpu_emul: + " j 10b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1326,10 +1327,10 @@ fpu_emul: + " j 10b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1397,10 +1398,10 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1467,10 +1468,10 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1582,14 +1583,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1701,14 +1702,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1820,14 +1821,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1938,14 +1939,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -2000,7 +2001,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "=&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV) +@@ -2058,7 +2059,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "+&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV)); +@@ -2119,7 +2120,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "=&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV) +@@ -2182,7 +2183,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "+&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV)); -- 2.47.3