From e58c8ba5f6b1bd9af00cf5fcebce4bdba0f0aabb Mon Sep 17 00:00:00 2001 From: ths Date: Fri, 13 Apr 2007 20:17:54 +0000 Subject: [PATCH] Another fix for CP0 Cause register handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-mips/helper.c | 2 +- target-mips/op.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/helper.c b/target-mips/helper.c index c23e9c6b375..71a9723396c 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -403,7 +403,7 @@ void do_interrupt (CPUState *env) env->PC = (int32_t)(env->CP0_EBase & ~0x3ff); } env->PC += offset; - env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: if (logfile) { diff --git a/target-mips/op.c b/target-mips/op.c index 9818847fe39..3951204169e 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1401,7 +1401,7 @@ void op_mtc0_cause (void) if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) mask |= 1 << CP0Ca_DC; - env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask); + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); /* Handle the software interrupt as an hardware one, as they are very similar */ -- 2.39.5