From e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba Mon Sep 17 00:00:00 2001 From: Victor Do Nascimento Date: Thu, 4 Jan 2024 14:06:38 +0000 Subject: [PATCH] aarch64: rcpc3: Add integer load/store insns Along with the relevant unit tests and updates to the existing regression tests, this adds support for the following novel rcpc3 insns: LDIAPP , , [] LDIAPP , , [], #8 LDIAPP , , [] LDIAPP , , [], #16 STILP , , [] STILP , , [, #-8]! STILP , , [] STILP , , [, #-16]! LDAPR , [], #4 LDAPR , [], #8 STLR , [, #-4]! STLR , [, #-8]! --- gas/testsuite/gas/aarch64/illegal-ldapr.l | 4 ++-- gas/testsuite/gas/aarch64/rcpc3-fail.d | 3 +++ gas/testsuite/gas/aarch64/rcpc3-fail.l | 9 +++++++++ gas/testsuite/gas/aarch64/rcpc3-fail.s | 13 +++++++++++++ gas/testsuite/gas/aarch64/rcpc3.d | 21 +++++++++++++++++++++ gas/testsuite/gas/aarch64/rcpc3.s | 17 +++++++++++++++++ include/opcode/aarch64.h | 1 + opcodes/aarch64-tbl.h | 5 +++++ 8 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.d create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.l create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.s create mode 100644 gas/testsuite/gas/aarch64/rcpc3.d create mode 100644 gas/testsuite/gas/aarch64/rcpc3.s diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l index 5e3ca6d2e5c..8811b730011 100644 --- a/gas/testsuite/gas/aarch64/illegal-ldapr.l +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l @@ -22,7 +22,7 @@ [^:]+:23: Info: macro .* [^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]' [^:]+:23: Info: macro .* -[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!' +[^:]+:7: Error: unexpected address writeback at operand 2 -- `ldapr w1,\[x7,#8\]!' [^:]+:23: Info: macro .* -[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8' +[^:]+:8: Error: invalid increment amount at operand 2 -- `ldapr w1,\[x7\],#8' [^:]+:23: Info: macro .* diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.d b/gas/testsuite/gas/aarch64/rcpc3-fail.d new file mode 100644 index 00000000000..508a27f5a39 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.d @@ -0,0 +1,3 @@ +#name: RCPC3 GPR load/store illegal +#as: -march=armv8.3-a+rcpc3 -mno-verbose-error +#error_output: rcpc3-fail.l diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.l b/gas/testsuite/gas/aarch64/rcpc3-fail.l new file mode 100644 index 00000000000..4b33c8524e5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.l @@ -0,0 +1,9 @@ +[^:]+: Assembler messages: +[^:]+:3: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp w0,w1,\[x3,#8\]' +[^:]+:4: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp x0,x1,\[x3,#16\]' +[^:]+:6: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp w0,w1,\[x3,#8\]' +[^:]+:7: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp x0,x1,\[x3,#16\]' +[^:]+:9: Error: invalid addressing mode at operand 3 -- `stilp w0,w1,\[x3\],#8' +[^:]+:10: Error: invalid addressing mode at operand 3 -- `stilp x0,x1,\[x3\],#16' +[^:]+:12: Error: invalid addressing mode at operand 3 -- `ldiapp w0,w1,\[x3,#-8\]!' +[^:]+:13: Error: invalid addressing mode at operand 3 -- `ldiapp x0,x1,\[x3,#-16\]!' diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.s b/gas/testsuite/gas/aarch64/rcpc3-fail.s new file mode 100644 index 00000000000..23b9eaaf19a --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.s @@ -0,0 +1,13 @@ +.text + + ldiapp w0, w1, [x3, #8] + ldiapp x0, x1, [x3, #16] + + stilp w0, w1, [x3, #8] + stilp x0, x1, [x3, #16] + + stilp w0, w1, [x3], #8 + stilp x0, x1, [x3], #16 + + ldiapp w0, w1, [x3, #-8]! + ldiapp x0, x1, [x3, #-16]! diff --git a/gas/testsuite/gas/aarch64/rcpc3.d b/gas/testsuite/gas/aarch64/rcpc3.d new file mode 100644 index 00000000000..4560ed09e5d --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3.d @@ -0,0 +1,21 @@ +#name: RCPC3 GPR load/store +#as: -march=armv8.2-a+rcpc3 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: d9411860 ldiapp x0, x1, \[x3\] + 4: 99411860 ldiapp w0, w1, \[x3\] + 8: d9410860 ldiapp x0, x1, \[x3\], #16 + c: 99410860 ldiapp w0, w1, \[x3\], #8 + 10: d9011860 stilp x0, x1, \[x3\] + 14: 99011860 stilp w0, w1, \[x3\] + 18: d9010860 stilp x0, x1, \[x3, #-16\]! + 1c: 99010860 stilp w0, w1, \[x3, #-8\]! + 20: 99c00841 ldapr w1, \[x2\], #4 + 24: d9c00841 ldapr x1, \[x2\], #8 + 28: 99800841 stlr w1, \[x2, #-4\]! + 2c: d9800841 stlr x1, \[x2, #-8\]! diff --git a/gas/testsuite/gas/aarch64/rcpc3.s b/gas/testsuite/gas/aarch64/rcpc3.s new file mode 100644 index 00000000000..2a877341e41 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3.s @@ -0,0 +1,17 @@ +.text + + ldiapp x0, x1, [x3] + ldiapp w0, w1, [x3] + ldiapp x0, x1, [x3], #16 + ldiapp w0, w1, [x3], #8 + + stilp x0, x1, [x3] + stilp w0, w1, [x3] + stilp x0, x1, [x3, #-16]! + stilp w0, w1, [x3, #-8]! + + ldapr w1, [x2], #4 + ldapr x1, [x2], #8 + + stlr w1, [x2, #-4]! + stlr x1, [x2, #-8]! diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 44d6aafd4b3..6f02f472fda 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1013,6 +1013,7 @@ enum aarch64_insn_class the, sve2_urqvs, sve_index1, + rcpc3 }; /* Opcode enumerators. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1b3895be25d..8855c831ccf 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4216,6 +4216,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + /* RCPC3 extension. */ + RCPC3_INSN ("ldiapp", 0x19400800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_POSTIND), QL_R2NIL, F_RCPC3_SIZE), + RCPC3_INSN ("stilp", 0x19000800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_PREIND_WB), QL_R2NIL, F_RCPC3_SIZE), + RCPC3_INSN ("ldapr", 0x19c00800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_POSTIND), QL_R1NIL, F_RCPC3_SIZE), + RCPC3_INSN ("stlr", 0x19800800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_PREIND_WB), QL_R1NIL, F_RCPC3_SIZE), /* Move wide (immediate). */ CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), -- 2.39.5