From ef5cc6bbb60b0ccbc10fb76b697ae02f28af18c0 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Wed, 8 Jun 2022 07:14:11 +0000 Subject: [PATCH] arm: Add star-mc1 cpu The star-mc1 is an embedded processor with armv8m architecture. Majorly it is designed to meet the requirements of AIoT application performance, power consumption and security. This patch is to add support of star-mc1 cpu. Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in (star-mc1): New cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * doc/invoke.texi: Update docs. --- gcc/config/arm/arm-cpus.in | 10 ++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 4 ++-- gcc/doc/invoke.texi | 8 +++++--- 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f7..5a63bc548e54 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1638,6 +1638,16 @@ begin cpu cortex-m55 vendor 41 end cpu cortex-m55 +begin cpu star-mc1 + cname starmc1 + tune flags LDSCHED + architecture armv8-m.main+dsp+fp + option nofp remove ALL_FP + option nodsp remove armv7em + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu star-mc1 + # V8 R-profile implementations. begin cpu cortex-r52 cname cortexr52 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ef0cc5ef0c87..e6461abcc57c 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) +EnumValue +Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) + EnumValue Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 342255360424..abc290edd094 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,6 @@ cortexa710,cortexx1,neoversen1, cortexa75cortexa55,cortexa76cortexa55,neoversev1, neoversen2,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52, - cortexr52plus" + cortexm35p,cortexm55,starmc1, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8cd5bdddc5d3..ac0c06cd2b0b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21190,7 +21190,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, -@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. +@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1}, +@samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @@ -21596,8 +21597,9 @@ Development Tools Engineering Specification", which can be found on Mitigate against a potential security issue with the @code{VLLDM} instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option @option{-mcpu=} is used with -@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option -@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation. +@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}. +The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable +the mitigation. @item -mstack-protector-guard=@var{guard} @itemx -mstack-protector-guard-offset=@var{offset} -- 2.47.2