From efacb10c79325089f8854f15590ecfa7ea69bbb3 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 11 Apr 2022 09:54:46 +0200 Subject: [PATCH] 4.9-stable patches added patches: x86-pm-save-the-msr-validity-status-at-context-setup.patch x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch --- queue-4.9/series | 2 + ...msr-validity-status-at-context-setup.patch | 55 +++++++++++++++++ ...lation-related-msrs-during-s3-resume.patch | 60 +++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 queue-4.9/x86-pm-save-the-msr-validity-status-at-context-setup.patch create mode 100644 queue-4.9/x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch diff --git a/queue-4.9/series b/queue-4.9/series index 9eb09b7cf42..21d3ed21ab2 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -191,3 +191,5 @@ drm-imx-fix-memory-leak-in-imx_pd_connector_get_mode.patch drbd-fix-five-use-after-free-bugs-in-get_initial_sta.patch mmmremap.c-avoid-pointless-invalidate_range_start-end-on-mremap-old_size-0.patch mm-mempolicy-fix-mpol_new-leak-in-shared_policy_replace.patch +x86-pm-save-the-msr-validity-status-at-context-setup.patch +x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch diff --git a/queue-4.9/x86-pm-save-the-msr-validity-status-at-context-setup.patch b/queue-4.9/x86-pm-save-the-msr-validity-status-at-context-setup.patch new file mode 100644 index 00000000000..100d3ab27c4 --- /dev/null +++ b/queue-4.9/x86-pm-save-the-msr-validity-status-at-context-setup.patch @@ -0,0 +1,55 @@ +From 73924ec4d560257004d5b5116b22a3647661e364 Mon Sep 17 00:00:00 2001 +From: Pawan Gupta +Date: Mon, 4 Apr 2022 17:34:19 -0700 +Subject: x86/pm: Save the MSR validity status at context setup + +From: Pawan Gupta + +commit 73924ec4d560257004d5b5116b22a3647661e364 upstream. + +The mechanism to save/restore MSRs during S3 suspend/resume checks for +the MSR validity during suspend, and only restores the MSR if its a +valid MSR. This is not optimal, as an invalid MSR will unnecessarily +throw an exception for every suspend cycle. The more invalid MSRs, +higher the impact will be. + +Check and save the MSR validity at setup. This ensures that only valid +MSRs that are guaranteed to not throw an exception will be attempted +during suspend. + +Fixes: 7a9c2dd08ead ("x86/pm: Introduce quirk framework to save/restore extra MSR registers around suspend/resume") +Suggested-by: Dave Hansen +Signed-off-by: Pawan Gupta +Reviewed-by: Dave Hansen +Acked-by: Borislav Petkov +Cc: stable@vger.kernel.org +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/power/cpu.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/arch/x86/power/cpu.c ++++ b/arch/x86/power/cpu.c +@@ -41,7 +41,8 @@ static void msr_save_context(struct save + struct saved_msr *end = msr + ctxt->saved_msrs.num; + + while (msr < end) { +- msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q); ++ if (msr->valid) ++ rdmsrl(msr->info.msr_no, msr->info.reg.q); + msr++; + } + } +@@ -419,8 +420,10 @@ static int msr_build_context(const u32 * + } + + for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) { ++ u64 dummy; ++ + msr_array[i].info.msr_no = msr_id[j]; +- msr_array[i].valid = false; ++ msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy); + msr_array[i].info.reg.q = 0; + } + saved_msrs->num = total_num; diff --git a/queue-4.9/x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch b/queue-4.9/x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch new file mode 100644 index 00000000000..025d61fde26 --- /dev/null +++ b/queue-4.9/x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch @@ -0,0 +1,60 @@ +From e2a1256b17b16f9b9adf1b6fea56819e7b68e463 Mon Sep 17 00:00:00 2001 +From: Pawan Gupta +Date: Mon, 4 Apr 2022 17:35:45 -0700 +Subject: x86/speculation: Restore speculation related MSRs during S3 resume + +From: Pawan Gupta + +commit e2a1256b17b16f9b9adf1b6fea56819e7b68e463 upstream. + +After resuming from suspend-to-RAM, the MSRs that control CPU's +speculative execution behavior are not being restored on the boot CPU. + +These MSRs are used to mitigate speculative execution vulnerabilities. +Not restoring them correctly may leave the CPU vulnerable. Secondary +CPU's MSRs are correctly being restored at S3 resume by +identify_secondary_cpu(). + +During S3 resume, restore these MSRs for boot CPU when restoring its +processor state. + +Fixes: 772439717dbf ("x86/bugs/intel: Set proper CPU features and setup RDS") +Reported-by: Neelima Krishnan +Signed-off-by: Pawan Gupta +Tested-by: Neelima Krishnan +Acked-by: Borislav Petkov +Reviewed-by: Dave Hansen +Cc: stable@vger.kernel.org +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/power/cpu.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/x86/power/cpu.c ++++ b/arch/x86/power/cpu.c +@@ -510,10 +510,24 @@ static int pm_cpu_check(const struct x86 + return ret; + } + ++static void pm_save_spec_msr(void) ++{ ++ u32 spec_msr_id[] = { ++ MSR_IA32_SPEC_CTRL, ++ MSR_IA32_TSX_CTRL, ++ MSR_TSX_FORCE_ABORT, ++ MSR_IA32_MCU_OPT_CTRL, ++ MSR_AMD64_LS_CFG, ++ }; ++ ++ msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id)); ++} ++ + static int pm_check_save_msr(void) + { + dmi_check_system(msr_save_dmi_table); + pm_cpu_check(msr_save_cpu_table); ++ pm_save_spec_msr(); + + return 0; + } -- 2.47.3