From efb8bde8e71c58244b1c0c545e7b2552655bd4fa Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 17 Oct 2015 13:36:49 -0700 Subject: [PATCH] 4.2-stable patches added patches: drm-amdgpu-disable-uvd-pg.patch drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch drm-amdgpu-fix-overflow-on-32bit-systems.patch drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch drm-amdgpu-make-uvd-handle-checking-more-strict.patch drm-amdgpu-restore-lcd-backlight-level-on-resume.patch drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch --- queue-4.2/drm-amdgpu-disable-uvd-pg.patch | 34 ++++++ ...nt-value-for-current-display-engines.patch | 39 ++++++ ...amdgpu-fix-overflow-on-32bit-systems.patch | 33 +++++ ...u-fix-the-uvd-suspend-sequence-order.patch | 72 +++++++++++ ...make-uvd-handle-checking-more-strict.patch | 114 ++++++++++++++++++ ...estore-lcd-backlight-level-on-resume.patch | 35 ++++++ ...le-mipi-sequence-block-v3-gracefully.patch | 68 +++++++++++ ...tor-as-connected-if-we-have-no-state.patch | 42 +++++++ ...y-surface-when-the-bo-is-not-primary.patch | 36 ++++++ ...lock-ioctl-functions-for-kms-drivers.patch | 49 ++++++++ queue-4.2/series | 10 ++ 11 files changed, 532 insertions(+) create mode 100644 queue-4.2/drm-amdgpu-disable-uvd-pg.patch create mode 100644 queue-4.2/drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch create mode 100644 queue-4.2/drm-amdgpu-fix-overflow-on-32bit-systems.patch create mode 100644 queue-4.2/drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch create mode 100644 queue-4.2/drm-amdgpu-make-uvd-handle-checking-more-strict.patch create mode 100644 queue-4.2/drm-amdgpu-restore-lcd-backlight-level-on-resume.patch create mode 100644 queue-4.2/drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch create mode 100644 queue-4.2/drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch create mode 100644 queue-4.2/drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch create mode 100644 queue-4.2/drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch diff --git a/queue-4.2/drm-amdgpu-disable-uvd-pg.patch b/queue-4.2/drm-amdgpu-disable-uvd-pg.patch new file mode 100644 index 00000000000..266f933ec43 --- /dev/null +++ b/queue-4.2/drm-amdgpu-disable-uvd-pg.patch @@ -0,0 +1,34 @@ +From 1ee4478a26cf55c8f8a6219d7e99f2b48959394d Mon Sep 17 00:00:00 2001 +From: Leo Liu +Date: Thu, 10 Sep 2015 13:41:38 -0400 +Subject: drm/amdgpu: Disable UVD PG +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Leo Liu + +commit 1ee4478a26cf55c8f8a6219d7e99f2b48959394d upstream. + +This causes problems with multiple suspend/resume cycles. + +Signed-off-by: Leo Liu +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -1290,7 +1290,8 @@ static int vi_common_early_init(void *ha + case CHIP_CARRIZO: + adev->has_uvd = true; + adev->cg_flags = 0; +- adev->pg_flags = AMDGPU_PG_SUPPORT_UVD | AMDGPU_PG_SUPPORT_VCE; ++ /* Disable UVD pg */ ++ adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE; + adev->external_rev_id = adev->rev_id + 0x1; + if (amdgpu_smc_load_fw && smc_enabled) + adev->firmware.smu_load = true; diff --git a/queue-4.2/drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch b/queue-4.2/drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch new file mode 100644 index 00000000000..85fc92c905e --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch @@ -0,0 +1,39 @@ +From 5a6adfa20b622a273205e33b20c12332aa7eb724 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 22 Sep 2015 10:06:45 -0400 +Subject: drm/amdgpu: Fix max_vblank_count value for current display engines +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 5a6adfa20b622a273205e33b20c12332aa7eb724 upstream. + +The value was much too low, which could cause the userspace visible +vblank counter to move backwards when the hardware counter wrapped +around. + +Ported from radeon commit: +b0b9bb4dd51f396dcf843831905f729e74b0c8c0 + +Reviewed-by: Christian König +Reviewed-by: Jammy Zhou +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +@@ -140,7 +140,7 @@ void amdgpu_irq_preinstall(struct drm_de + */ + int amdgpu_irq_postinstall(struct drm_device *dev) + { +- dev->max_vblank_count = 0x001fffff; ++ dev->max_vblank_count = 0x00ffffff; + return 0; + } + diff --git a/queue-4.2/drm-amdgpu-fix-overflow-on-32bit-systems.patch b/queue-4.2/drm-amdgpu-fix-overflow-on-32bit-systems.patch new file mode 100644 index 00000000000..91be2f9d1e5 --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-overflow-on-32bit-systems.patch @@ -0,0 +1,33 @@ +From b7d698d7fd7d132c6ebe56d230584f2cae6c94ee Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 7 Sep 2015 12:32:09 +0200 +Subject: drm/amdgpu: fix overflow on 32bit systems +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Christian=20K=C3=B6nig?= + +commit b7d698d7fd7d132c6ebe56d230584f2cae6c94ee upstream. + +mem->start is a long, so this can overflow on 32bit systems. + +Signed-off-by: Christian König +Reviewed-by: Jammy Zhou +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -787,7 +787,7 @@ int amdgpu_vm_bo_update(struct amdgpu_de + int r; + + if (mem) { +- addr = mem->start << PAGE_SHIFT; ++ addr = (u64)mem->start << PAGE_SHIFT; + if (mem->mem_type != TTM_PL_TT) + addr += adev->vm_manager.vram_base_offset; + } else { diff --git a/queue-4.2/drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch b/queue-4.2/drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch new file mode 100644 index 00000000000..96fc8a3643c --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch @@ -0,0 +1,72 @@ +From 2bd188d0167227932be3cf5b033c0e600b01291f Mon Sep 17 00:00:00 2001 +From: Leo Liu +Date: Fri, 11 Sep 2015 14:22:18 -0400 +Subject: drm/amdgpu: fix the UVD suspend sequence order +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Leo Liu + +commit 2bd188d0167227932be3cf5b033c0e600b01291f upstream. + +Fixes suspend issues with UVD. + +Signed-off-by: Leo Liu +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- + 3 files changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +@@ -224,11 +224,11 @@ static int uvd_v4_2_suspend(void *handle + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- r = uvd_v4_2_hw_fini(adev); ++ r = amdgpu_uvd_suspend(adev); + if (r) + return r; + +- r = amdgpu_uvd_suspend(adev); ++ r = uvd_v4_2_hw_fini(adev); + if (r) + return r; + +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -220,11 +220,11 @@ static int uvd_v5_0_suspend(void *handle + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- r = uvd_v5_0_hw_fini(adev); ++ r = amdgpu_uvd_suspend(adev); + if (r) + return r; + +- r = amdgpu_uvd_suspend(adev); ++ r = uvd_v5_0_hw_fini(adev); + if (r) + return r; + +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -214,11 +214,11 @@ static int uvd_v6_0_suspend(void *handle + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- r = uvd_v6_0_hw_fini(adev); ++ r = amdgpu_uvd_suspend(adev); + if (r) + return r; + +- r = amdgpu_uvd_suspend(adev); ++ r = uvd_v6_0_hw_fini(adev); + if (r) + return r; + diff --git a/queue-4.2/drm-amdgpu-make-uvd-handle-checking-more-strict.patch b/queue-4.2/drm-amdgpu-make-uvd-handle-checking-more-strict.patch new file mode 100644 index 00000000000..00ffaaf6b2c --- /dev/null +++ b/queue-4.2/drm-amdgpu-make-uvd-handle-checking-more-strict.patch @@ -0,0 +1,114 @@ +From 5146419e6feb99cfbc8dbf005dd2f62603e15efb Mon Sep 17 00:00:00 2001 +From: Leo Liu +Date: Tue, 15 Sep 2015 10:38:38 -0400 +Subject: drm/amdgpu: make UVD handle checking more strict +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Leo Liu + +commit 5146419e6feb99cfbc8dbf005dd2f62603e15efb upstream. + +Invalid messages can crash the hw otherwise + +Ported from radeon commit a1b403da70e038ca6c6c6fe434d1d873546873a3 + +Signed-off-by: Leo Liu +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 68 +++++++++++++++++++------------- + 1 file changed, 41 insertions(+), 27 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -543,46 +543,60 @@ static int amdgpu_uvd_cs_msg(struct amdg + return -EINVAL; + } + +- if (msg_type == 1) { ++ switch (msg_type) { ++ case 0: ++ /* it's a create msg, calc image size (width * height) */ ++ amdgpu_bo_kunmap(bo); ++ ++ /* try to alloc a new handle */ ++ for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { ++ if (atomic_read(&adev->uvd.handles[i]) == handle) { ++ DRM_ERROR("Handle 0x%x already in use!\n", handle); ++ return -EINVAL; ++ } ++ ++ if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { ++ adev->uvd.filp[i] = ctx->parser->filp; ++ return 0; ++ } ++ } ++ ++ DRM_ERROR("No more free UVD handles!\n"); ++ return -EINVAL; ++ ++ case 1: + /* it's a decode msg, calc buffer sizes */ + r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); + amdgpu_bo_kunmap(bo); + if (r) + return r; + +- } else if (msg_type == 2) { ++ /* validate the handle */ ++ for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { ++ if (atomic_read(&adev->uvd.handles[i]) == handle) { ++ if (adev->uvd.filp[i] != ctx->parser->filp) { ++ DRM_ERROR("UVD handle collision detected!\n"); ++ return -EINVAL; ++ } ++ return 0; ++ } ++ } ++ ++ DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); ++ return -ENOENT; ++ ++ case 2: + /* it's a destroy msg, free the handle */ + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); + amdgpu_bo_kunmap(bo); + return 0; +- } else { +- /* it's a create msg */ +- amdgpu_bo_kunmap(bo); + +- if (msg_type != 0) { +- DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); +- return -EINVAL; +- } +- +- /* it's a create msg, no special handling needed */ +- } +- +- /* create or decode, validate the handle */ +- for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { +- if (atomic_read(&adev->uvd.handles[i]) == handle) +- return 0; +- } +- +- /* handle not found try to alloc a new one */ +- for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { +- if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { +- adev->uvd.filp[i] = ctx->parser->filp; +- return 0; +- } ++ default: ++ DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); ++ return -EINVAL; + } +- +- DRM_ERROR("No more free UVD handles!\n"); ++ BUG(); + return -EINVAL; + } + diff --git a/queue-4.2/drm-amdgpu-restore-lcd-backlight-level-on-resume.patch b/queue-4.2/drm-amdgpu-restore-lcd-backlight-level-on-resume.patch new file mode 100644 index 00000000000..2ace5475a4f --- /dev/null +++ b/queue-4.2/drm-amdgpu-restore-lcd-backlight-level-on-resume.patch @@ -0,0 +1,35 @@ +From 74b3112e95073b351e3b0b9799795bc76f8415fa Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 29 Sep 2015 13:53:30 -0400 +Subject: drm/amdgpu: Restore LCD backlight level on resume + +From: Alex Deucher + +commit 74b3112e95073b351e3b0b9799795bc76f8415fa upstream. + +Instead of only enabling the backlight (which seems to set it to max +brightness), just re-set the current backlight level, which also takes +care of enabling the backlight if necessary. + +Port of radeon commit: +drm/radeon: Restore LCD backlight level on resume (>= R5xx) + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c ++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +@@ -1279,8 +1279,7 @@ amdgpu_atombios_encoder_setup_dig(struct + amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); + } + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) +- amdgpu_atombios_encoder_setup_dig_transmitter(encoder, +- ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); ++ amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder, dig->backlight_level); + if (ext_encoder) + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE); + } else { diff --git a/queue-4.2/drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch b/queue-4.2/drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch new file mode 100644 index 00000000000..269e5ddd6bf --- /dev/null +++ b/queue-4.2/drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch @@ -0,0 +1,68 @@ +From cd67d226ebd909d239d2c6e5a6abd6e2a338d1cd Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Thu, 17 Sep 2015 16:42:07 +0300 +Subject: drm/i915/bios: handle MIPI Sequence Block v3+ gracefully + +From: Jani Nikula + +commit cd67d226ebd909d239d2c6e5a6abd6e2a338d1cd upstream. + +The VBT MIPI Sequence Block version 3 has forward incompatible changes: + +First, the block size in the header has been specified reserved, and the +actual size is a separate 32-bit value within the block. The current +find_section() function to will only look at the size in the block +header, and, depending on what's in that now reserved size field, +continue looking for other sections in the wrong place. + +Fix this by taking the new block size field into account. This will +ensure that the lookups for other sections will work properly, as long +as the new 32-bit size does not go beyond the opregion VBT mailbox size. + +Second, the contents of the block have been completely +changed. Gracefully refuse parsing the yet unknown data version. + +Cc: Deepak M +Reviewed-by: Deepak M +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_bios.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_bios.c ++++ b/drivers/gpu/drm/i915/intel_bios.c +@@ -42,7 +42,7 @@ find_section(const void *_bdb, int secti + const struct bdb_header *bdb = _bdb; + const u8 *base = _bdb; + int index = 0; +- u16 total, current_size; ++ u32 total, current_size; + u8 current_id; + + /* skip to first section */ +@@ -57,6 +57,10 @@ find_section(const void *_bdb, int secti + current_size = *((const u16 *)(base + index)); + index += 2; + ++ /* The MIPI Sequence Block v3+ has a separate size field. */ ++ if (current_id == BDB_MIPI_SEQUENCE && *(base + index) >= 3) ++ current_size = *((const u32 *)(base + index + 1)); ++ + if (index + current_size > total) + return NULL; + +@@ -859,6 +863,12 @@ parse_mipi(struct drm_i915_private *dev_ + return; + } + ++ /* Fail gracefully for forward incompatible sequence block. */ ++ if (sequence->version >= 3) { ++ DRM_ERROR("Unable to parse MIPI Sequence Block v3+\n"); ++ return; ++ } ++ + DRM_DEBUG_DRIVER("Found MIPI sequence block\n"); + + block_size = get_blocksize(sequence); diff --git a/queue-4.2/drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch b/queue-4.2/drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch new file mode 100644 index 00000000000..3b8179ff8f9 --- /dev/null +++ b/queue-4.2/drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch @@ -0,0 +1,42 @@ +From 69e5d3f893e19613486f300fd6e631810338aa4b Mon Sep 17 00:00:00 2001 +From: Dave Airlie +Date: Mon, 14 Sep 2015 10:28:34 +1000 +Subject: drm/qxl: only report first monitor as connected if we have no state + +From: Dave Airlie + +commit 69e5d3f893e19613486f300fd6e631810338aa4b upstream. + +If the server isn't new enough to give us state, report the first +monitor as always connected, otherwise believe the server side. + +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/qxl/qxl_display.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/qxl/qxl_display.c ++++ b/drivers/gpu/drm/qxl/qxl_display.c +@@ -886,13 +886,15 @@ static enum drm_connector_status qxl_con + drm_connector_to_qxl_output(connector); + struct drm_device *ddev = connector->dev; + struct qxl_device *qdev = ddev->dev_private; +- int connected; ++ bool connected = false; + + /* The first monitor is always connected */ +- connected = (output->index == 0) || +- (qdev->client_monitors_config && +- qdev->client_monitors_config->count > output->index && +- qxl_head_enabled(&qdev->client_monitors_config->heads[output->index])); ++ if (!qdev->client_monitors_config) { ++ if (output->index == 0) ++ connected = true; ++ } else ++ connected = qdev->client_monitors_config->count > output->index && ++ qxl_head_enabled(&qdev->client_monitors_config->heads[output->index]); + + DRM_DEBUG("#%d connected: %d\n", output->index, connected); + if (!connected) diff --git a/queue-4.2/drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch b/queue-4.2/drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch new file mode 100644 index 00000000000..d4b6cd23168 --- /dev/null +++ b/queue-4.2/drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch @@ -0,0 +1,36 @@ +From 8d0d94015e96b8853c4f7f06eac3f269e1b3d866 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Fabiano=20Fid=C3=AAncio?= +Date: Thu, 24 Sep 2015 15:18:34 +0200 +Subject: drm/qxl: recreate the primary surface when the bo is not primary +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Fabiano=20Fid=C3=AAncio?= + +commit 8d0d94015e96b8853c4f7f06eac3f269e1b3d866 upstream. + +When disabling/enabling a crtc the primary area must be updated +independently of which crtc has been disabled/enabled. + +Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1264735 + +Signed-off-by: Fabiano Fidêncio +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/qxl/qxl_display.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/qxl/qxl_display.c ++++ b/drivers/gpu/drm/qxl/qxl_display.c +@@ -618,7 +618,7 @@ static int qxl_crtc_mode_set(struct drm_ + adjusted_mode->hdisplay, + adjusted_mode->vdisplay); + +- if (qcrtc->index == 0) ++ if (bo->is_primary == false) + recreate_primary = true; + + if (bo->surf.stride * bo->surf.height > qdev->vram_size) { diff --git a/queue-4.2/drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch b/queue-4.2/drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch new file mode 100644 index 00000000000..62ea0348e55 --- /dev/null +++ b/queue-4.2/drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch @@ -0,0 +1,49 @@ +From da168d81b44898404d281d5dbe70154ab5f117c1 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Tue, 23 Jun 2015 11:34:21 +0200 +Subject: drm: Reject DRI1 hw lock ioctl functions for kms drivers + +From: Daniel Vetter + +commit da168d81b44898404d281d5dbe70154ab5f117c1 upstream. + +I've done some extensive history digging across libdrm, mesa and +xf86-video-{intel,nouveau,ati}. The only potential user of this with +kms drivers I could find was ttmtest, which once used drmGetLock +still. But that mistake was quickly fixed up. Even the intel xvmc +library (which otherwise was really good with using dri1 stuff in kms +mode) managed to never take the hw lock for dri2 (and hence kms). + +Hence it should be save to unconditionally disallow this. + +Cc: Peter Antoine +Reviewed-by: Peter Antoine +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_lock.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/gpu/drm/drm_lock.c ++++ b/drivers/gpu/drm/drm_lock.c +@@ -61,6 +61,9 @@ int drm_legacy_lock(struct drm_device *d + struct drm_master *master = file_priv->master; + int ret = 0; + ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) ++ return -EINVAL; ++ + ++file_priv->lock_count; + + if (lock->context == DRM_KERNEL_CONTEXT) { +@@ -153,6 +156,9 @@ int drm_legacy_unlock(struct drm_device + struct drm_lock *lock = data; + struct drm_master *master = file_priv->master; + ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) ++ return -EINVAL; ++ + if (lock->context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + task_pid_nr(current), lock->context); diff --git a/queue-4.2/series b/queue-4.2/series index cb6ae812573..a7f6ffb50f2 100644 --- a/queue-4.2/series +++ b/queue-4.2/series @@ -137,3 +137,13 @@ nfs-fix-a-write-performance-regression.patch fix-sec-krb5-on-smb3-mounts.patch disabling-oplocks-leases-via-module-parm-enable_oplocks-broken-for-smb3.patch do-not-fall-back-to-smbwritex-in-set_file_size-error-cases.patch +drm-qxl-only-report-first-monitor-as-connected-if-we-have-no-state.patch +drm-qxl-recreate-the-primary-surface-when-the-bo-is-not-primary.patch +drm-amdgpu-fix-overflow-on-32bit-systems.patch +drm-amdgpu-disable-uvd-pg.patch +drm-amdgpu-fix-the-uvd-suspend-sequence-order.patch +drm-amdgpu-make-uvd-handle-checking-more-strict.patch +drm-amdgpu-fix-max_vblank_count-value-for-current-display-engines.patch +drm-amdgpu-restore-lcd-backlight-level-on-resume.patch +drm-i915-bios-handle-mipi-sequence-block-v3-gracefully.patch +drm-reject-dri1-hw-lock-ioctl-functions-for-kms-drivers.patch -- 2.47.3