From f18e96e6188242a4e1a4b0320aad5de8ca6d15fa Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Mon, 6 Feb 2023 21:02:48 +0800 Subject: [PATCH] RISC-V: Add vmulh.vx C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vmulh_vx_mu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_mu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_mu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_mu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_mu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_mu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_rv32-1.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulh_vx_rv32-2.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulh_vx_rv32-3.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulh_vx_rv64-1.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulh_vx_rv64-2.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulh_vx_rv64-3.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tum_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulh_vx_tumu_rv64-3.C | 160 +++++++++ 30 files changed, 5670 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C new file mode 100644 index 000000000000..e94f1cbbcc17 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C new file mode 100644 index 000000000000..0300a1d61910 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C new file mode 100644 index 000000000000..e2a44005965c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C new file mode 100644 index 000000000000..3d940fa7b6e0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C new file mode 100644 index 000000000000..cd8cb1bb6688 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C new file mode 100644 index 000000000000..0c0f2ceed79b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C new file mode 100644 index 000000000000..540d8b1db6ed --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C new file mode 100644 index 000000000000..c9dbfd198a11 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C new file mode 100644 index 000000000000..e0df51d35a68 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C new file mode 100644 index 000000000000..6523c5b05f56 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C new file mode 100644 index 000000000000..b5a2cd9b5cca --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C new file mode 100644 index 000000000000..3e43c77e1c2b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulh(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C new file mode 100644 index 000000000000..e4afe24171dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C new file mode 100644 index 000000000000..aedf4799960d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C new file mode 100644 index 000000000000..8d4f63e775f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C new file mode 100644 index 000000000000..ff99eeb9157d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C new file mode 100644 index 000000000000..151193bbd979 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C new file mode 100644 index 000000000000..76887462d234 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C new file mode 100644 index 000000000000..64a52d6aab10 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C new file mode 100644 index 000000000000..c19da170581a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C new file mode 100644 index 000000000000..2c56f5f0603d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C new file mode 100644 index 000000000000..b8e1ab74cde9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C new file mode 100644 index 000000000000..aadf38452f8c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C new file mode 100644 index 000000000000..ff6af7e717fb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C new file mode 100644 index 000000000000..e1c1bcfe994b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C new file mode 100644 index 000000000000..bed48a13f0a5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C new file mode 100644 index 000000000000..c5d1c7c10507 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C new file mode 100644 index 000000000000..1c52f44f94c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C new file mode 100644 index 000000000000..29c016a35394 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C new file mode 100644 index 000000000000..0a4e27f6a455 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulh_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulh_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulh_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulh_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulh_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulh_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulh_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulh_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulh_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulh_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulh_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulh_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulh_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulh_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulh_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulh_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulh_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulh_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulh_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulh_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulh_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulh_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vmulh_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.47.2