From f2ae542b327ae72ca2d933a69a1ebbc1a263f636 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 31 Aug 2023 12:39:28 +0200 Subject: [PATCH] 4.19-stable patches added patches: revert-mips-alchemy-fix-dbdma2.patch --- .../revert-mips-alchemy-fix-dbdma2.patch | 81 +++++++++++++++++++ queue-4.19/series | 1 + 2 files changed, 82 insertions(+) create mode 100644 queue-4.19/revert-mips-alchemy-fix-dbdma2.patch diff --git a/queue-4.19/revert-mips-alchemy-fix-dbdma2.patch b/queue-4.19/revert-mips-alchemy-fix-dbdma2.patch new file mode 100644 index 00000000000..9c140c38bcf --- /dev/null +++ b/queue-4.19/revert-mips-alchemy-fix-dbdma2.patch @@ -0,0 +1,81 @@ +From 1a4039bdcf972a7d2e469bb1a5ea616c4c2216fb Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Thu, 31 Aug 2023 12:30:23 +0200 +Subject: Revert "MIPS: Alchemy: fix dbdma2" + +From: Greg Kroah-Hartman + +This reverts commit a16419bae292d768546bcd6e0bfbf8a722756fee which is +commit 2d645604f69f3a772d58ead702f9a8e84ab2b342 upstream. + +It breaks the build, so should be dropped. + +Reported-by: Guenter Roeck +Link: https://lore.kernel.org/r/5b30ff73-46cb-1d1e-3823-f175dbfbd91b@roeck-us.net +Cc: Thomas Bogendoerfer +Cc: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/alchemy/common/dbdma.c | 27 ++++++++++++--------------- + 1 file changed, 12 insertions(+), 15 deletions(-) + +--- a/arch/mips/alchemy/common/dbdma.c ++++ b/arch/mips/alchemy/common/dbdma.c +@@ -30,7 +30,6 @@ + * + */ + +-#include /* for dma_default_coherent */ + #include + #include + #include +@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result ++ * in "stale" data being DMA'ed. It has to do with the snoop logic on ++ * the cache eviction buffer. DMA_NONCOHERENT is on by default for ++ * these parts. If it is fixed in the future, these dma_cache_inv will ++ * just be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_wback_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); +@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dm + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); + #endif + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result in ++ * "stale" data being DMA'ed. It has to do with the snoop logic on the ++ * cache eviction buffer. DMA_NONCOHERENT is on by default for these ++ * parts. If it is fixed in the future, these dma_cache_inv will just ++ * be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); diff --git a/queue-4.19/series b/queue-4.19/series index e69de29bb2d..be0d4f997e2 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -0,0 +1 @@ +revert-mips-alchemy-fix-dbdma2.patch -- 2.47.3