From f58d5545d6b39cb6534dae105931e92ea9389d1f Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 7 Sep 2022 10:52:03 +0100 Subject: [PATCH] aarch64: Prevent FPR register asms for +nofp +nofp disabled the automatic allocation of FPRs, but it didn't stop users from explicitly putting register variables in FPRs. We'd then either report an ICE or generate unsupported instructions. It's still possible (and deliberately redundant) to specify FPRs in clobber lists. gcc/ * config/aarch64/aarch64.cc (aarch64_conditional_register_usage): Disallow use of FPRs in register asms for !TARGET_FLOAT. gcc/testsuite/ * gcc.target/aarch64/nofp_2.c: New test. --- gcc/config/aarch64/aarch64.cc | 1 + gcc/testsuite/gcc.target/aarch64/nofp_2.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/nofp_2.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 566763ce50c4..786ede76131f 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -19847,6 +19847,7 @@ aarch64_conditional_register_usage (void) { fixed_regs[i] = 1; call_used_regs[i] = 1; + CLEAR_HARD_REG_BIT (operand_reg_set, i); } } if (!TARGET_SVE) diff --git a/gcc/testsuite/gcc.target/aarch64/nofp_2.c b/gcc/testsuite/gcc.target/aarch64/nofp_2.c new file mode 100644 index 000000000000..8a262cc76fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/nofp_2.c @@ -0,0 +1,19 @@ +/* { dg-options "" } */ + +#pragma GCC target "+nothing+nofp" + +void +test (void) +{ + register int q0 asm ("q0"); // { dg-error "not general enough" } + register int q1 asm ("q1"); // { dg-error "not general enough" } + asm volatile ("" : "=w" (q0)); + q1 = q0; + asm volatile ("" :: "w" (q1)); +} + +void +ok (void) +{ + asm volatile ("" ::: "q0"); +} -- 2.47.2