From fa84b53bc39e3a848d8b4a971dd26790fe426c98 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 5 Jan 2015 12:51:56 -0800 Subject: [PATCH] 3.17-stable patches added patches: arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch arm64-add-compat_hwcap_lpae.patch drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch --- ...-situations-on-armada-370-375-38x-xp.patch | 116 ++++++++++++++++++ ...ebu-fix-ordering-in-armada-370-.dtsi.patch | 52 ++++++++ ...ctions-work-with-no-coherency-fabric.patch | 97 +++++++++++++++ ...removed-soc-id-macro-to-tegra_resume.patch | 37 ++++++ queue-3.17/arm64-add-compat_hwcap_lpae.patch | 45 +++++++ ...-gem-dumb-pitch-and-size-are-outputs.patch | 47 +++++++ queue-3.17/series | 7 ++ ...obes-in-fixup_bad_iret-and-sync_regs.patch | 52 ++++++++ 8 files changed, 453 insertions(+) create mode 100644 queue-3.17/arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch create mode 100644 queue-3.17/arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch create mode 100644 queue-3.17/arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch create mode 100644 queue-3.17/arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch create mode 100644 queue-3.17/arm64-add-compat_hwcap_lpae.patch create mode 100644 queue-3.17/drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch create mode 100644 queue-3.17/x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch diff --git a/queue-3.17/arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch b/queue-3.17/arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch new file mode 100644 index 00000000000..652f2dbcfe8 --- /dev/null +++ b/queue-3.17/arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch @@ -0,0 +1,116 @@ +From e55355453600a33bb5ca4f71f2d7214875f3b061 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Thu, 13 Nov 2014 10:38:57 +0100 +Subject: ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP + +From: Thomas Petazzoni + +commit e55355453600a33bb5ca4f71f2d7214875f3b061 upstream. + +Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada +38x and Armada XP requires a certain number of conditions: + + - On Armada 370, the cache policy must be set to write-allocate. + + - On Armada 375, 38x and XP, the cache policy must be set to + write-allocate, the pages must be mapped with the shareable + attribute, and the SMP bit must be set + +Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions +are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none +of these conditions are met. With Armada 370, the situation is worse: +since the processor is single core, regardless of whether CONFIG_SMP +or !CONFIG_SMP is used, the cache policy will be set to write-back by +the kernel and not write-allocate. + +Since solving this problem turns out to be quite complicated, and we +don't want to let users with a mainline kernel known to have +infrequent but existing data corruptions, this commit proposes to +simply disable hardware I/O coherency in situations where it is known +not to work. + +And basically, the is_smp() function of the kernel tells us whether it +is OK to enable hardware I/O coherency or not, so this commit slightly +refactors the coherency_type() function to return +COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate +type of the coherency fabric in the other case. + +Thanks to this, the I/O coherency fabric will no longer be used at all +in !CONFIG_SMP configurations. It will continue to be used in +CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x +(which are multiple cores processors), but will no longer be used on +Armada 370 (which is a single core processor). + +In the process, it simplifies the implementation of the +coherency_type() function, and adds a missing call to of_node_put(). + +Signed-off-by: Thomas Petazzoni +Fixes: e60304f8cb7bb545e79fe62d9b9762460c254ec2 ("arm: mvebu: Add hardware I/O Coherency support") +Acked-by: Gregory CLEMENT +Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com +Signed-off-by: Jason Cooper +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-mvebu/coherency.c | 46 ++++++++++++++++++++++++++-------------- + 1 file changed, 31 insertions(+), 15 deletions(-) + +--- a/arch/arm/mach-mvebu/coherency.c ++++ b/arch/arm/mach-mvebu/coherency.c +@@ -361,25 +361,41 @@ static int coherency_type(void) + { + struct device_node *np; + const struct of_device_id *match; ++ int type; ++ ++ /* ++ * The coherency fabric is needed: ++ * - For coherency between processors on Armada XP, so only ++ * when SMP is enabled. ++ * - For coherency between the processor and I/O devices, but ++ * this coherency requires many pre-requisites (write ++ * allocate cache policy, shareable pages, SMP bit set) that ++ * are only meant in SMP situations. ++ * ++ * Note that this means that on Armada 370, there is currently ++ * no way to use hardware I/O coherency, because even when ++ * CONFIG_SMP is enabled, is_smp() returns false due to the ++ * Armada 370 being a single-core processor. To lift this ++ * limitation, we would have to find a way to make the cache ++ * policy set to write-allocate (on all Armada SoCs), and to ++ * set the shareable attribute in page tables (on all Armada ++ * SoCs except the Armada 370). Unfortunately, such decisions ++ * are taken very early in the kernel boot process, at a point ++ * where we don't know yet on which SoC we are running. ++ ++ */ ++ if (!is_smp()) ++ return COHERENCY_FABRIC_TYPE_NONE; + + np = of_find_matching_node_and_match(NULL, of_coherency_table, &match); +- if (np) { +- int type = (int) match->data; ++ if (!np) ++ return COHERENCY_FABRIC_TYPE_NONE; ++ ++ type = (int) match->data; + +- /* Armada 370/XP coherency works in both UP and SMP */ +- if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) +- return type; +- +- /* Armada 375 coherency works only on SMP */ +- else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp()) +- return type; +- +- /* Armada 380 coherency works only on SMP */ +- else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp()) +- return type; +- } ++ of_node_put(np); + +- return COHERENCY_FABRIC_TYPE_NONE; ++ return type; + } + + int coherency_available(void) diff --git a/queue-3.17/arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch b/queue-3.17/arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch new file mode 100644 index 00000000000..b098481d3e3 --- /dev/null +++ b/queue-3.17/arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch @@ -0,0 +1,52 @@ +From ab1e85372168892387dd1ac171158fc8c3119be4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Fri, 14 Nov 2014 21:43:33 +0100 +Subject: ARM: mvebu: fix ordering in Armada 370 .dtsi +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= + +commit ab1e85372168892387dd1ac171158fc8c3119be4 upstream. + +Commit a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") +missed placing the system-controller in the correct order. + +Fixes: a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") +Signed-off-by: Uwe Kleine-König +Acked-by: Andrew Lunn +Link: https://lkml.kernel.org/r/20141114204333.GS27002@pengutronix.de +Signed-off-by: Jason Cooper +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/armada-370.dtsi | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -106,11 +106,6 @@ + reg = <0x11100 0x20>; + }; + +- system-controller@18200 { +- compatible = "marvell,armada-370-xp-system-controller"; +- reg = <0x18200 0x100>; +- }; +- + pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + reg = <0x18000 0x38>; +@@ -186,6 +181,11 @@ + interrupts = <91>; + }; + ++ system-controller@18200 { ++ compatible = "marvell,armada-370-xp-system-controller"; ++ reg = <0x18200 0x100>; ++ }; ++ + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0x18220 0x4>; diff --git a/queue-3.17/arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch b/queue-3.17/arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch new file mode 100644 index 00000000000..8531f7454a8 --- /dev/null +++ b/queue-3.17/arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch @@ -0,0 +1,97 @@ +From 30cdef97107370a7f63ab5d80fd2de30540750c8 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Thu, 13 Nov 2014 10:38:56 +0100 +Subject: ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric + +From: Thomas Petazzoni + +commit 30cdef97107370a7f63ab5d80fd2de30540750c8 upstream. + +The ll_add_cpu_to_smp_group(), ll_enable_coherency() and +ll_disable_coherency() are used on Armada XP to control the coherency +fabric. However, they make the assumption that the coherency fabric is +always available, which is currently a correct assumption but will no +longer be true with a followup commit that disables the usage of the +coherency fabric when the conditions are not met to use it. + +Therefore, this commit modifies those functions so that they check the +return value of ll_get_coherency_base(), and if the return value is 0, +they simply return without configuring anything in the coherency +fabric. + +The ll_get_coherency_base() function is also modified to properly +return 0 when the function is called with the MMU disabled. In this +case, it normally returns the physical address of the coherency +fabric, but we now check if the virtual address is 0, and if that's +case, return a physical address of 0 to indicate that the coherency +fabric is not enabled. + +Signed-off-by: Thomas Petazzoni +Acked-by: Gregory CLEMENT +Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com +Signed-off-by: Jason Cooper +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-mvebu/coherency_ll.S | 21 +++++++++++++++++++-- + 1 file changed, 19 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-mvebu/coherency_ll.S ++++ b/arch/arm/mach-mvebu/coherency_ll.S +@@ -24,7 +24,10 @@ + #include + + .text +-/* Returns the coherency base address in r1 (r0 is untouched) */ ++/* ++ * Returns the coherency base address in r1 (r0 is untouched), or 0 if ++ * the coherency fabric is not enabled. ++ */ + ENTRY(ll_get_coherency_base) + mrc p15, 0, r1, c1, c0, 0 + tst r1, #CR_M @ Check MMU bit enabled +@@ -32,8 +35,13 @@ ENTRY(ll_get_coherency_base) + + /* + * MMU is disabled, use the physical address of the coherency +- * base address. ++ * base address. However, if the coherency fabric isn't mapped ++ * (i.e its virtual address is zero), it means coherency is ++ * not enabled, so we return 0. + */ ++ ldr r1, =coherency_base ++ cmp r1, #0 ++ beq 2f + adr r1, 3f + ldr r3, [r1] + ldr r1, [r1, r3] +@@ -85,6 +93,9 @@ ENTRY(ll_add_cpu_to_smp_group) + */ + mov r0, lr + bl ll_get_coherency_base ++ /* Bail out if the coherency is not enabled */ ++ cmp r1, #0 ++ reteq r0 + bl ll_get_coherency_cpumask + mov lr, r0 + add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET +@@ -107,6 +118,9 @@ ENTRY(ll_enable_coherency) + */ + mov r0, lr + bl ll_get_coherency_base ++ /* Bail out if the coherency is not enabled */ ++ cmp r1, #0 ++ reteq r0 + bl ll_get_coherency_cpumask + mov lr, r0 + add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET +@@ -131,6 +145,9 @@ ENTRY(ll_disable_coherency) + */ + mov r0, lr + bl ll_get_coherency_base ++ /* Bail out if the coherency is not enabled */ ++ cmp r1, #0 ++ reteq r0 + bl ll_get_coherency_cpumask + mov lr, r0 + add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET diff --git a/queue-3.17/arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch b/queue-3.17/arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch new file mode 100644 index 00000000000..5e72590def8 --- /dev/null +++ b/queue-3.17/arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch @@ -0,0 +1,37 @@ +From e4a680099a6e97ecdbb81081cff9e4a489a4dc44 Mon Sep 17 00:00:00 2001 +From: Dmitry Osipenko +Date: Fri, 10 Oct 2014 17:24:47 +0400 +Subject: ARM: tegra: Re-add removed SoC id macro to tegra_resume() + +From: Dmitry Osipenko + +commit e4a680099a6e97ecdbb81081cff9e4a489a4dc44 upstream. + +Commit d127e9c ("ARM: tegra: make tegra_resume can work with current and later +chips") removed tegra_get_soc_id macro leaving used cpu register corrupted after +branching to v7_invalidate_l1() and as result causing execution of unintended +code on tegra20. Possibly it was expected that r6 would be SoC id func argument +since common cpu reset handler is setting r6 before branching to tegra_resume(), +but neither tegra20_lp1_reset() nor tegra30_lp1_reset() aren't setting r6 +register before jumping to resume function. Fix it by re-adding macro. + +Fixes: d127e9c (ARM: tegra: make tegra_resume can work with current and later chips) +Reviewed-by: Felipe Balbi +Signed-off-by: Dmitry Osipenko +Signed-off-by: Thierry Reding +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-tegra/reset-handler.S | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-tegra/reset-handler.S ++++ b/arch/arm/mach-tegra/reset-handler.S +@@ -51,6 +51,7 @@ ENTRY(tegra_resume) + THUMB( it ne ) + bne cpu_resume @ no + ++ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + /* Are we on Tegra20? */ + cmp r6, #TEGRA20 + beq 1f @ Yes diff --git a/queue-3.17/arm64-add-compat_hwcap_lpae.patch b/queue-3.17/arm64-add-compat_hwcap_lpae.patch new file mode 100644 index 00000000000..ec8333ea5ed --- /dev/null +++ b/queue-3.17/arm64-add-compat_hwcap_lpae.patch @@ -0,0 +1,45 @@ +From 7d57511d2dba03a8046c8b428dd9192a4bfc1e73 Mon Sep 17 00:00:00 2001 +From: Catalin Marinas +Date: Mon, 17 Nov 2014 10:37:40 +0000 +Subject: arm64: Add COMPAT_HWCAP_LPAE + +From: Catalin Marinas + +commit 7d57511d2dba03a8046c8b428dd9192a4bfc1e73 upstream. + +Commit a469abd0f868 (ARM: elf: add new hwcap for identifying atomic +ldrd/strd instructions) introduces HWCAP_ELF for 32-bit ARM +applications. As LPAE is always present on arm64, report the +corresponding compat HWCAP to user space. + +Signed-off-by: Catalin Marinas +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/hwcap.h | 1 + + arch/arm64/kernel/setup.c | 3 ++- + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -30,6 +30,7 @@ + #define COMPAT_HWCAP_IDIVA (1 << 17) + #define COMPAT_HWCAP_IDIVT (1 << 18) + #define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT) ++#define COMPAT_HWCAP_LPAE (1 << 20) + #define COMPAT_HWCAP_EVTSTRM (1 << 21) + + #define COMPAT_HWCAP2_AES (1 << 0) +--- a/arch/arm64/kernel/setup.c ++++ b/arch/arm64/kernel/setup.c +@@ -72,7 +72,8 @@ EXPORT_SYMBOL_GPL(elf_hwcap); + COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ + COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ + COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ +- COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) ++ COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ ++ COMPAT_HWCAP_LPAE) + unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; + unsigned int compat_elf_hwcap2 __read_mostly; + #endif diff --git a/queue-3.17/drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch b/queue-3.17/drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch new file mode 100644 index 00000000000..a889a6cc9ca --- /dev/null +++ b/queue-3.17/drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch @@ -0,0 +1,47 @@ +From dc6057ecb39edb34b0461ca55382094410bd257a Mon Sep 17 00:00:00 2001 +From: Thierry Reding +Date: Thu, 30 Oct 2014 15:32:56 +0100 +Subject: drm/tegra: gem: dumb: pitch and size are outputs + +From: Thierry Reding + +commit dc6057ecb39edb34b0461ca55382094410bd257a upstream. + +When creating a dumb buffer object using the DRM_IOCTL_MODE_CREATE_DUMB +IOCTL, only the width, height, bpp and flags parameters are inputs. The +caller is not guaranteed to zero out or set handle, pitch and size, so +the driver must not treat these values as possible inputs. + +Fixes a bug where running the Weston compositor on Tegra DRM would cause +an attempt to allocate a 3 GiB framebuffer to be allocated. + +Fixes: de2ba664c30f ("gpu: host1x: drm: Add memory manager and fb") +Signed-off-by: Thierry Reding +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/tegra/gem.c | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/tegra/gem.c ++++ b/drivers/gpu/drm/tegra/gem.c +@@ -259,16 +259,12 @@ void tegra_bo_free_object(struct drm_gem + int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm, + struct drm_mode_create_dumb *args) + { +- int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); ++ unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); + struct tegra_drm *tegra = drm->dev_private; + struct tegra_bo *bo; + +- min_pitch = round_up(min_pitch, tegra->pitch_align); +- if (args->pitch < min_pitch) +- args->pitch = min_pitch; +- +- if (args->size < args->pitch * args->height) +- args->size = args->pitch * args->height; ++ args->pitch = round_up(min_pitch, tegra->pitch_align); ++ args->size = args->pitch * args->height; + + bo = tegra_bo_create_with_handle(file, drm, args->size, 0, + &args->handle); diff --git a/queue-3.17/series b/queue-3.17/series index 39b439634b3..b11c9ba7878 100644 --- a/queue-3.17/series +++ b/queue-3.17/series @@ -26,3 +26,10 @@ dm-thin-fix-inability-to-discard-blocks-when-in-out-of-data-space-mode.patch dm-thin-fix-missing-out-of-data-space-to-write-mode-transition-if-blocks-are-released.patch dm-thin-fix-a-race-in-thin_dtr.patch brcmfmac-fix-bitmap-malloc-bug-in-msgbuf.patch +arm64-add-compat_hwcap_lpae.patch +drm-tegra-gem-dumb-pitch-and-size-are-outputs.patch +arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch +arm-mvebu-make-the-coherency_ll.s-functions-work-with-no-coherency-fabric.patch +arm-mvebu-disable-i-o-coherency-on-non-smp-situations-on-armada-370-375-38x-xp.patch +arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch +x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch diff --git a/queue-3.17/x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch b/queue-3.17/x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch new file mode 100644 index 00000000000..82e24c1fae6 --- /dev/null +++ b/queue-3.17/x86-asm-traps-disable-tracing-and-kprobes-in-fixup_bad_iret-and-sync_regs.patch @@ -0,0 +1,52 @@ +From 7ddc6a2199f1da405a2fb68c40db8899b1a8cd87 Mon Sep 17 00:00:00 2001 +From: Andy Lutomirski +Date: Mon, 24 Nov 2014 17:39:06 -0800 +Subject: x86/asm/traps: Disable tracing and kprobes in fixup_bad_iret and sync_regs + +From: Andy Lutomirski + +commit 7ddc6a2199f1da405a2fb68c40db8899b1a8cd87 upstream. + +These functions can be executed on the int3 stack, so kprobes +are dangerous. Tracing is probably a bad idea, too. + +Fixes: b645af2d5905 ("x86_64, traps: Rework bad_iret") +Signed-off-by: Andy Lutomirski +Cc: Linus Torvalds +Cc: Steven Rostedt +Link: http://lkml.kernel.org/r/50e33d26adca60816f3ba968875801652507d0c4.1416870125.git.luto@amacapital.net +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/traps.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/traps.c ++++ b/arch/x86/kernel/traps.c +@@ -387,7 +387,7 @@ NOKPROBE_SYMBOL(do_int3); + * for scheduling or signal handling. The actual stack switch is done in + * entry.S + */ +-asmlinkage __visible struct pt_regs *sync_regs(struct pt_regs *eregs) ++asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) + { + struct pt_regs *regs = eregs; + /* Did already sync */ +@@ -413,7 +413,7 @@ struct bad_iret_stack { + struct pt_regs regs; + }; + +-asmlinkage __visible ++asmlinkage __visible notrace + struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) + { + /* +@@ -436,6 +436,7 @@ struct bad_iret_stack *fixup_bad_iret(st + BUG_ON(!user_mode_vm(&new_stack->regs)); + return new_stack; + } ++NOKPROBE_SYMBOL(fixup_bad_iret); + #endif + + /* -- 2.47.3