From fb36a5ee8fd0f6a967004846bc00d4555a80ba5d Mon Sep 17 00:00:00 2001 From: nobody <> Date: Thu, 15 Jun 2006 11:03:03 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create branch 'binutils-csl- 2_17-branch'. Cherrypick from master 2006-06-15 11:03:02 UTC Mark Shinwell ' * include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}': gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s gas/testsuite/gas/arm/group-reloc-alu.d gas/testsuite/gas/arm/group-reloc-alu.s gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s gas/testsuite/gas/arm/group-reloc-ldc.d gas/testsuite/gas/arm/group-reloc-ldc.s gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s gas/testsuite/gas/arm/group-reloc-ldr.d gas/testsuite/gas/arm/group-reloc-ldr.s gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s gas/testsuite/gas/arm/group-reloc-ldrs.d gas/testsuite/gas/arm/group-reloc-ldrs.s gas/testsuite/gas/mips/vxworks1-el.d gas/testsuite/gas/mips/vxworks1-xgot-el.d gas/testsuite/gas/mips/vxworks1-xgot.d gas/testsuite/gas/mips/vxworks1.d ld/emulparams/elf32bfinfd.sh ld/testsuite/ld-arm/group-relocs-alu-bad.d ld/testsuite/ld-arm/group-relocs-alu-bad.s ld/testsuite/ld-arm/group-relocs-ldc-bad.d ld/testsuite/ld-arm/group-relocs-ldc-bad.s ld/testsuite/ld-arm/group-relocs-ldr-bad.d ld/testsuite/ld-arm/group-relocs-ldr-bad.s ld/testsuite/ld-arm/group-relocs-ldrs-bad.d ld/testsuite/ld-arm/group-relocs-ldrs-bad.s ld/testsuite/ld-arm/group-relocs.d ld/testsuite/ld-arm/group-relocs.s ld/testsuite/ld-elf/eh1.s ld/testsuite/ld-elf/eh1a.s ld/testsuite/ld-elf/eh2a.s ld/testsuite/ld-elf/eh3.s ld/testsuite/ld-elf/eh3a.s ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d ld/testsuite/ld-mips-elf/stub-dynsym-1.ld ld/testsuite/ld-mips-elf/stub-dynsym-1.s --- .../gas/arm/group-reloc-alu-encoding-bad.d | 2 + .../gas/arm/group-reloc-alu-encoding-bad.l | 81 ++ .../gas/arm/group-reloc-alu-encoding-bad.s | 35 + .../gas/arm/group-reloc-alu-parsing-bad.d | 2 + .../gas/arm/group-reloc-alu-parsing-bad.l | 5 + .../gas/arm/group-reloc-alu-parsing-bad.s | 12 + gas/testsuite/gas/arm/group-reloc-alu.d | 167 ++++ gas/testsuite/gas/arm/group-reloc-alu.s | 39 + .../gas/arm/group-reloc-ldc-encoding-bad.d | 2 + .../gas/arm/group-reloc-ldc-encoding-bad.l | 721 +++++++++++++++++ .../gas/arm/group-reloc-ldc-encoding-bad.s | 169 ++++ .../gas/arm/group-reloc-ldc-parsing-bad.d | 2 + .../gas/arm/group-reloc-ldc-parsing-bad.l | 147 ++++ .../gas/arm/group-reloc-ldc-parsing-bad.s | 67 ++ gas/testsuite/gas/arm/group-reloc-ldc.d | 726 ++++++++++++++++++ gas/testsuite/gas/arm/group-reloc-ldc.s | 151 ++++ .../gas/arm/group-reloc-ldr-encoding-bad.d | 2 + .../gas/arm/group-reloc-ldr-encoding-bad.l | 97 +++ .../gas/arm/group-reloc-ldr-encoding-bad.s | 39 + .../gas/arm/group-reloc-ldr-parsing-bad.d | 2 + .../gas/arm/group-reloc-ldr-parsing-bad.l | 21 + .../gas/arm/group-reloc-ldr-parsing-bad.s | 33 + gas/testsuite/gas/arm/group-reloc-ldr.d | 199 +++++ gas/testsuite/gas/arm/group-reloc-ldr.s | 41 + .../gas/arm/group-reloc-ldrs-encoding-bad.d | 2 + .../gas/arm/group-reloc-ldrs-encoding-bad.l | 121 +++ .../gas/arm/group-reloc-ldrs-encoding-bad.s | 54 ++ .../gas/arm/group-reloc-ldrs-parsing-bad.d | 2 + .../gas/arm/group-reloc-ldrs-parsing-bad.l | 31 + .../gas/arm/group-reloc-ldrs-parsing-bad.s | 44 ++ gas/testsuite/gas/arm/group-reloc-ldrs.d | 247 ++++++ gas/testsuite/gas/arm/group-reloc-ldrs.s | 54 ++ gas/testsuite/gas/mips/vxworks1-el.d | 72 ++ gas/testsuite/gas/mips/vxworks1-xgot-el.d | 102 +++ gas/testsuite/gas/mips/vxworks1-xgot.d | 102 +++ gas/testsuite/gas/mips/vxworks1.d | 71 ++ ld/emulparams/elf32bfinfd.sh | 16 + ld/testsuite/ld-arm/group-relocs-alu-bad.d | 4 + ld/testsuite/ld-arm/group-relocs-alu-bad.s | 20 + ld/testsuite/ld-arm/group-relocs-ldc-bad.d | 4 + ld/testsuite/ld-arm/group-relocs-ldc-bad.s | 19 + ld/testsuite/ld-arm/group-relocs-ldr-bad.d | 4 + ld/testsuite/ld-arm/group-relocs-ldr-bad.s | 18 + ld/testsuite/ld-arm/group-relocs-ldrs-bad.d | 4 + ld/testsuite/ld-arm/group-relocs-ldrs-bad.s | 17 + ld/testsuite/ld-arm/group-relocs.d | 69 ++ ld/testsuite/ld-arm/group-relocs.s | 156 ++++ ld/testsuite/ld-elf/eh1.s | 47 ++ ld/testsuite/ld-elf/eh1a.s | 3 + ld/testsuite/ld-elf/eh2a.s | 3 + ld/testsuite/ld-elf/eh3.s | 48 ++ ld/testsuite/ld-elf/eh3a.s | 3 + .../ld-mips-elf/stub-dynsym-1-10000.d | 18 + .../ld-mips-elf/stub-dynsym-1-2fe80.d | 18 + ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d | 16 + ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d | 16 + ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d | 16 + ld/testsuite/ld-mips-elf/stub-dynsym-1.ld | 17 + ld/testsuite/ld-mips-elf/stub-dynsym-1.s | 10 + 59 files changed, 4210 insertions(+) create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-alu.d create mode 100644 gas/testsuite/gas/arm/group-reloc-alu.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldc.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldr.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs.d create mode 100644 gas/testsuite/gas/arm/group-reloc-ldrs.s create mode 100644 gas/testsuite/gas/mips/vxworks1-el.d create mode 100644 gas/testsuite/gas/mips/vxworks1-xgot-el.d create mode 100644 gas/testsuite/gas/mips/vxworks1-xgot.d create mode 100644 gas/testsuite/gas/mips/vxworks1.d create mode 100644 ld/emulparams/elf32bfinfd.sh create mode 100644 ld/testsuite/ld-arm/group-relocs-alu-bad.d create mode 100644 ld/testsuite/ld-arm/group-relocs-alu-bad.s create mode 100644 ld/testsuite/ld-arm/group-relocs-ldc-bad.d create mode 100644 ld/testsuite/ld-arm/group-relocs-ldc-bad.s create mode 100644 ld/testsuite/ld-arm/group-relocs-ldr-bad.d create mode 100644 ld/testsuite/ld-arm/group-relocs-ldr-bad.s create mode 100644 ld/testsuite/ld-arm/group-relocs-ldrs-bad.d create mode 100644 ld/testsuite/ld-arm/group-relocs-ldrs-bad.s create mode 100644 ld/testsuite/ld-arm/group-relocs.d create mode 100644 ld/testsuite/ld-arm/group-relocs.s create mode 100644 ld/testsuite/ld-elf/eh1.s create mode 100644 ld/testsuite/ld-elf/eh1a.s create mode 100644 ld/testsuite/ld-elf/eh2a.s create mode 100644 ld/testsuite/ld-elf/eh3.s create mode 100644 ld/testsuite/ld-elf/eh3a.s create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1.ld create mode 100644 ld/testsuite/ld-mips-elf/stub-dynsym-1.s diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d new file mode 100644 index 00000000000..148f6028f95 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, encoding failures (alu) +#error-output: group-reloc-alu-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l new file mode 100644 index 00000000000..fe8827cec78 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l @@ -0,0 +1,81 @@ +[^:]*: Assembler messages: +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s new file mode 100644 index 00000000000..bdde4ad4506 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s @@ -0,0 +1,35 @@ +@ Tests that should fail for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym + \offset) + \insn r0, r0, #:pc_g1:(\sym + \offset) + \insn r0, r0, #:pc_g2:(\sym + \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym + \offset) + \insn r0, r0, #:pc_g1_nc:(\sym + \offset) + + \insn r0, r0, #:sb_g0:(\sym + \offset) + \insn r0, r0, #:sb_g1:(\sym + \offset) + \insn r0, r0, #:sb_g2:(\sym + \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym + \offset) + \insn r0, r0, #:sb_g1_nc:(\sym + \offset) + + .endm + + alutest add f 0x11001 + alutest add localsym 0x11001 + alutest adds f 0x11001 + alutest adds localsym 0x11001 + + alutest add f "-0x11001" + alutest add localsym "-0x11001" + alutest adds f "-0x11001" + alutest adds localsym "-0x11001" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d new file mode 100644 index 00000000000..79d50bb87f7 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, parsing failures (alu) +#error-output: group-reloc-alu-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l new file mode 100644 index 00000000000..1c27ad02ffc --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)' +[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)' +[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)' +[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)' diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s new file mode 100644 index 00000000000..70a62acefa6 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s @@ -0,0 +1,12 @@ +@ Tests that should fail for ALU group relocations. + + .text + +@ Group relocs aren't allowed on SUB(S) instructions... + sub r0, r0, #:pc_g0:(foo) + subs r0, r0, #:pc_g0:(foo) + +@ Some nonexistent relocations: + add r0, r0, #:pc_g2_nc:(foo) + add r0, r0, #:sb_g2_nc:(foo) + diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d new file mode 100644 index 00000000000..c616276cafb --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.d @@ -0,0 +1,167 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Group relocation tests (alu) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 10: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 14: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 18: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 1c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 20: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 24: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 28: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 2c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 30: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 34: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 38: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 3c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 40: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 44: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 48: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 50: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 54: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 58: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 5c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 60: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 64: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 68: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 6c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 70: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 74: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 78: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 7c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 80: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 84: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 88: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 8c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 90: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 94: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 98: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 9c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ac: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b0: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b4: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b8: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + bc: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c0: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c4: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c8: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + cc: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d0: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d4: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d8: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + dc: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e0: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e4: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e8: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ec: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + fc: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 100: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 104: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 108: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 10c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 110: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 114: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 118: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 11c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 120: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 124: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 128: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 12c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 130: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 134: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 138: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 13c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-alu.s b/gas/testsuite/gas/arm/group-reloc-alu.s new file mode 100644 index 00000000000..696f1dac0cc --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.s @@ -0,0 +1,39 @@ +@ Tests for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym \offset) + \insn r0, r0, #:pc_g1:(\sym \offset) + +@ Try this one without the hash; it should still work. + \insn r0, r0, :pc_g2:(\sym \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym \offset) + \insn r0, r0, #:pc_g1_nc:(\sym \offset) + + \insn r0, r0, #:sb_g0:(\sym \offset) + \insn r0, r0, #:sb_g1:(\sym \offset) + \insn r0, r0, #:sb_g2:(\sym \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym \offset) + \insn r0, r0, #:sb_g1_nc:(\sym \offset) + + .endm + + alutest add f "+ 0x100" + alutest add localsym "+ 0x100" + alutest adds f "+ 0x100" + alutest adds localsym "+ 0x100" + +@ The following should cause the insns to be switched to SUB(S). + + alutest add f "- 0x100" + alutest add localsym "- 0x100" + alutest adds f "- 0x100" + alutest adds localsym "- 0x100" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d new file mode 100644 index 00000000000..51520b8578c --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, encoding failures (ldc) +#error-output: group-reloc-ldc-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l new file mode 100644 index 00000000000..22e53a5901d --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l @@ -0,0 +1,721 @@ +[^:]*: Assembler messages: +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s new file mode 100644 index 00000000000..5ab27c25fb7 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s @@ -0,0 +1,169 @@ +@ LDC group relocation tests that are supposed to fail during encoding. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store cst + + \load 0, c0, [r0, #:pc_g0:(f + \cst)] + \load 0, c0, [r0, #:pc_g1:(f + \cst)] + \load 0, c0, [r0, #:pc_g2:(f + \cst)] + + \load 0, c0, [r0, #:sb_g0:(f + \cst)] + \load 0, c0, [r0, #:sb_g1:(f + \cst)] + \load 0, c0, [r0, #:sb_g2:(f + \cst)] + + \store 0, c0, [r0, #:pc_g0:(f + \cst)] + \store 0, c0, [r0, #:pc_g1:(f + \cst)] + \store 0, c0, [r0, #:pc_g2:(f + \cst)] + + \store 0, c0, [r0, #:sb_g0:(f + \cst)] + \store 0, c0, [r0, #:sb_g1:(f + \cst)] + \store 0, c0, [r0, #:sb_g2:(f + \cst)] + + \load 0, c0, [r0, #:pc_g0:(f - \cst)] + \load 0, c0, [r0, #:pc_g1:(f - \cst)] + \load 0, c0, [r0, #:pc_g2:(f - \cst)] + + \load 0, c0, [r0, #:sb_g0:(f - \cst)] + \load 0, c0, [r0, #:sb_g1:(f - \cst)] + \load 0, c0, [r0, #:sb_g2:(f - \cst)] + + \store 0, c0, [r0, #:pc_g0:(f - \cst)] + \store 0, c0, [r0, #:pc_g1:(f - \cst)] + \store 0, c0, [r0, #:pc_g2:(f - \cst)] + + \store 0, c0, [r0, #:sb_g0:(f - \cst)] + \store 0, c0, [r0, #:sb_g1:(f - \cst)] + \store 0, c0, [r0, #:sb_g2:(f - \cst)] + + .endm + + ldctest ldc stc 0x1 + ldctest ldcl stcl 0x1 + ldctest ldc2 stc2 0x1 + ldctest ldc2l stc2l 0x1 + + ldctest ldc stc 0x808 + ldctest ldcl stcl 0x808 + ldctest ldc2 stc2 0x808 + ldctest ldc2l stc2l 0x808 + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store cst + + \load f0, [r0, #:pc_g0:(f + \cst)] + \load f0, [r0, #:pc_g1:(f + \cst)] + \load f0, [r0, #:pc_g2:(f + \cst)] + + \load f0, [r0, #:sb_g0:(f + \cst)] + \load f0, [r0, #:sb_g1:(f + \cst)] + \load f0, [r0, #:sb_g2:(f + \cst)] + + \store f0, [r0, #:pc_g0:(f + \cst)] + \store f0, [r0, #:pc_g1:(f + \cst)] + \store f0, [r0, #:pc_g2:(f + \cst)] + + \store f0, [r0, #:sb_g0:(f + \cst)] + \store f0, [r0, #:sb_g1:(f + \cst)] + \store f0, [r0, #:sb_g2:(f + \cst)] + + \load f0, [r0, #:pc_g0:(f - \cst)] + \load f0, [r0, #:pc_g1:(f - \cst)] + \load f0, [r0, #:pc_g2:(f - \cst)] + + \load f0, [r0, #:sb_g0:(f - \cst)] + \load f0, [r0, #:sb_g1:(f - \cst)] + \load f0, [r0, #:sb_g2:(f - \cst)] + + \store f0, [r0, #:pc_g0:(f - \cst)] + \store f0, [r0, #:pc_g1:(f - \cst)] + \store f0, [r0, #:pc_g2:(f - \cst)] + + \store f0, [r0, #:sb_g0:(f - \cst)] + \store f0, [r0, #:sb_g1:(f - \cst)] + \store f0, [r0, #:sb_g2:(f - \cst)] + + .endm + + fpa_test ldfs stfs 0x1 + fpa_test ldfd stfd 0x1 + fpa_test ldfe stfe 0x1 + fpa_test ldfp stfp 0x1 + + fpa_test ldfs stfs 0x808 + fpa_test ldfd stfd 0x808 + fpa_test ldfe stfe 0x808 + fpa_test ldfp stfp 0x808 + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg cst + + \load \reg, [r0, #:pc_g0:(f + \cst)] + \load \reg, [r0, #:pc_g1:(f + \cst)] + \load \reg, [r0, #:pc_g2:(f + \cst)] + + \load \reg, [r0, #:sb_g0:(f + \cst)] + \load \reg, [r0, #:sb_g1:(f + \cst)] + \load \reg, [r0, #:sb_g2:(f + \cst)] + + \store \reg, [r0, #:pc_g0:(f + \cst)] + \store \reg, [r0, #:pc_g1:(f + \cst)] + \store \reg, [r0, #:pc_g2:(f + \cst)] + + \store \reg, [r0, #:sb_g0:(f + \cst)] + \store \reg, [r0, #:sb_g1:(f + \cst)] + \store \reg, [r0, #:sb_g2:(f + \cst)] + + \load \reg, [r0, #:pc_g0:(f - \cst)] + \load \reg, [r0, #:pc_g1:(f - \cst)] + \load \reg, [r0, #:pc_g2:(f - \cst)] + + \load \reg, [r0, #:sb_g0:(f - \cst)] + \load \reg, [r0, #:sb_g1:(f - \cst)] + \load \reg, [r0, #:sb_g2:(f - \cst)] + + \store \reg, [r0, #:pc_g0:(f - \cst)] + \store \reg, [r0, #:pc_g1:(f - \cst)] + \store \reg, [r0, #:pc_g2:(f - \cst)] + + \store \reg, [r0, #:sb_g0:(f - \cst)] + \store \reg, [r0, #:sb_g1:(f - \cst)] + \store \reg, [r0, #:sb_g2:(f - \cst)] + + .endm + + vfp_test flds fsts s0 0x1 + vfp_test flds fsts s0 0x808 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 0x1 + vfp_test fldd fstd d0 0x808 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 0x1 + vfp_test vldr vstr d0 0x808 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 0x1 + vfp_test cfldrd cfstrd mvd0 0x1 + vfp_test cfldr32 cfstr32 mvfx0 0x1 + vfp_test cfldr64 cfstr64 mvdx0 0x1 + + vfp_test cfldrs cfstrs mvf0 0x808 + vfp_test cfldrd cfstrd mvd0 0x808 + vfp_test cfldr32 cfstr32 mvfx0 0x808 + vfp_test cfldr64 cfstr64 mvdx0 0x808 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d new file mode 100644 index 00000000000..fa1840f1246 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, parsing failures (ldc) +#error-output: group-reloc-ldc-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l new file mode 100644 index 00000000000..238d94db1d9 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l @@ -0,0 +1,147 @@ +[^:]*: Assembler messages: +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:54: Error: too many positional arguments +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s new file mode 100644 index 00000000000..a815f5de75b --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s @@ -0,0 +1,67 @@ +@ Tests for LDC group relocations that are meant to fail during parsing. + + .macro ldctest insn reg + + \insn 0, \reg, [r0, #:pc_g0_nc:(sym)] + \insn 0, \reg, [r0, #:pc_g1_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g0_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g1_nc:(sym)] + + \insn 0, \reg, [r0, #:foo:(sym)] + + .endm + + .macro ldctest2 insn reg + + \insn \reg, [r0, #:pc_g0_nc:(sym)] + \insn \reg, [r0, #:pc_g1_nc:(sym)] + \insn \reg, [r0, #:sb_g0_nc:(sym)] + \insn \reg, [r0, #:sb_g1_nc:(sym)] + + \insn \reg, [r0, #:foo:(sym)] + + .endm + + ldctest ldc c0 + ldctest ldcl c0 + ldctest ldc2 c0 + ldctest ldc2l c0 + + ldctest stc c0 + ldctest stcl c0 + ldctest stc2 c0 + ldctest stc2l c0 + + .fpu fpa + + ldctest2 ldfs f0 + ldctest2 stfs f0 + ldctest2 ldfd f0 + ldctest2 stfd f0 + ldctest2 ldfe f0 + ldctest2 stfe f0 + ldctest2 ldfp f0 + ldctest2 stfp f0 + + .fpu vfp + + ldctest2 flds s0 + ldctest2 fsts s0 + + ldctest2 fldd d0 + ldctest2 fstd d0 + + ldctest2 vldr d0 FIXME + ldctest2 vstr d0 + + .cpu ep9312 + + ldctest2 cfldrs mvf0 + ldctest2 cfstrs mvf0 + ldctest2 cfldrd mvd0 + ldctest2 cfstrd mvd0 + ldctest2 cfldr32 mvfx0 + ldctest2 cfstr32 mvfx0 + ldctest2 cfldr64 mvdx0 + ldctest2 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/arm/group-reloc-ldc.d new file mode 100644 index 00000000000..106cf145b8f --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.d @@ -0,0 +1,726 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Group relocation tests (ldc) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 10: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 14: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 18: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 1c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 20: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 24: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 28: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 2c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 30: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 34: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 38: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 3c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 40: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 44: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 48: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 4c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 50: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 54: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 58: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 5c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 60: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 64: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 68: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 6c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 70: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 74: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 78: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 7c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 80: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 84: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 88: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 8c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 90: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 94: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 98: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 9c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 100: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 104: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 108: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 10c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 110: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 114: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 118: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 11c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 120: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 124: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 128: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 12c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 130: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 134: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 138: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 13c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 140: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 144: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 148: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 14c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 150: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 154: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 158: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 15c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 160: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 164: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 168: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 16c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 170: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 174: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 178: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 17c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 180: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 184: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 188: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 18c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 190: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 194: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 198: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 19c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 200: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 204: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 208: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 20c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 210: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 214: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 218: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 21c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 220: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 224: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 228: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 22c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 230: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 234: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 238: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 23c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 240: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 244: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 248: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 24c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 250: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 254: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 258: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 25c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 260: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 264: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 268: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 26c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 270: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 274: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 278: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 27c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 280: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 284: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 288: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 28c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 290: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 294: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 298: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 29c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2ac: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2b8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2bc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2cc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2dc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2e8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2ec: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2fc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 300: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 304: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 308: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 30c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 310: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 314: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 318: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 31c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 320: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 324: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 328: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 32c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 330: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 334: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 338: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 33c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 340: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 344: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 348: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 34c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 350: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 354: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 358: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 35c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 360: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 364: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 368: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 36c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 370: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 374: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 378: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 37c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 380: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 384: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 388: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 38c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 390: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 394: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 398: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 39c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 400: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 404: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 408: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 40c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 410: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 414: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 418: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 41c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 420: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 424: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 428: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 42c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 430: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 434: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 438: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 43c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 440: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 444: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 448: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 44c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 450: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 454: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 458: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 45c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 460: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 464: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 468: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 46c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 470: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 474: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 478: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 47c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 480: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 484: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 488: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 48c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 490: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 494: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 498: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 49c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 500: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 504: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 508: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 50c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 510: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 514: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 518: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 51c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 520: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 524: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 528: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 52c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 530: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 534: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 538: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 53c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 540: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 544: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 548: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 54c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 550: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 554: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 558: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 55c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 560: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 564: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 568: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 56c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 570: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 574: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 578: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 57c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 580: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 584: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 588: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 58c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 590: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 594: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 598: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 59c: R_ARM_LDC_SB_G2 f diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/arm/group-reloc-ldc.s new file mode 100644 index 00000000000..df27aaf55e0 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.s @@ -0,0 +1,151 @@ +@ LDC group relocation tests. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store + + \load 0, c0, [r0, #:pc_g0:(f + 0x214)] + \load 0, c0, [r0, #:pc_g1:(f + 0x214)] + \load 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f + 0x214)] + \load 0, c0, [r0, #:sb_g1:(f + 0x214)] + \load 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f + 0x214)] + \store 0, c0, [r0, #:pc_g1:(f + 0x214)] + \store 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f + 0x214)] + \store 0, c0, [r0, #:sb_g1:(f + 0x214)] + \store 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \load 0, c0, [r0, #:pc_g0:(f - 0x214)] + \load 0, c0, [r0, #:pc_g1:(f - 0x214)] + \load 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f - 0x214)] + \load 0, c0, [r0, #:sb_g1:(f - 0x214)] + \load 0, c0, [r0, #:sb_g2:(f - 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f - 0x214)] + \store 0, c0, [r0, #:pc_g1:(f - 0x214)] + \store 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f - 0x214)] + \store 0, c0, [r0, #:sb_g1:(f - 0x214)] + \store 0, c0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + ldctest ldc stc + ldctest ldcl stcl + ldctest ldc2 stc2 + ldctest ldc2l stc2l + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store + + \load f0, [r0, #:pc_g0:(f + 0x214)] + \load f0, [r0, #:pc_g1:(f + 0x214)] + \load f0, [r0, #:pc_g2:(f + 0x214)] + + \load f0, [r0, #:sb_g0:(f + 0x214)] + \load f0, [r0, #:sb_g1:(f + 0x214)] + \load f0, [r0, #:sb_g2:(f + 0x214)] + + \store f0, [r0, #:pc_g0:(f + 0x214)] + \store f0, [r0, #:pc_g1:(f + 0x214)] + \store f0, [r0, #:pc_g2:(f + 0x214)] + + \store f0, [r0, #:sb_g0:(f + 0x214)] + \store f0, [r0, #:sb_g1:(f + 0x214)] + \store f0, [r0, #:sb_g2:(f + 0x214)] + + \load f0, [r0, #:pc_g0:(f - 0x214)] + \load f0, [r0, #:pc_g1:(f - 0x214)] + \load f0, [r0, #:pc_g2:(f - 0x214)] + + \load f0, [r0, #:sb_g0:(f - 0x214)] + \load f0, [r0, #:sb_g1:(f - 0x214)] + \load f0, [r0, #:sb_g2:(f - 0x214)] + + \store f0, [r0, #:pc_g0:(f - 0x214)] + \store f0, [r0, #:pc_g1:(f - 0x214)] + \store f0, [r0, #:pc_g2:(f - 0x214)] + + \store f0, [r0, #:sb_g0:(f - 0x214)] + \store f0, [r0, #:sb_g1:(f - 0x214)] + \store f0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + fpa_test ldfs stfs + fpa_test ldfd stfd + fpa_test ldfe stfe + fpa_test ldfp stfp + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg + + \load \reg, [r0, #:pc_g0:(f + 0x214)] + \load \reg, [r0, #:pc_g1:(f + 0x214)] + \load \reg, [r0, #:pc_g2:(f + 0x214)] + + \load \reg, [r0, #:sb_g0:(f + 0x214)] + \load \reg, [r0, #:sb_g1:(f + 0x214)] + \load \reg, [r0, #:sb_g2:(f + 0x214)] + + \store \reg, [r0, #:pc_g0:(f + 0x214)] + \store \reg, [r0, #:pc_g1:(f + 0x214)] + \store \reg, [r0, #:pc_g2:(f + 0x214)] + + \store \reg, [r0, #:sb_g0:(f + 0x214)] + \store \reg, [r0, #:sb_g1:(f + 0x214)] + \store \reg, [r0, #:sb_g2:(f + 0x214)] + + \load \reg, [r0, #:pc_g0:(f - 0x214)] + \load \reg, [r0, #:pc_g1:(f - 0x214)] + \load \reg, [r0, #:pc_g2:(f - 0x214)] + + \load \reg, [r0, #:sb_g0:(f - 0x214)] + \load \reg, [r0, #:sb_g1:(f - 0x214)] + \load \reg, [r0, #:sb_g2:(f - 0x214)] + + \store \reg, [r0, #:pc_g0:(f - 0x214)] + \store \reg, [r0, #:pc_g1:(f - 0x214)] + \store \reg, [r0, #:pc_g2:(f - 0x214)] + + \store \reg, [r0, #:sb_g0:(f - 0x214)] + \store \reg, [r0, #:sb_g1:(f - 0x214)] + \store \reg, [r0, #:sb_g2:(f - 0x214)] + + .endm + + vfp_test flds fsts s0 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 + vfp_test cfldrd cfstrd mvd0 + vfp_test cfldr32 cfstr32 mvfx0 + vfp_test cfldr64 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d new file mode 100644 index 00000000000..6046de4a4c1 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, encoding failures (ldr) +#error-output: group-reloc-ldr-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l new file mode 100644 index 00000000000..276a341dc34 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l @@ -0,0 +1,97 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s new file mode 100644 index 00000000000..3c528f19975 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s @@ -0,0 +1,39 @@ +@ Tests that are supposed to fail during encoding +@ for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all fail. + + ldrtest ldr str f "+ 4096" + ldrtest ldrb strb f "+ 4096" + ldrtest ldr str f "- 4096" + ldrtest ldrb strb f "- 4096" + + ldrtest ldr str localsym "+ 4096" + ldrtest ldrb strb localsym "+ 4096" + ldrtest ldr str localsym "- 4096" + ldrtest ldrb strb localsym "- 4096" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d new file mode 100644 index 00000000000..688e2a35e5a --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, parsing failures (ldr) +#error-output: group-reloc-ldr-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l new file mode 100644 index 00000000000..316a6a6c8d8 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]' +[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]' +[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]' +[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s new file mode 100644 index 00000000000..c7d0ba75965 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s @@ -0,0 +1,33 @@ +@ Tests that are supposed to fail during parsing of LDR group relocations. + + .text + +@ No NC variants exist for the LDR relocations. + + ldr r0, [r0, #:pc_g0_nc:(f)] + ldr r0, [r0, #:pc_g1_nc:(f)] + ldr r0, [r0, #:sb_g0_nc:(f)] + ldr r0, [r0, #:sb_g1_nc:(f)] + + str r0, [r0, #:pc_g0_nc:(f)] + str r0, [r0, #:pc_g1_nc:(f)] + str r0, [r0, #:sb_g0_nc:(f)] + str r0, [r0, #:sb_g1_nc:(f)] + + ldrb r0, [r0, #:pc_g0_nc:(f)] + ldrb r0, [r0, #:pc_g1_nc:(f)] + ldrb r0, [r0, #:sb_g0_nc:(f)] + ldrb r0, [r0, #:sb_g1_nc:(f)] + + strb r0, [r0, #:pc_g0_nc:(f)] + strb r0, [r0, #:pc_g1_nc:(f)] + strb r0, [r0, #:sb_g0_nc:(f)] + strb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + + ldr r0, [r0, #:foo:(f)] + str r0, [r0, #:foo:(f)] + ldrb r0, [r0, #:foo:(f)] + strb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.d b/gas/testsuite/gas/arm/group-reloc-ldr.d new file mode 100644 index 00000000000..78cb2edc56c --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.d @@ -0,0 +1,199 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Group relocation tests (ldr) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 0: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 4: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 8: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 10: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 14: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 18: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 1c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 20: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 24: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 28: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 2c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 30: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 34: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 38: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 3c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 40: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 44: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 48: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 4c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 50: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 54: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 58: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 5c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 60: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 64: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 68: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 6c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 70: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 74: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 78: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 7c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 80: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 84: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 88: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 8c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 90: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 94: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 98: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 9c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a0: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a4: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + a8: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + ac: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b0: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b4: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b8: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + bc: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + cc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d0: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d4: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + d8: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + dc: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e0: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e4: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e8: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + ec: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + fc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 100: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 104: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 108: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 10c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 110: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 114: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 118: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 11c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 120: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 124: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 128: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 12c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 130: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 134: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 138: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 13c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 140: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 144: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 148: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 14c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 150: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 154: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 158: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 15c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 160: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 164: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 168: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 16c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 170: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 174: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 178: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 17c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.s b/gas/testsuite/gas/arm/group-reloc-ldr.s new file mode 100644 index 00000000000..389042d70af --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.s @@ -0,0 +1,41 @@ +@ Tests for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all (just) work. + + ldrtest ldr str f "+ 4095" + ldrtest ldrb strb f "+ 4095" + ldrtest ldr str f "- 4095" + ldrtest ldrb strb f "- 4095" + +@ The same as the above, but for a local symbol. These should not be +@ resolved by the assembler but instead left to the linker. + + ldrtest ldr str localsym "+ 4095" + ldrtest ldrb strb localsym "+ 4095" + ldrtest ldr str localsym "- 4095" + ldrtest ldrb strb localsym "- 4095" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d new file mode 100644 index 00000000000..c8cf5d5d830 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, encoding failures (ldrs) +#error-output: group-reloc-ldrs-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l new file mode 100644 index 00000000000..2621002d2ee --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l @@ -0,0 +1,121 @@ +[^:]*: Assembler messages: +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s new file mode 100644 index 00000000000..ac7a90f0e9e --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s @@ -0,0 +1,54 @@ +@ Tests that are meant to fail during encoding of LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) fail. + + ldrtest ldrd strd f "+ 256" + ldrtest ldrh strh f "+ 256" + ldrtest2 ldrsh f "+ 256" + ldrtest2 ldrsb f "+ 256" + + ldrtest ldrd strd f "- 256" + ldrtest ldrh strh f "- 256" + ldrtest2 ldrsh f "- 256" + ldrtest2 ldrsb f "- 256" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 256" + ldrtest ldrh strh localsym "+ 256" + ldrtest2 ldrsh localsym "+ 256" + ldrtest2 ldrsb localsym "+ 256" + + ldrtest ldrd strd localsym "- 256" + ldrtest ldrh strh localsym "- 256" + ldrtest2 ldrsh localsym "- 256" + ldrtest2 ldrsb localsym "- 256" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d new file mode 100644 index 00000000000..7150dfd6496 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d @@ -0,0 +1,2 @@ +#name: Group relocation tests, parsing failures (ldrs) +#error-output: group-reloc-ldrs-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l new file mode 100644 index 00000000000..b3d60351f19 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]' +[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]' +[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]' +[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]' +[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]' +[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s new file mode 100644 index 00000000000..16c1bea5ecf --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s @@ -0,0 +1,44 @@ +@ Tests that are supposed to fail during parsing of LDRS group relocations. + + .text + +@ No NC variants exist for the LDRS relocations. + + ldrd r0, [r0, #:pc_g0_nc:(f)] + ldrd r0, [r0, #:pc_g1_nc:(f)] + ldrd r0, [r0, #:sb_g0_nc:(f)] + ldrd r0, [r0, #:sb_g1_nc:(f)] + + strd r0, [r0, #:pc_g0_nc:(f)] + strd r0, [r0, #:pc_g1_nc:(f)] + strd r0, [r0, #:sb_g0_nc:(f)] + strd r0, [r0, #:sb_g1_nc:(f)] + + ldrh r0, [r0, #:pc_g0_nc:(f)] + ldrh r0, [r0, #:pc_g1_nc:(f)] + ldrh r0, [r0, #:sb_g0_nc:(f)] + ldrh r0, [r0, #:sb_g1_nc:(f)] + + strh r0, [r0, #:pc_g0_nc:(f)] + strh r0, [r0, #:pc_g1_nc:(f)] + strh r0, [r0, #:sb_g0_nc:(f)] + strh r0, [r0, #:sb_g1_nc:(f)] + + ldrsh r0, [r0, #:pc_g0_nc:(f)] + ldrsh r0, [r0, #:pc_g1_nc:(f)] + ldrsh r0, [r0, #:sb_g0_nc:(f)] + ldrsh r0, [r0, #:sb_g1_nc:(f)] + + ldrsb r0, [r0, #:pc_g0_nc:(f)] + ldrsb r0, [r0, #:pc_g1_nc:(f)] + ldrsb r0, [r0, #:sb_g0_nc:(f)] + ldrsb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + ldrd r0, [r0, #:foo:(f)] + strd r0, [r0, #:foo:(f)] + ldrh r0, [r0, #:foo:(f)] + strh r0, [r0, #:foo:(f)] + ldrsh r0, [r0, #:foo:(f)] + ldrsb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d new file mode 100644 index 00000000000..9a7d9fafd69 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d @@ -0,0 +1,247 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Group relocation tests (ldrs) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 10: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 14: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 18: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 1c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 20: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 24: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 28: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 2c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 30: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 34: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 38: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 3c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 40: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 44: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 48: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 4c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 50: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 54: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 58: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 5c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 60: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 64: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 68: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 6c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 70: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 74: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 78: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 7c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 80: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 84: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 88: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 8c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 90: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 94: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 98: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 9c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + ac: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + b0: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b4: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b8: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + bc: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c0: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c4: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + c8: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + cc: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d0: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d4: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d8: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + dc: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e0: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e4: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e8: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + ec: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f0: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f4: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f8: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + fc: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 100: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 104: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 108: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 10c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 110: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 114: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 118: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 11c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 120: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 124: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 128: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 12c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 130: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 134: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 138: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 13c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 140: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 144: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 148: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 14c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 150: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 154: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 158: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 15c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 160: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 164: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 168: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 16c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 170: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 174: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 178: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 17c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 180: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 184: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 188: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 18c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 190: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 194: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 198: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 19c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 1a0: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a4: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a8: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1ac: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b0: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b4: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1b8: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1bc: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c0: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c4: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c8: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1cc: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d0: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d4: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d8: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1dc: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.s b/gas/testsuite/gas/arm/group-reloc-ldrs.s new file mode 100644 index 00000000000..fa74e7eabe0 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.s @@ -0,0 +1,54 @@ +@ Tests for LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) work. + + ldrtest ldrd strd f "+ 255" + ldrtest ldrh strh f "+ 255" + ldrtest2 ldrsh f "+ 255" + ldrtest2 ldrsb f "+ 255" + + ldrtest ldrd strd f "- 255" + ldrtest ldrh strh f "- 255" + ldrtest2 ldrsh f "- 255" + ldrtest2 ldrsb f "- 255" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 255" + ldrtest ldrh strh localsym "+ 255" + ldrtest2 ldrsh localsym "+ 255" + ldrtest2 ldrsb localsym "+ 255" + + ldrtest ldrd strd localsym "- 255" + ldrtest ldrh strh localsym "- 255" + ldrtest2 ldrsh localsym "- 255" + ldrtest2 ldrsb localsym "- 255" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/mips/vxworks1-el.d b/gas/testsuite/gas/mips/vxworks1-el.d new file mode 100644 index 00000000000..3db07e4a17d --- /dev/null +++ b/gas/testsuite/gas/mips/vxworks1-el.d @@ -0,0 +1,72 @@ +#as: -mips2 -mvxworks-pic -mabi=32 -EL +#source: vxworks1.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +00000000 <\.text>: +# +# la $4,local +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 \.data +# +# la $4,global +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 global +# +# lw $4,local +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: 8c840000 lw a0,0\(a0\) +# +# lw $4,global +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 global +.*: 8c840000 lw a0,0\(a0\) +# +# sw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: ac240000 sw a0,0\(at\) +# +# sw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: ac240000 sw a0,0\(at\) +# +# ulw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: 88240003 lwl a0,3\(at\) +.*: 98240000 lwr a0,0\(at\) +# +# ulw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: 88240003 lwl a0,3\(at\) +.*: 98240000 lwr a0,0\(at\) +# +# usw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: a8240003 swl a0,3\(at\) +.*: b8240000 swr a0,0\(at\) +# +# usw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: a8240003 swl a0,3\(at\) +.*: b8240000 swr a0,0\(at\) + \.\.\. diff --git a/gas/testsuite/gas/mips/vxworks1-xgot-el.d b/gas/testsuite/gas/mips/vxworks1-xgot-el.d new file mode 100644 index 00000000000..c48d804f10d --- /dev/null +++ b/gas/testsuite/gas/mips/vxworks1-xgot-el.d @@ -0,0 +1,102 @@ +#as: -mips2 -mvxworks-pic -xgot -mabi=32 -EL +#source: vxworks1.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +00000000 <\.text>: +# +# la $4,local +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 \.data +# +# la $4,global +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 global +# +# lw $4,local +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 \.data +.*: 8c840000 lw a0,0\(a0\) +# +# lw $4,global +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 global +.*: 8c840000 lw a0,0\(a0\) +# +# sw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: ac240000 sw a0,0\(at\) +# +# sw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: ac240000 sw a0,0\(at\) +# +# ulw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: 88240003 lwl a0,3\(at\) +.*: 98240000 lwr a0,0\(at\) +# +# ulw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: 88240003 lwl a0,3\(at\) +.*: 98240000 lwr a0,0\(at\) +# +# usw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: a8240003 swl a0,3\(at\) +.*: b8240000 swr a0,0\(at\) +# +# usw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: a8240003 swl a0,3\(at\) +.*: b8240000 swr a0,0\(at\) + \.\.\. diff --git a/gas/testsuite/gas/mips/vxworks1-xgot.d b/gas/testsuite/gas/mips/vxworks1-xgot.d new file mode 100644 index 00000000000..660b34e07b5 --- /dev/null +++ b/gas/testsuite/gas/mips/vxworks1-xgot.d @@ -0,0 +1,102 @@ +#as: -mips2 -mvxworks-pic -xgot -mabi=32 -EB +#source: vxworks1.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +00000000 <\.text>: +# +# la $4,local +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 \.data +# +# la $4,global +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 global +# +# lw $4,local +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 \.data +.*: 8c840000 lw a0,0\(a0\) +# +# lw $4,global +# +.*: 3c040000 lui a0,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 009c2021 addu a0,a0,gp +.*: 8c840000 lw a0,0\(a0\) + .*: R_MIPS_GOT_LO16 global +.*: 8c840000 lw a0,0\(a0\) +# +# sw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: ac240000 sw a0,0\(at\) +# +# sw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: ac240000 sw a0,0\(at\) +# +# ulw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: 88240000 lwl a0,0\(at\) +.*: 98240003 lwr a0,3\(at\) +# +# ulw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: 88240000 lwl a0,0\(at\) +.*: 98240003 lwr a0,3\(at\) +# +# usw $4,local +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 \.data +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 \.data +.*: a8240000 swl a0,0\(at\) +.*: b8240003 swr a0,3\(at\) +# +# usw $4,global +# +.*: 3c010000 lui at,0x0 + .*: R_MIPS_GOT_HI16 global +.*: 003c0821 addu at,at,gp +.*: 8c210000 lw at,0\(at\) + .*: R_MIPS_GOT_LO16 global +.*: a8240000 swl a0,0\(at\) +.*: b8240003 swr a0,3\(at\) + \.\.\. diff --git a/gas/testsuite/gas/mips/vxworks1.d b/gas/testsuite/gas/mips/vxworks1.d new file mode 100644 index 00000000000..86d64b43a8e --- /dev/null +++ b/gas/testsuite/gas/mips/vxworks1.d @@ -0,0 +1,71 @@ +#as: -mips2 -mvxworks-pic -mabi=32 -EB +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +00000000 <\.text>: +# +# la $4,local +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 \.data +# +# la $4,global +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 global +# +# lw $4,local +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: 8c840000 lw a0,0\(a0\) +# +# lw $4,global +# +.*: 8f840000 lw a0,0\(gp\) + .*: R_MIPS_GOT16 global +.*: 8c840000 lw a0,0\(a0\) +# +# sw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: ac240000 sw a0,0\(at\) +# +# sw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: ac240000 sw a0,0\(at\) +# +# ulw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: 88240000 lwl a0,0\(at\) +.*: 98240003 lwr a0,3\(at\) +# +# ulw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: 88240000 lwl a0,0\(at\) +.*: 98240003 lwr a0,3\(at\) +# +# usw $4,local +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 \.data +.*: a8240000 swl a0,0\(at\) +.*: b8240003 swr a0,3\(at\) +# +# usw $4,global +# +.*: 8f810000 lw at,0\(gp\) + .*: R_MIPS_GOT16 global +.*: a8240000 swl a0,0\(at\) +.*: b8240003 swr a0,3\(at\) + \.\.\. diff --git a/ld/emulparams/elf32bfinfd.sh b/ld/emulparams/elf32bfinfd.sh new file mode 100644 index 00000000000..19ec748b7fb --- /dev/null +++ b/ld/emulparams/elf32bfinfd.sh @@ -0,0 +1,16 @@ +. ${srcdir}/emulparams/bfin.sh +unset STACK_ADDR +OUTPUT_FORMAT="elf32-bfinfdpic" +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +TEMPLATE_NAME=elf32 +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes +EMBEDDED= # This gets us program headers mapped as part of the text segment. +OTHER_GOT_SYMBOLS= +OTHER_READONLY_SECTIONS=" + .rofixup : { + ${RELOCATING+__ROFIXUP_LIST__ = .;} + *(.rofixup) + ${RELOCATING+__ROFIXUP_END__ = .;} + } +" diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.d b/ld/testsuite/ld-arm/group-relocs-alu-bad.d new file mode 100644 index 00000000000..0346db1a973 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.d @@ -0,0 +1,4 @@ +#name: ALU group relocations failure test +#source: group-relocs-alu-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x9010 +#error: Overflow whilst splitting 0x1010 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.s b/ld/testsuite/ld-arm/group-relocs-alu-bad.s new file mode 100644 index 00000000000..e644669c3b9 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.s @@ -0,0 +1,20 @@ +@ Test intended to fail for ALU group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ a specific PC-relative offset arises. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0:(bar) + +@ We will place the section foo at 0x9004. + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.d b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d new file mode 100644 index 00000000000..d4bfb2dfbdd --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d @@ -0,0 +1,4 @@ +#name: LDC group relocations failure test +#source: group-relocs-ldc-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x118400 +#error: Overflow whilst splitting 0x110400 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.s b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s new file mode 100644 index 00000000000..611255b063d --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s @@ -0,0 +1,19 @@ +@ Test intended to fail for LDC group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0_nc:(bar) + ldc 0, c0, [r0, #:pc_g1:(bar + 4)] + +@ We will place the section foo at 0x118400. +@ (The relocations above would be OK if it were at 0x118200, for example.) + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.d b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d new file mode 100644 index 00000000000..04586af34f5 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d @@ -0,0 +1,4 @@ +#name: LDR group relocations failure test +#source: group-relocs-ldr-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8001000 +#error: .*Overflow whilst splitting 0x8001000 for group relocation.* diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.s b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s new file mode 100644 index 00000000000..6ab4f3c9746 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s @@ -0,0 +1,18 @@ +@ Test intended to fail for LDR group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldr r1, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8001000. + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d new file mode 100644 index 00000000000..0520184b336 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d @@ -0,0 +1,4 @@ +#name: LDRS group relocations failure test +#source: group-relocs-ldrs-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8000100 +#error: Overflow whilst splitting 0x8000100 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s new file mode 100644 index 00000000000..4480d4aa5f0 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s @@ -0,0 +1,17 @@ +@ Test intended to fail for LDRS group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldrd r2, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8000100. + + .section foo + +bar: + mov r0, #0 diff --git a/ld/testsuite/ld-arm/group-relocs.d b/ld/testsuite/ld-arm/group-relocs.d new file mode 100644 index 00000000000..d1fdc7d1b77 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs.d @@ -0,0 +1,69 @@ + +tmpdir/group-relocs: file format elf32-(little|big)arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: e28f00bc add r0, pc, #188 ; 0xbc + 8004: e28f0c6e add r0, pc, #28160 ; 0x6e00 + 8008: e28000ec add r0, r0, #236 ; 0xec + 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000 + 8010: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8014: e28000e4 add r0, r0, #228 ; 0xe4 + 8018: e2800000 add r0, r0, #0 ; 0x0 + 801c: e28f0cee add r0, pc, #60928 ; 0xee00 + 8020: e28000f0 add r0, r0, #240 ; 0xf0 + 8024: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8028: e2800cee add r0, r0, #60928 ; 0xee00 + 802c: e28000f0 add r0, r0, #240 ; 0xf0 + 8030: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8034: e59010c0 ldr r1, \[r0, #192\] + 8038: e28008ff add r0, r0, #16711680 ; 0xff0000 + 803c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8040: e59010b8 ldr r1, \[r0, #184\] + 8044: e5901000 ldr r1, \[r0\] + 8048: e2800cee add r0, r0, #60928 ; 0xee00 + 804c: e59010f0 ldr r1, \[r0, #240\] + 8050: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8054: e2800cee add r0, r0, #60928 ; 0xee00 + 8058: e59010f0 ldr r1, \[r0, #240\] + 805c: e1c026d0 ldrd r2, \[r0, #96\] + 8060: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8064: e1c029d0 ldrd r2, \[r0, #144\] + 8068: e28008ff add r0, r0, #16711680 ; 0xff0000 + 806c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8070: e1c028d8 ldrd r2, \[r0, #136\] + 8074: e1c020d0 ldrd r2, \[r0\] + 8078: e2800cee add r0, r0, #60928 ; 0xee00 + 807c: e1c02fd0 ldrd r2, \[r0, #240\] + 8080: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8084: e2800cee add r0, r0, #60928 ; 0xee00 + 8088: e1c02fd0 ldrd r2, \[r0, #240\] + 808c: ed90000c ldc 0, cr0, \[r0, #48\] + 8090: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8094: ed900018 ldc 0, cr0, \[r0, #96\] + 8098: e28008ff add r0, r0, #16711680 ; 0xff0000 + 809c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 80a0: ed900016 ldc 0, cr0, \[r0, #88\] + 80a4: ed900000 ldc 0, cr0, \[r0\] + 80a8: e2800cee add r0, r0, #60928 ; 0xee00 + 80ac: ed90003c ldc 0, cr0, \[r0, #240\] + 80b0: e28008ff add r0, r0, #16711680 ; 0xff0000 + 80b4: e2800cee add r0, r0, #60928 ; 0xee00 + 80b8: ed90003c ldc 0, cr0, \[r0, #240\] + +000080bc : + 80bc: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section zero: + +00000000 : + 0: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section alpha: + +0000eef0 : + eef0: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section beta: + +00ffeef0 : + ffeef0: e3a00000 mov r0, #0 ; 0x0 +#... diff --git a/ld/testsuite/ld-arm/group-relocs.s b/ld/testsuite/ld-arm/group-relocs.s new file mode 100644 index 00000000000..da1a1507268 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs.s @@ -0,0 +1,156 @@ +@ Tests for group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ specific PC- and SB-relative offsets arise. +@ +@ Note that the gas tests have already checked that group relocations are +@ handled in the same way for local and external symbols. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + @ ALU, PC-relative + + @ Instructions start at .text + 0x0 + add r0, r15, #:pc_g0:(one_group_needed_alu_pc) + + @ Instructions start at .text + 0x4 + add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc) + add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4) + + @ Instructions start at .text + 0xc + add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4) + add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8) + + @ ALU, SB-relative + + add r0, r0, #:sb_g0:(one_group_needed_alu_sb) + + add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb) + add r0, r0, #:sb_g1:(two_groups_needed_alu_sb) + + add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g2:(three_groups_needed_alu_sb) + + @ LDR, PC-relative + + @ Instructions start at .text + 0x30 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc) + ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)] + + @ Instructions start at .text + 0x38 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4) + ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)] + + @ LDR, SB-relative + + ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)] + + @ LDRS, PC-relative + + @ Instructions start at .text + 0x5c + ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)] + + @ Instructions start at .text + 0x60 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc) + ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)] + + @ Instructions start at .text + 0x68 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4) + ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)] + + @ LDRS, SB-relative + + ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)] + + @ LDC, PC-relative + + @ Instructions start at .text + 0x8c + ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)] + + @ Instructions start at .text + 0x90 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc) + ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)] + + @ Instructions start at .text + 0x98 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4) + ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)] + + @ LDC, SB-relative + + ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)] + +@ This point in the file is .text + 0xbc. + +one_group_needed_alu_pc: +one_group_needed_ldrs_pc: +one_group_needed_ldc_pc: + mov r0, #0 + +@ We will place the section zero at 0x0. + + .section zero + +one_group_needed_alu_sb: +one_group_needed_ldr_sb: +one_group_needed_ldrs_sb: +one_group_needed_ldc_sb: + mov r0, #0 + +@ We will place the section alpha at 0xeef0. + + .section alpha + +two_groups_needed_alu_sb: +two_groups_needed_ldr_sb: +two_groups_needed_ldrs_sb: +two_groups_needed_ldc_sb: +two_groups_needed_alu_pc: +two_groups_needed_ldr_pc: +two_groups_needed_ldrs_pc: +two_groups_needed_ldc_pc: + mov r0, #0 + +@ We will place the section beta at 0xffeef0. + + .section beta + +three_groups_needed_alu_sb: +three_groups_needed_ldr_sb: +three_groups_needed_ldrs_sb: +three_groups_needed_ldc_sb: +three_groups_needed_alu_pc: +three_groups_needed_ldr_pc: +three_groups_needed_ldrs_pc: +three_groups_needed_ldc_pc: + mov r0, #0 + diff --git a/ld/testsuite/ld-elf/eh1.s b/ld/testsuite/ld-elf/eh1.s new file mode 100644 index 00000000000..a6052096808 --- /dev/null +++ b/ld/testsuite/ld-elf/eh1.s @@ -0,0 +1,47 @@ + .text +.globl _start + .type _start, %function +_start: +.LFB2: +.LCFI0: +.LCFI1: +.LFE2: + .size _start, .-_start + .section .eh_frame,"a",%progbits +.Lframe1: + .long .LECIE1-.LSCIE1 +.LSCIE1: + .long 0x0 + .byte 0x1 + .string "" + .uleb128 0x1 + .sleb128 -8 + .byte 0x10 + .byte 0xc + .uleb128 0x7 + .uleb128 0x8 + .byte 0x90 + .uleb128 0x1 + .align 8 +.LECIE1: +.LSFDE1: + .long .LEFDE1-.LASFDE1 +.LASFDE1: + .long .LASFDE1-.Lframe1 + .quad .LFB2 + .quad .LFE2-.LFB2 + .byte 0x4 + .long .LCFI0-.LFB2 + .byte 0xe + .uleb128 0x10 + .byte 0x86 + .uleb128 0x2 + .byte 0x4 + .long .LCFI1-.LCFI0 + .byte 0xd + .uleb128 0x6 + .byte 0x0 + .byte 0x0 + .byte 0x0 + .byte 0x0 +.LEFDE1: diff --git a/ld/testsuite/ld-elf/eh1a.s b/ld/testsuite/ld-elf/eh1a.s new file mode 100644 index 00000000000..c644014dc6d --- /dev/null +++ b/ld/testsuite/ld-elf/eh1a.s @@ -0,0 +1,3 @@ + .section .eh_frame,"a",%progbits + .align 8 + .zero 4 diff --git a/ld/testsuite/ld-elf/eh2a.s b/ld/testsuite/ld-elf/eh2a.s new file mode 100644 index 00000000000..2c024f8f080 --- /dev/null +++ b/ld/testsuite/ld-elf/eh2a.s @@ -0,0 +1,3 @@ + .section .eh_frame,"a",%progbits + .align 4 + .zero 4 diff --git a/ld/testsuite/ld-elf/eh3.s b/ld/testsuite/ld-elf/eh3.s new file mode 100644 index 00000000000..24bd90d2413 --- /dev/null +++ b/ld/testsuite/ld-elf/eh3.s @@ -0,0 +1,48 @@ + .text +.globl _start + .type _start, %function +_start: +.LFB2: +.LCFI0: +.LCFI1: +.LFE2: + .size _start, .-_start + .section .eh_frame,"a",%progbits + .align 16 +.Lframe1: + .long .LECIE1-.LSCIE1 +.LSCIE1: + .long 0x0 + .byte 0x1 + .string "" + .uleb128 0x1 + .sleb128 -8 + .byte 0x10 + .byte 0xc + .uleb128 0x7 + .uleb128 0x8 + .byte 0x90 + .uleb128 0x1 + .align 8 +.LECIE1: +.LSFDE1: + .long .LEFDE1-.LASFDE1 +.LASFDE1: + .long .LASFDE1-.Lframe1 + .quad .LFB2 + .quad .LFE2-.LFB2 + .byte 0x4 + .long .LCFI0-.LFB2 + .byte 0xe + .uleb128 0x10 + .byte 0x86 + .uleb128 0x2 + .byte 0x4 + .long .LCFI1-.LCFI0 + .byte 0xd + .uleb128 0x6 + .byte 0x0 + .byte 0x0 + .byte 0x0 + .byte 0x0 +.LEFDE1: diff --git a/ld/testsuite/ld-elf/eh3a.s b/ld/testsuite/ld-elf/eh3a.s new file mode 100644 index 00000000000..c245871ed10 --- /dev/null +++ b/ld/testsuite/ld-elf/eh3a.s @@ -0,0 +1,3 @@ + .section .eh_frame,"a",%progbits + .align 8 + .zero 8 diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d new file mode 100644 index 00000000000..b59bb5fb9c2 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d @@ -0,0 +1,18 @@ + +.*: file format elf32-tradbigmips + +Disassembly of section \.MIPS\.stubs: + +.* <\.MIPS.stubs>: +.*: 8f998010 lw t9,-32752\(gp\) +.*: 03e07821 move t7,ra +.*: 3c180001 lui t8,0x1 +.*: 0320f809 jalr t9 +.*: 37180000 ori t8,t8,0x0 +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +Disassembly of section .text: +#pass diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d new file mode 100644 index 00000000000..07ca1a2ba5f --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d @@ -0,0 +1,18 @@ + +.*: file format elf32-tradbigmips + +Disassembly of section \.MIPS\.stubs: + +.* <\.MIPS.stubs>: +.*: 8f998010 lw t9,-32752\(gp\) +.*: 03e07821 move t7,ra +.*: 3c180002 lui t8,0x2 +.*: 0320f809 jalr t9 +.*: 3718fe80 ori t8,t8,0xfe80 +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +Disassembly of section .text: +#pass diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d new file mode 100644 index 00000000000..bfc94c5a6d4 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d @@ -0,0 +1,16 @@ + +.*: file format elf32-tradbigmips + +Disassembly of section \.MIPS\.stubs: + +.* <\.MIPS.stubs>: +.*: 8f998010 lw t9,-32752\(gp\) +.*: 03e07821 move t7,ra +.*: 0320f809 jalr t9 +.*: 24187fff li t8,32767 +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +Disassembly of section .text: +#pass diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d new file mode 100644 index 00000000000..2861ac222a8 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d @@ -0,0 +1,16 @@ + +.*: file format elf32-tradbigmips + +Disassembly of section \.MIPS\.stubs: + +.* <\.MIPS.stubs>: +.*: 8f998010 lw t9,-32752\(gp\) +.*: 03e07821 move t7,ra +.*: 0320f809 jalr t9 +.*: 34188000 li t8,0x8000 +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +Disassembly of section .text: +#pass diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d new file mode 100644 index 00000000000..440d32a9dad --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d @@ -0,0 +1,16 @@ + +.*: file format elf32-tradbigmips + +Disassembly of section \.MIPS\.stubs: + +.* <\.MIPS.stubs>: +.*: 8f998010 lw t9,-32752\(gp\) +.*: 03e07821 move t7,ra +.*: 0320f809 jalr t9 +.*: 3418fff0 li t8,0xfff0 +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +.*: 00000000 nop +Disassembly of section .text: +#pass diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld b/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld new file mode 100644 index 00000000000..17c998df029 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld @@ -0,0 +1,17 @@ +SECTIONS +{ + . = 0x80000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.dyn : { *(.rel.dyn) } + .MIPS.stubs : { *(.MIPS.stubs) } + .text : { *(.text) } + + . = ALIGN (0x10000); + _gp = . + 0x7ff0; + .got : { *(.got) } + + /DISCARD/ : { *(.reginfo) } +} diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1.s b/ld/testsuite/ld-mips-elf/stub-dynsym-1.s new file mode 100644 index 00000000000..15d2e1b8025 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1.s @@ -0,0 +1,10 @@ + .macro decl + .global exported\@ + .equ exported\@,\@ + .endm + + .rept dynsym - base_syms + decl + .endr + + lw $25,%call16(foo)($gp) -- 2.47.2