From fd97444eb2a82e13923a48b0b6951e3530d02c74 Mon Sep 17 00:00:00 2001 From: Stefan Maksimovic Date: Fri, 17 Apr 2020 18:05:20 +0000 Subject: [PATCH] mips: add a special case for beq r0, r0, imm This results in unconditional PUTs to PC in generated IR code. This fixes: memcheck/tests/cdebug_zlib memcheck/tests/cdebug_zlib_gnu memcheck/tests/origin2-not-quite memcheck/tests/origin5-bz2 none/tests/mips64/branch_and_jump_instructions --- VEX/priv/guest_mips_toIR.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index d915487af0..489d91afb7 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -20034,16 +20034,31 @@ static UInt disInstr_MIPS_WRK_00(UInt cins, const VexArchInfo* archinfo, *lastn = mkexpr(t0); break; - case 0x04: /* BEQ */ - DIP("beq r%u, r%u, %u", rs, rt, imm); + case 0x04: /* BEQ, B */ + if (rs == 0 && rt == 0) { + ULong branch_offset; + t0 = newTemp(ty); + DIP("b %u", imm); - if (mode64) - dis_branch(False, binop(Iop_CmpEQ64, getIReg(rs), getIReg(rt)), - imm, bstmt); - else - dis_branch(False, binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)), - imm, bstmt); + if (mode64) { + branch_offset = extend_s_18to64(imm << 2); + assign(t0, mkU64(guest_PC_curr_instr + 4 + branch_offset)); + } else { + branch_offset = extend_s_18to32(imm << 2); + assign(t0, mkU32(guest_PC_curr_instr + 4 + branch_offset)); + } + *lastn = mkexpr(t0); + } else { + DIP("beq r%u, r%u, %u", rs, rt, imm); + + if (mode64) + dis_branch(False, binop(Iop_CmpEQ64, getIReg(rs), getIReg(rt)), + imm, bstmt); + else + dis_branch(False, binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)), + imm, bstmt); + } break; case 0x05: /* BNE */ -- 2.47.3