From fe16dc2d88cbacbedaa9e354fc558ad0128f504e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 16 Sep 2021 04:27:28 -0600 Subject: [PATCH] clk: versal: Enable only GATE type clocks Clocks should be enabled or disabled only if they are of GATE type clocks. If they are not of GATE type clocks, don't touch them. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_versal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 86d35bfdce3..3134ca5a526 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + + return 0; } static struct clk_ops versal_clk_ops = { -- 2.47.3