From fe6262910cd3fefe8a23d5f59a701085f7adad6b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 4 Nov 2025 15:47:26 +0100 Subject: [PATCH] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock Some IOMMUs on some platforms (there doesn't seem to be a good denominator for this) require the presence of a third clock, specifically relating to the instance's Translation Buffer Unit (TBU). Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section "8.8.3.1.2 Clock gating", which reads: For APPS TCU/TBU (TBU to TCU interface is asynchronous) Software should turn ON clock to APPS TCU - During APPS TCU register programming sequence For GPU TCU/TBU (TBU to TCU interface is synchronous) Software should turn ON clock to GPU TBU - During GPU TLB invalidation sequence <===================== Software should turn ON clock to GPU TCU - During GPU TCU register programming sequence - While GPU master clock is Active The clock should be turned on at least during TLB invalidation on the GPU SMMU instance. This is corroborated by Commit 5bc1cf1466f6 ("iommu/qcom: add optional 'tbu' clock for TLB invalidate"). This is also not to be confused with qcom,sdm845-tbu, which is a description of a debug interface, absent on the generation of hardware that this binding describes. Allow this clock. [1] https://lore.kernel.org/linux-arm-msm/aPX_cKtial56AgvU@linaro.org/ Reviewed-by: Rob Herring Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml index 3e5623edd207a..93a4890253170 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -32,14 +32,18 @@ properties: - const: qcom,msm-iommu-v2 clocks: + minItems: 2 items: - description: Clock required for IOMMU register group access - description: Clock required for underlying bus access + - description: Clock required for Translation Buffer Unit access clock-names: + minItems: 2 items: - const: iface - const: bus + - const: tbu power-domains: maxItems: 1 -- 2.47.3