From fe7fb85893b22ed528eed1618b9eed8a3f2348b2 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 21 Jan 2015 03:25:34 +0800 Subject: [PATCH] update queue-3.18/clk-rockchip-fix-rk3066-pll-lock-bit-location.patch --- .../clk-rockchip-fix-rk3066-pll-lock-bit-location.patch | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/queue-3.18/clk-rockchip-fix-rk3066-pll-lock-bit-location.patch b/queue-3.18/clk-rockchip-fix-rk3066-pll-lock-bit-location.patch index 7319a5c778a..d04675de763 100644 --- a/queue-3.18/clk-rockchip-fix-rk3066-pll-lock-bit-location.patch +++ b/queue-3.18/clk-rockchip-fix-rk3066-pll-lock-bit-location.patch @@ -24,6 +24,7 @@ Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 cloc Tested-by: FUKAUMI Naoki Signed-off-by: Greg Kroah-Hartman + --- drivers/clk/rockchip/clk-rk3188.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) @@ -36,13 +37,13 @@ Signed-off-by: Greg Kroah-Hartman +static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), -+ RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), ++ RK2928_MODE_CON, 0, 5, rk3188_pll_rates), + [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), -+ RK2928_MODE_CON, 4, 4, 0, NULL), ++ RK2928_MODE_CON, 4, 4, NULL), + [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), -+ RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), ++ RK2928_MODE_CON, 8, 6, rk3188_pll_rates), + [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), -+ RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), ++ RK2928_MODE_CON, 12, 7, rk3188_pll_rates), +}; + static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { -- 2.47.3