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thirdparty/qemu.git
2025-05-21  Daniel P. Berrangéui/vnc: take account of client byte order in pixman...
2025-05-21  Daniel P. Berrangéui/vnc.c: replace big endian flag with byte order value
2025-05-20  Stefan HajnocziMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2025-05-20  Paolo Bonziniqom: reverse order of instance_post_init calls
2025-05-20  Paolo Bonzinitarget/riscv: remove .instance_post_init
2025-05-20  Paolo Bonzinitarget/riscv: convert Xiangshan Nanhu to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert Ventana V1 to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert TT Ascalon to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert THead C906 to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: generalize custom CSR functionality
2025-05-20  Paolo Bonzinitarget/riscv: th: make CSR insertion test a bit more...
2025-05-20  Paolo Bonzinitarget/riscv: convert SiFive U models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert ibex CPU models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert SiFive E CPU models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert dynamic CPU models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert bare CPU models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert profile CPU models to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: convert abstract CPU classes to RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: add more RISCVCPUDef fields
2025-05-20  Paolo Bonzinitarget/riscv: include default value in cpu_cfg_fields...
2025-05-20  Paolo Bonzinitarget/riscv: move RISCVCPUConfig fields to a header...
2025-05-20  Paolo Bonzinitarget/riscv: merge riscv_cpu_class_init with the class...
2025-05-20  Paolo Bonzinitarget/riscv: store RISCVCPUDef struct directly in...
2025-05-20  Paolo Bonzinitarget/riscv: introduce RISCVCPUDef
2025-05-20  Paolo Bonzinitarget/riscv: move satp_mode.{map,init} out of CPUConfig
2025-05-20  Paolo Bonzinitarget/riscv: remove supported from RISCVSATPMap
2025-05-20  Paolo Bonzinitarget/riscv: update max_satp_mode based on QOM properties
2025-05-20  Paolo Bonzinitarget/riscv: cpu: store max SATP mode as a single...
2025-05-20  Paolo Bonzinitarget/riscv: assert argument to set_satp_mode_max_supp...
2025-05-20  Paolo Bonzinihw/riscv: acpi: only create RHCT MMU entry for supporte...
2025-05-20  Zhao Liuqapi/misc-target: Fix the doc to distinguish query...
2025-05-20  Zhao Liuqapi/misc-target: Fix the doc related SGXEPCSection
2025-05-20  Zhao Liuqapi/misc-target: Rename SGXInfo to SgxInfo
2025-05-20  Zhao Liuqapi/misc-target: Rename SGXEPCSection to SgxEpcSection
2025-05-20  Rakesh Jeyasinghhw/pci-host: Remove unused pci_host_data_be_ops
2025-05-20  Rakesh Jeyasinghhw/pci-host/gt64120: Fix endianness handling
2025-05-20  Xiaoyao Lii386/hvf: Make CPUID_HT supported
2025-05-20  Xiaoyao Lii386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported
2025-05-19  Stefan HajnocziMerge tag 'pull-riscv-to-apply-20250519' of https:...
2025-05-19  Daniel Henrique... hw/riscv/virt.c: remove 'long' casts in fmt strings
2025-05-19  Daniel Henrique... hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
2025-05-19  Daniel Henrique... hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
2025-05-19  Daniel Henrique... hw/riscv/virt.c: use s->memmap in create_fdt_sockets...
2025-05-19  Daniel Henrique... hw/riscv/virt.c: use s->memmap in create_fdt() path
2025-05-19  Daniel Henrique... hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
2025-05-19  Daniel Henrique... hw/riscv/virt.c: use s->memmap in virt_machine_done()
2025-05-19  Daniel Henrique... hw/riscv/virt.c: remove trivial virt_memmap references
2025-05-19  Daniel Henrique... hw/riscv/virt.c: enforce s->memmap use in machine_init()
2025-05-19  Daniel Henrique... target/riscv/kvm: add scounteren CSR
2025-05-19  Daniel Henrique... target/riscv/kvm: read/write KVM regs via env size
2025-05-19  Daniel Henrique... target/riscv/kvm: add senvcfg CSR
2025-05-19  Daniel Henrique... target/riscv/kvm: do not read unavailable CSRs
2025-05-19  Daniel Henrique... target/riscv/kvm: add kvm_csr_cfgs[]
2025-05-19  Daniel Henrique... target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into...
2025-05-19  Daniel Henrique... target/riscv/kvm: turn u32/u64 reg functions into macros
2025-05-19  Daniel Henrique... target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
2025-05-19  Daniel Henrique... target/riscv/kvm: minor fixes/tweaks
2025-05-19  Richard Hendersontarget/riscv: Fix write_misa vs aligned next_pc
2025-05-19  Richard Hendersontarget/riscv: Move insn_len to internals.h
2025-05-19  Richard Hendersontarget/riscv: Pass ra to riscv_csrrw_i128
2025-05-19  Richard Hendersontarget/riscv: Pass ra to riscv_csrrw
2025-05-19  Richard Hendersontarget/riscv: Pass ra to riscv_csrrw_do128
2025-05-19  Richard Hendersontarget/riscv: Pass ra to riscv_csrrw_do64
2025-05-19  Richard Hendersontarget/riscv: Pass ra to riscv_csr_write_fn
2025-05-19  Alistair FrancisMAINTAINERS: Add common-user/host/riscv to RISC-V section
2025-05-19  Anton Blanchardtarget/riscv: Fix vslidedown with rvv_ta_all_1s
2025-05-19  Max Choutarget/riscv: Fix the rvv reserved encoding of unmasked...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to vector...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to vector...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to vector...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to vector...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to OPIVV...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to OPIVI...
2025-05-19  Max Choutarget/riscv: rvv: Apply vext_check_input_eew to vrgath...
2025-05-19  Anton Blanchardtarget/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
2025-05-19  Anton Blanchardtarget/riscv: rvv: Source vector registers cannot overl...
2025-05-19  Icenowy Zhengcommon-user/host/riscv: use tail pseudoinstruction...
2025-05-19  Ziqiao Kongtarget/riscv: fix endless translation loop on big endia...
2025-05-19  Paolo Bonzinihw/riscv: Fix type conflict of GLib function pointers
2025-05-19  Paolo SaviniExpand the probe_pages helper function to handle probe...
2025-05-19  Paolo Savinitarget/riscv: use tcg ops generation to emulate whole...
2025-05-19  Sebastian Huberhw/riscv: microchip_pfsoc: Rework documentation
2025-05-19  Sebastian Huberhw/riscv: Configurable MPFS CLINT timebase freq
2025-05-19  Sebastian Huberhw/riscv: Allow direct start of kernel for MPFS
2025-05-19  Sebastian Huberhw/riscv: Make FDT optional for MPFS
2025-05-19  Sebastian Huberhw/riscv: More flexible FDT placement for MPFS
2025-05-19  Sebastian Huberhw/misc: Add MPFS system reset support
2025-05-19  Paolo SaviniGenerate strided vector loads/stores with tcg nodes.
2025-05-19  Loïc Leforttarget/riscv: pmp: remove redundant check in pmp_is_locked
2025-05-19  Loïc Leforttarget/riscv: pmp: exit csr writes early if value was...
2025-05-19  Loïc Leforttarget/riscv: pmp: fix checks on writes to pmpcfg in...
2025-05-19  Loïc Leforttarget/riscv: pmp: move Smepmp operation conversion...
2025-05-19  Loïc Leforttarget/riscv: pmp: don't allow RLB to bypass rule privi...
2025-05-19  Sunil V Lhw/riscv/virt-acpi-build: Add support for RIMT
2025-05-19  Sunil V Lhw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState...
2025-05-15  Stefan HajnocziMerge tag 'pull-nvme-20250515' of https://gitlab.com...
2025-05-15  Stefan HajnocziMerge tag 'pull-target-arm-20250515' of https://git...
2025-05-15  Stefan HajnocziMerge tag 'pull-nbd-2025-05-14' of https://repo.or...
2025-05-15  Stefan HajnocziMerge tag 'for_upstream' of https://git.kernel.org...
2025-05-15  Stefan HajnocziMerge tag 'pull-request-2025-05-14' of https://gitlab...
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