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Commit | Line | Data |
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f7075c3a SS |
1 | From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001 |
2 | From: Sean Cross <xobs@kosagi.com> | |
3 | Date: Thu, 26 Sep 2013 10:51:09 +0800 | |
4 | Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node | |
5 | ||
6 | Add pcie device node for imx6qdl. | |
7 | ||
8 | Signed-off-by: Sean Cross <xobs@kosagi.com> | |
9 | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> | |
10 | --- | |
11 | arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++ | |
12 | 1 file changed, 16 insertions(+) | |
13 | ||
14 | --- a/arch/arm/boot/dts/imx6qdl.dtsi | |
15 | +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |
16 | @@ -108,6 +108,22 @@ | |
17 | cache-level = <2>; | |
18 | }; | |
19 | ||
20 | + pcie: pcie@0x01000000 { | |
21 | + compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
22 | + reg = <0x01ffc000 0x4000>; /* DBI */ | |
23 | + #address-cells = <3>; | |
24 | + #size-cells = <2>; | |
25 | + device_type = "pci"; | |
26 | + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
27 | + 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
28 | + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
29 | + num-lanes = <1>; | |
30 | + interrupts = <0 123 0x04>; | |
31 | + clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; | |
32 | + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; | |
33 | + status = "disabled"; | |
34 | + }; | |
35 | + | |
36 | pmu { | |
37 | compatible = "arm,cortex-a9-pmu"; | |
38 | interrupts = <0 94 0x04>; |