projects / ipfire-2.x.git / blame
| Commit | Line | Data |
|---|---|---|
| f7075c3a SS |
1 | From: Sean Cross <xobs@kosagi.com> |
| 2 | Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition | |
| 3 | ||
| 4 | PCIe requires additional bits be defined for GPR8 and GPR12. | |
| 5 | ||
| 6 | Signed-off-by: Sean Cross <xobs@kosagi.com> | |
| 7 | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> | |
| 8 | Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | |
| 9 | --- | |
| 10 | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ | |
| 11 | 1 file changed, 8 insertions(+) | |
| 12 | ||
| 13 | --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |
| 14 | +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |
| 15 | @@ -241,6 +241,12 @@ | |
| 16 | ||
| 17 | #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) | |
| 18 | ||
| 19 | +#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) | |
| 20 | +#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) | |
| 21 | +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) | |
| 22 | +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) | |
| 23 | +#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) | |
| 24 | + | |
| 25 | #define IMX6Q_GPR9_TZASC2_BYP BIT(1) | |
| 26 | #define IMX6Q_GPR9_TZASC1_BYP BIT(0) | |
| 27 | ||
| 28 | @@ -273,7 +279,9 @@ | |
| 29 | #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) | |
| 30 | #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) | |
| 31 | #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) | |
| 32 | +#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) | |
| 33 | #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) | |
| 34 | +#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) | |
| 35 | ||
| 36 | #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) | |
| 37 | #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |