src/patches/kernel/wandboard/imx/0008-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch

   1 From 371863a788db77e6092d69df17d8884cb0d94270 Mon Sep 17 00:00:00 2001
   2 From: Richard Zhu <r65037@freescale.com>
   3 Date: Wed, 24 Jul 2013 06:15:28 +0000
   4 Subject: [PATCH 1/2] ARM: imx6q: update the sata bits definitions of gpr13
   5
   6 Replace the SATA_PHY_# by the more readable definitons.
   7
   8 tj: Being routed through libata branch to enable implementation of
   9     ahci_imx.
  10
  11 Signed-off-by: Richard Zhu <r65037@freescale.com>
  12 Acked-by: Shawn Guo <shawn.guo@linaro.org>
  13 Signed-off-by: Tejun Heo <tj@kernel.org>
  14 ---
  15  include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |  121 +++++++++++++++++++--------
  16  1 file changed, 84 insertions(+), 37 deletions(-)
  17
  18 diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
  19 index b1521e8..b6bdcd6 100644
  20 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
  21 +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
  22 @@ -279,41 +279,88 @@
  23  #define IMX6Q_GPR13_CAN2_STOP_REQ              BIT(29)
  24  #define IMX6Q_GPR13_CAN1_STOP_REQ              BIT(28)
  25  #define IMX6Q_GPR13_ENET_STOP_REQ              BIT(27)
  26 -#define IMX6Q_GPR13_SATA_PHY_8_MASK            (0x7 << 24)
  27 -#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB          (0x0 << 24)
  28 -#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB          (0x1 << 24)
  29 -#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB          (0x2 << 24)
  30 -#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB          (0x3 << 24)
  31 -#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB          (0x4 << 24)
  32 -#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB          (0x5 << 24)
  33 -#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB          (0x6 << 24)
  34 -#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB          (0x7 << 24)
  35 -#define IMX6Q_GPR13_SATA_PHY_7_MASK            (0x1f << 19)
  36 -#define IMX6Q_GPR13_SATA_PHY_7_SATA1I          (0x10 << 19)
  37 -#define IMX6Q_GPR13_SATA_PHY_7_SATA1M          (0x10 << 19)
  38 -#define IMX6Q_GPR13_SATA_PHY_7_SATA1X          (0x1a << 19)
  39 -#define IMX6Q_GPR13_SATA_PHY_7_SATA2I          (0x12 << 19)
  40 -#define IMX6Q_GPR13_SATA_PHY_7_SATA2M          (0x12 << 19)
  41 -#define IMX6Q_GPR13_SATA_PHY_7_SATA2X          (0x1a << 19)
  42 -#define IMX6Q_GPR13_SATA_PHY_6_MASK            (0x7 << 16)
  43 -#define IMX6Q_GPR13_SATA_SPEED_MASK            BIT(15)
  44 -#define IMX6Q_GPR13_SATA_SPEED_1P5G            0x0
  45 -#define IMX6Q_GPR13_SATA_SPEED_3P0G            BIT(15)
  46 -#define IMX6Q_GPR13_SATA_PHY_5                 BIT(14)
  47 -#define IMX6Q_GPR13_SATA_PHY_4_MASK            (0x7 << 11)
  48 -#define IMX6Q_GPR13_SATA_PHY_4_16_16           (0x0 << 11)
  49 -#define IMX6Q_GPR13_SATA_PHY_4_14_16           (0x1 << 11)
  50 -#define IMX6Q_GPR13_SATA_PHY_4_12_16           (0x2 << 11)
  51 -#define IMX6Q_GPR13_SATA_PHY_4_10_16           (0x3 << 11)
  52 -#define IMX6Q_GPR13_SATA_PHY_4_9_16            (0x4 << 11)
  53 -#define IMX6Q_GPR13_SATA_PHY_4_8_16            (0x5 << 11)
  54 -#define IMX6Q_GPR13_SATA_PHY_3_MASK            (0xf << 7)
  55 -#define IMX6Q_GPR13_SATA_PHY_3_OFF             0x7
  56 -#define IMX6Q_GPR13_SATA_PHY_2_MASK            (0x1f << 2)
  57 -#define IMX6Q_GPR13_SATA_PHY_2_OFF             0x2
  58 -#define IMX6Q_GPR13_SATA_PHY_1_MASK            (0x3 << 0)
  59 -#define IMX6Q_GPR13_SATA_PHY_1_FAST            (0x0 << 0)
  60 -#define IMX6Q_GPR13_SATA_PHY_1_MED             (0x1 << 0)
  61 -#define IMX6Q_GPR13_SATA_PHY_1_SLOW            (0x2 << 0)
  62 -
  63 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK                (0x7 << 24)
  64 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB      (0x0 << 24)
  65 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB      (0x1 << 24)
  66 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB      (0x2 << 24)
  67 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB      (0x3 << 24)
  68 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB      (0x4 << 24)
  69 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB      (0x5 << 24)
  70 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB      (0x6 << 24)
  71 +#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB      (0x7 << 24)
  72 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK       (0x1f << 19)
  73 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I     (0x10 << 19)
  74 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M     (0x10 << 19)
  75 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X     (0x1a << 19)
  76 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I     (0x12 << 19)
  77 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M     (0x12 << 19)
  78 +#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X     (0x1a << 19)
  79 +#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK     (0x7 << 16)
  80 +#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F    (0x0 << 16)
  81 +#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F    (0x1 << 16)
  82 +#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F    (0x2 << 16)
  83 +#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F    (0x3 << 16)
  84 +#define IMX6Q_GPR13_SATA_SPD_MODE_MASK         BIT(15)
  85 +#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G         0x0
  86 +#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G         BIT(15)
  87 +#define IMX6Q_GPR13_SATA_MPLL_SS_EN            BIT(14)
  88 +#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK         (0x7 << 11)
  89 +#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16                (0x0 << 11)
  90 +#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16                (0x1 << 11)
  91 +#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16                (0x2 << 11)
  92 +#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16                (0x3 << 11)
  93 +#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16         (0x4 << 11)
  94 +#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16         (0x5 << 11)
  95 +#define IMX6Q_GPR13_SATA_TX_BOOST_MASK         (0xf << 7)
  96 +#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB      (0x0 << 7)
  97 +#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB      (0x1 << 7)
  98 +#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB      (0x2 << 7)
  99 +#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB      (0x3 << 7)
 100 +#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB      (0x4 << 7)
 101 +#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB      (0x5 << 7)
 102 +#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB      (0x6 << 7)
 103 +#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB      (0x7 << 7)
 104 +#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB      (0x8 << 7)
 105 +#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB      (0x9 << 7)
 106 +#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB      (0xa << 7)
 107 +#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB      (0xb << 7)
 108 +#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB      (0xc << 7)
 109 +#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB      (0xd << 7)
 110 +#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB      (0xe << 7)
 111 +#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB      (0xf << 7)
 112 +#define IMX6Q_GPR13_SATA_TX_LVL_MASK           (0x1f << 2)
 113 +#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V                (0x00 << 2)
 114 +#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V                (0x01 << 2)
 115 +#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V                (0x02 << 2)
 116 +#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V                (0x03 << 2)
 117 +#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V                (0x04 << 2)
 118 +#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V                (0x05 << 2)
 119 +#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V                (0x06 << 2)
 120 +#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V                (0x07 << 2)
 121 +#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V                (0x08 << 2)
 122 +#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V                (0x09 << 2)
 123 +#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V                (0x0a << 2)
 124 +#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V                (0x0b << 2)
 125 +#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V                (0x0c << 2)
 126 +#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V                (0x0d << 2)
 127 +#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V                (0x0e << 2)
 128 +#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V                (0x0f << 2)
 129 +#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V                (0x10 << 2)
 130 +#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V                (0x11 << 2)
 131 +#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V                (0x12 << 2)
 132 +#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V                (0x13 << 2)
 133 +#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V                (0x14 << 2)
 134 +#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V                (0x15 << 2)
 135 +#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V                (0x16 << 2)
 136 +#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V                (0x17 << 2)
 137 +#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V                (0x18 << 2)
 138 +#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V                (0x19 << 2)
 139 +#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V                (0x1a << 2)
 140 +#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V                (0x1b << 2)
 141 +#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V                (0x1c << 2)
 142 +#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V                (0x1d << 2)
 143 +#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V                (0x1e << 2)
 144 +#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V                (0x1f << 2)
 145 +#define IMX6Q_GPR13_SATA_MPLL_CLK_EN           BIT(1)
 146 +#define IMX6Q_GPR13_SATA_TX_EDGE_RATE          BIT(0)
 147  #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
 148 --
 149 1.7.10.4
 150