[people/arne_f/kernel.git] / arch / arm / boot / dts / dra7.dtsi

/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>

#include "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "ti,dra7xx";
	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;

			operating-points = <
				/* kHz    uV */
				1000000	1060000
				1176000	1160000
				>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the SOC interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		prm: prm@4ae06000 {
			compatible = "ti,dra7-prm";
			reg = <0x4ae06000 0x3000>;

			prm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prm_clockdomains: clockdomains {
			};
		};

		cm_core_aon: cm_core_aon@4a005000 {
			compatible = "ti,dra7-cm-core-aon";
			reg = <0x4a005000 0x2000>;

			cm_core_aon_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cm_core_aon_clockdomains: clockdomains {
			};
		};

		cm_core: cm_core@4a008000 {
			compatible = "ti,dra7-cm-core";
			reg = <0x4a008000 0x3000>;

			cm_core_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cm_core_clockdomains: clockdomains {
			};
		};

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		dra7_pmx_core: pinmux@4a003400 {
			compatible = "pinctrl-single";
			reg = <0x4a003400 0x0464>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x3fffffff>;
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
                        status = "disabled";
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart7: serial@48420000 {
			compatible = "ti,omap4-uart";
			reg = <0x48420000 0x100>;
			ti,hwmods = "uart7";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart8: serial@48422000 {
			compatible = "ti,omap4-uart";
			reg = <0x48422000 0x100>;
			ti,hwmods = "uart8";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart9: serial@48424000 {
			compatible = "ti,omap4-uart";
			reg = <0x48424000 0x100>;
			ti,hwmods = "uart9";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		uart10: serial@4ae2b000 {
			compatible = "ti,omap4-uart";
			reg = <0x4ae2b000 0x100>;
			ti,hwmods = "uart10";
			clock-frequency = <48000000>;
			status = "disabled";
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer4";
		};

		timer5: timer@48820000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48820000 0x80>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@48822000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48822000 0x80>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@48824000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48824000 0x80>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@48826000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48826000 0x80>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
		};

		timer10: timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
		};

		timer11: timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		timer13: timer@48828000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48828000 0x80>;
			ti,hwmods = "timer13";
			status = "disabled";
		};

		timer14: timer@4882a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882a000 0x80>;
			ti,hwmods = "timer14";
			status = "disabled";
		};

		timer15: timer@4882c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882c000 0x80>;
			ti,hwmods = "timer15";
			status = "disabled";
		};

		timer16: timer@4882e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882e000 0x80>;
			ti,hwmods = "timer16";
			status = "disabled";
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
			status = "disabled";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
			status = "disabled";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
			status = "disabled";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
			status = "disabled";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
			status = "disabled";
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
			status = "disabled";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
			status = "disabled";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
			status = "disabled";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
			status = "disabled";
		};
	};
};

/include/ "dra7xx-clocks.dtsi"
Commit	Line	Data
6e58b8f1 S	1	/*
	2	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11	#include <dt-bindings/pinctrl/dra.h>
	12
	13	#include "skeleton.dtsi"
	14
	15	/ {
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
	19	compatible = "ti,dra7xx";
	20	interrupt-parent = <&gic>;
	21
	22	aliases {
20b80942 NM	23	i2c0 = &i2c1;
	24	i2c1 = &i2c2;
	25	i2c2 = &i2c3;
	26	i2c3 = &i2c4;
	27	i2c4 = &i2c5;
6e58b8f1 S	28	serial0 = &uart1;
	29	serial1 = &uart2;
	30	serial2 = &uart3;
	31	serial3 = &uart4;
	32	serial4 = &uart5;
	33	serial5 = &uart6;
	34	};
	35
	36	cpus {
	37	#address-cells = <1>;
	38	#size-cells = <0>;
	39
22f1e7ef	40	cpu0: cpu@0 {
6e58b8f1 S	41	device_type = "cpu";
	42	compatible = "arm,cortex-a15";
	43	reg = <0>;
620c5168 K	44
	45	operating-points = <
	46	/* kHz uV */
	47	1000000 1060000
	48	1176000 1160000
	49	>;
6e58b8f1 S	50	};
	51	cpu@1 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a15";
	54	reg = <1>;
	55	};
	56	};
	57
	58	timer {
	59	compatible = "arm,armv7-timer";
	60	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	61	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	62	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	63	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	64	};
	65
	66	gic: interrupt-controller@48211000 {
	67	compatible = "arm,cortex-a15-gic";
	68	interrupt-controller;
	69	#interrupt-cells = <3>;
	70	reg = <0x48211000 0x1000>,
	71	<0x48212000 0x1000>,
	72	<0x48214000 0x2000>,
	73	<0x48216000 0x2000>;
	74	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	75	};
	76
	77	/*
	78	* The soc node represents the soc top level view. It is uses for IPs
	79	* that are not memory mapped in the MPU view or for the MPU itself.
	80	*/
	81	soc {
	82	compatible = "ti,omap-infra";
	83	mpu {
	84	compatible = "ti,omap5-mpu";
	85	ti,hwmods = "mpu";
	86	};
	87	};
	88
	89	/*
	90	* XXX: Use a flat representation of the SOC interconnect.
	91	* The real OMAP interconnect network is quite complex.
	92	* Since that will not bring real advantage to represent that in DT for
	93	* the moment, just use a fake OCP bus entry to represent the whole bus
	94	* hierarchy.
	95	*/
	96	ocp {
	97	compatible = "ti,omap4-l3-noc", "simple-bus";
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	ranges;
	101	ti,hwmods = "l3_main_1", "l3_main_2";
	102	reg = <0x44000000 0x2000>,
	103	<0x44800000 0x3000>;
	104	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	106
ee6c7507 TK	107	prm: prm@4ae06000 {
	108	compatible = "ti,dra7-prm";
	109	reg = <0x4ae06000 0x3000>;
	110
	111	prm_clocks: clocks {
	112	#address-cells = <1>;
	113	#size-cells = <0>;
	114	};
	115
	116	prm_clockdomains: clockdomains {
	117	};
	118	};
	119
	120	cm_core_aon: cm_core_aon@4a005000 {
	121	compatible = "ti,dra7-cm-core-aon";
	122	reg = <0x4a005000 0x2000>;
	123
	124	cm_core_aon_clocks: clocks {
	125	#address-cells = <1>;
	126	#size-cells = <0>;
	127	};
	128
	129	cm_core_aon_clockdomains: clockdomains {
	130	};
	131	};
	132
	133	cm_core: cm_core@4a008000 {
	134	compatible = "ti,dra7-cm-core";
	135	reg = <0x4a008000 0x3000>;
	136
	137	cm_core_clocks: clocks {
	138	#address-cells = <1>;
	139	#size-cells = <0>;
	140	};
	141
	142	cm_core_clockdomains: clockdomains {
	143	};
	144	};
	145
6e58b8f1 S	146	counter32k: counter@4ae04000 {
	147	compatible = "ti,omap-counter32k";
	148	reg = <0x4ae04000 0x40>;
	149	ti,hwmods = "counter_32k";
	150	};
	151
	152	dra7_pmx_core: pinmux@4a003400 {
	153	compatible = "pinctrl-single";
	154	reg = <0x4a003400 0x0464>;
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	pinctrl-single,register-width = <32>;
	158	pinctrl-single,function-mask = <0x3fffffff>;
	159	};
	160
	161	sdma: dma-controller@4a056000 {
	162	compatible = "ti,omap4430-sdma";
	163	reg = <0x4a056000 0x1000>;
	164	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	165	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	166	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	167	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	168	#dma-cells = <1>;
	169	#dma-channels = <32>;
	170	#dma-requests = <127>;
	171	};
	172
	173	gpio1: gpio@4ae10000 {
	174	compatible = "ti,omap4-gpio";
	175	reg = <0x4ae10000 0x200>;
	176	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	177	ti,hwmods = "gpio1";
	178	gpio-controller;
	179	#gpio-cells = <2>;
	180	interrupt-controller;
e50b78c6	181	#interrupt-cells = <2>;
6e58b8f1 S	182	};
	183
	184	gpio2: gpio@48055000 {
	185	compatible = "ti,omap4-gpio";
	186	reg = <0x48055000 0x200>;
	187	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	188	ti,hwmods = "gpio2";
	189	gpio-controller;
	190	#gpio-cells = <2>;
	191	interrupt-controller;
e50b78c6	192	#interrupt-cells = <2>;
6e58b8f1 S	193	};
	194
	195	gpio3: gpio@48057000 {
	196	compatible = "ti,omap4-gpio";
	197	reg = <0x48057000 0x200>;
	198	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	199	ti,hwmods = "gpio3";
	200	gpio-controller;
	201	#gpio-cells = <2>;
	202	interrupt-controller;
e50b78c6	203	#interrupt-cells = <2>;
6e58b8f1 S	204	};
	205
	206	gpio4: gpio@48059000 {
	207	compatible = "ti,omap4-gpio";
	208	reg = <0x48059000 0x200>;
	209	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	210	ti,hwmods = "gpio4";
	211	gpio-controller;
	212	#gpio-cells = <2>;
	213	interrupt-controller;
e50b78c6	214	#interrupt-cells = <2>;
6e58b8f1 S	215	};
	216
	217	gpio5: gpio@4805b000 {
	218	compatible = "ti,omap4-gpio";
	219	reg = <0x4805b000 0x200>;
	220	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	221	ti,hwmods = "gpio5";
	222	gpio-controller;
	223	#gpio-cells = <2>;
	224	interrupt-controller;
e50b78c6	225	#interrupt-cells = <2>;
6e58b8f1 S	226	};
	227
	228	gpio6: gpio@4805d000 {
	229	compatible = "ti,omap4-gpio";
	230	reg = <0x4805d000 0x200>;
	231	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	232	ti,hwmods = "gpio6";
	233	gpio-controller;
	234	#gpio-cells = <2>;
	235	interrupt-controller;
e50b78c6	236	#interrupt-cells = <2>;
6e58b8f1 S	237	};
	238
	239	gpio7: gpio@48051000 {
	240	compatible = "ti,omap4-gpio";
	241	reg = <0x48051000 0x200>;
	242	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	243	ti,hwmods = "gpio7";
	244	gpio-controller;
	245	#gpio-cells = <2>;
	246	interrupt-controller;
e50b78c6	247	#interrupt-cells = <2>;
6e58b8f1 S	248	};
	249
	250	gpio8: gpio@48053000 {
	251	compatible = "ti,omap4-gpio";
	252	reg = <0x48053000 0x200>;
	253	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	254	ti,hwmods = "gpio8";
	255	gpio-controller;
	256	#gpio-cells = <2>;
	257	interrupt-controller;
e50b78c6	258	#interrupt-cells = <2>;
6e58b8f1 S	259	};
	260
	261	uart1: serial@4806a000 {
	262	compatible = "ti,omap4-uart";
	263	reg = <0x4806a000 0x100>;
	264	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	265	ti,hwmods = "uart1";
	266	clock-frequency = <48000000>;
	267	status = "disabled";
	268	};
	269
	270	uart2: serial@4806c000 {
	271	compatible = "ti,omap4-uart";
	272	reg = <0x4806c000 0x100>;
	273	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	274	ti,hwmods = "uart2";
	275	clock-frequency = <48000000>;
	276	status = "disabled";
	277	};
	278
	279	uart3: serial@48020000 {
	280	compatible = "ti,omap4-uart";
	281	reg = <0x48020000 0x100>;
	282	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	283	ti,hwmods = "uart3";
	284	clock-frequency = <48000000>;
	285	status = "disabled";
	286	};
	287
	288	uart4: serial@4806e000 {
	289	compatible = "ti,omap4-uart";
	290	reg = <0x4806e000 0x100>;
	291	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	292	ti,hwmods = "uart4";
	293	clock-frequency = <48000000>;
	294	status = "disabled";
	295	};
	296
	297	uart5: serial@48066000 {
	298	compatible = "ti,omap4-uart";
	299	reg = <0x48066000 0x100>;
	300	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	301	ti,hwmods = "uart5";
	302	clock-frequency = <48000000>;
	303	status = "disabled";
	304	};
	305
	306	uart6: serial@48068000 {
	307	compatible = "ti,omap4-uart";
	308	reg = <0x48068000 0x100>;
	309	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	310	ti,hwmods = "uart6";
	311	clock-frequency = <48000000>;
	312	status = "disabled";
	313	};
	314
	315	uart7: serial@48420000 {
	316	compatible = "ti,omap4-uart";
	317	reg = <0x48420000 0x100>;
	318	ti,hwmods = "uart7";
	319	clock-frequency = <48000000>;
	320	status = "disabled";
	321	};
	322
323	uart8: serial@48422000 {
324	compatible = "ti,omap4-uart";
325	reg = <0x48422000 0x100>;
326	ti,hwmods = "uart8";
327	clock-frequency = <48000000>;
328	status = "disabled";
329	};
330
331	uart9: serial@48424000 {
332	compatible = "ti,omap4-uart";
333	reg = <0x48424000 0x100>;
334	ti,hwmods = "uart9";
335	clock-frequency = <48000000>;
336	status = "disabled";
337	};
338
339	uart10: serial@4ae2b000 {
340	compatible = "ti,omap4-uart";
341	reg = <0x4ae2b000 0x100>;
342	ti,hwmods = "uart10";
343	clock-frequency = <48000000>;
344	status = "disabled";
345	};
346
347	timer1: timer@4ae18000 {
348	compatible = "ti,omap5430-timer";
349	reg = <0x4ae18000 0x80>;
350	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
351	ti,hwmods = "timer1";
352	ti,timer-alwon;
353	};
354
355	timer2: timer@48032000 {
356	compatible = "ti,omap5430-timer";
357	reg = <0x48032000 0x80>;
358	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
359	ti,hwmods = "timer2";
360	};
361
362	timer3: timer@48034000 {
363	compatible = "ti,omap5430-timer";
364	reg = <0x48034000 0x80>;
365	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
366	ti,hwmods = "timer3";
367	};
368
369	timer4: timer@48036000 {
370	compatible = "ti,omap5430-timer";
371	reg = <0x48036000 0x80>;
372	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
373	ti,hwmods = "timer4";
374	};
375
376	timer5: timer@48820000 {
377	compatible = "ti,omap5430-timer";
378	reg = <0x48820000 0x80>;
379	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
380	ti,hwmods = "timer5";
381	ti,timer-dsp;
382	};
383
384	timer6: timer@48822000 {
385	compatible = "ti,omap5430-timer";
386	reg = <0x48822000 0x80>;
387	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
388	ti,hwmods = "timer6";
389	ti,timer-dsp;
390	ti,timer-pwm;
391	};
392
393	timer7: timer@48824000 {
394	compatible = "ti,omap5430-timer";
395	reg = <0x48824000 0x80>;
396	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
397	ti,hwmods = "timer7";
398	ti,timer-dsp;
399	};
400
401	timer8: timer@48826000 {
402	compatible = "ti,omap5430-timer";
403	reg = <0x48826000 0x80>;
404	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
405	ti,hwmods = "timer8";
406	ti,timer-dsp;
407	ti,timer-pwm;
408	};
409
410	timer9: timer@4803e000 {
411	compatible = "ti,omap5430-timer";
412	reg = <0x4803e000 0x80>;
413	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
414	ti,hwmods = "timer9";
415	};
416
417	timer10: timer@48086000 {
418	compatible = "ti,omap5430-timer";
419	reg = <0x48086000 0x80>;
420	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
421	ti,hwmods = "timer10";
422	};
423
424	timer11: timer@48088000 {
425	compatible = "ti,omap5430-timer";
426	reg = <0x48088000 0x80>;
427	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
428	ti,hwmods = "timer11";
429	ti,timer-pwm;
430	};
431
432	timer13: timer@48828000 {
433	compatible = "ti,omap5430-timer";
434	reg = <0x48828000 0x80>;
435	ti,hwmods = "timer13";
436	status = "disabled";
437	};
438
439	timer14: timer@4882a000 {
440	compatible = "ti,omap5430-timer";
441	reg = <0x4882a000 0x80>;
442	ti,hwmods = "timer14";
443	status = "disabled";
444	};
445
446	timer15: timer@4882c000 {
447	compatible = "ti,omap5430-timer";
448	reg = <0x4882c000 0x80>;
449	ti,hwmods = "timer15";
450	status = "disabled";
451	};
452
453	timer16: timer@4882e000 {
454	compatible = "ti,omap5430-timer";
455	reg = <0x4882e000 0x80>;
456	ti,hwmods = "timer16";
457	status = "disabled";
458	};
459
460	wdt2: wdt@4ae14000 {
9feeb8f3	461	compatible = "ti,omap3-wdt";
6e58b8f1 S	462	reg = <0x4ae14000 0x80>;
	463	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	464	ti,hwmods = "wd_timer2";
	465	};
	466
	467	i2c1: i2c@48070000 {
	468	compatible = "ti,omap4-i2c";
	469	reg = <0x48070000 0x100>;
	470	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	471	#address-cells = <1>;
	472	#size-cells = <0>;
	473	ti,hwmods = "i2c1";
	474	status = "disabled";
	475	};
	476
	477	i2c2: i2c@48072000 {
	478	compatible = "ti,omap4-i2c";
	479	reg = <0x48072000 0x100>;
	480	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	481	#address-cells = <1>;
	482	#size-cells = <0>;
	483	ti,hwmods = "i2c2";
	484	status = "disabled";
	485	};
	486
	487	i2c3: i2c@48060000 {
	488	compatible = "ti,omap4-i2c";
	489	reg = <0x48060000 0x100>;
	490	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	491	#address-cells = <1>;
	492	#size-cells = <0>;
	493	ti,hwmods = "i2c3";
	494	status = "disabled";
	495	};
	496
	497	i2c4: i2c@4807a000 {
	498	compatible = "ti,omap4-i2c";
	499	reg = <0x4807a000 0x100>;
	500	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	501	#address-cells = <1>;
	502	#size-cells = <0>;
	503	ti,hwmods = "i2c4";
	504	status = "disabled";
	505	};
	506
	507	i2c5: i2c@4807c000 {
	508	compatible = "ti,omap4-i2c";
	509	reg = <0x4807c000 0x100>;
	510	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	511	#address-cells = <1>;
	512	#size-cells = <0>;
	513	ti,hwmods = "i2c5";
	514	status = "disabled";
	515	};
	516
	517	mmc1: mmc@4809c000 {
	518	compatible = "ti,omap4-hsmmc";
	519	reg = <0x4809c000 0x400>;
	520	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	521	ti,hwmods = "mmc1";
	522	ti,dual-volt;
	523	ti,needs-special-reset;
	524	dmas = <&sdma 61>, <&sdma 62>;
	525	dma-names = "tx", "rx";
526	status = "disabled";
527	};
528
529	mmc2: mmc@480b4000 {
530	compatible = "ti,omap4-hsmmc";
531	reg = <0x480b4000 0x400>;
532	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
533	ti,hwmods = "mmc2";
534	ti,needs-special-reset;
535	dmas = <&sdma 47>, <&sdma 48>;
536	dma-names = "tx", "rx";
537	status = "disabled";
538	};
539
540	mmc3: mmc@480ad000 {
541	compatible = "ti,omap4-hsmmc";
542	reg = <0x480ad000 0x400>;
543	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
544	ti,hwmods = "mmc3";
545	ti,needs-special-reset;
546	dmas = <&sdma 77>, <&sdma 78>;
547	dma-names = "tx", "rx";
548	status = "disabled";
549	};
550
551	mmc4: mmc@480d1000 {
552	compatible = "ti,omap4-hsmmc";
553	reg = <0x480d1000 0x400>;
554	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
555	ti,hwmods = "mmc4";
556	ti,needs-special-reset;
557	dmas = <&sdma 57>, <&sdma 58>;
558	dma-names = "tx", "rx";
559	status = "disabled";
560	};
561
562	mcspi1: spi@48098000 {
563	compatible = "ti,omap4-mcspi";
564	reg = <0x48098000 0x200>;
565	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
566	#address-cells = <1>;
567	#size-cells = <0>;
568	ti,hwmods = "mcspi1";
569	ti,spi-num-cs = <4>;
570	dmas = <&sdma 35>,
571	<&sdma 36>,
572	<&sdma 37>,
573	<&sdma 38>,
574	<&sdma 39>,
575	<&sdma 40>,
576	<&sdma 41>,
577	<&sdma 42>;
578	dma-names = "tx0", "rx0", "tx1", "rx1",
579	"tx2", "rx2", "tx3", "rx3";
580	status = "disabled";
581	};
582
583	mcspi2: spi@4809a000 {
584	compatible = "ti,omap4-mcspi";
585	reg = <0x4809a000 0x200>;
586	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
587	#address-cells = <1>;
588	#size-cells = <0>;
589	ti,hwmods = "mcspi2";
590	ti,spi-num-cs = <2>;
591	dmas = <&sdma 43>,
592	<&sdma 44>,
593	<&sdma 45>,
594	<&sdma 46>;
595	dma-names = "tx0", "rx0", "tx1", "rx1";
596	status = "disabled";
597	};
598
599	mcspi3: spi@480b8000 {
600	compatible = "ti,omap4-mcspi";
601	reg = <0x480b8000 0x200>;
602	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
603	#address-cells = <1>;
604	#size-cells = <0>;
605	ti,hwmods = "mcspi3";
606	ti,spi-num-cs = <2>;
607	dmas = <&sdma 15>, <&sdma 16>;
608	dma-names = "tx0", "rx0";
609	status = "disabled";
610	};
611
612	mcspi4: spi@480ba000 {
613	compatible = "ti,omap4-mcspi";
614	reg = <0x480ba000 0x200>;
615	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
616	#address-cells = <1>;
617	#size-cells = <0>;
618	ti,hwmods = "mcspi4";
619	ti,spi-num-cs = <1>;
620	dmas = <&sdma 70>, <&sdma 71>;
621	dma-names = "tx0", "rx0";
622	status = "disabled";
623	};
624	};
625	};
ee6c7507 TK	626
ee6c7507 TK	627	/include/ "dra7xx-clocks.dtsi"