]>
Commit | Line | Data |
---|---|---|
0f7238a1 TF |
1 | /* |
2 | * Samsung's Exynos4x12 SoCs device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 | |
8 | * based board files can include this file and provide values for board specfic | |
9 | * bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional | |
13 | * nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
3799279f PV |
20 | #include "exynos4.dtsi" |
21 | #include "exynos4x12-pinctrl.dtsi" | |
0f7238a1 TF |
22 | |
23 | / { | |
64a57434 TF |
24 | aliases { |
25 | pinctrl0 = &pinctrl_0; | |
26 | pinctrl1 = &pinctrl_1; | |
27 | pinctrl2 = &pinctrl_2; | |
28 | pinctrl3 = &pinctrl_3; | |
582435b3 SN |
29 | fimc-lite0 = &fimc_lite_0; |
30 | fimc-lite1 = &fimc_lite_1; | |
56d52bfb | 31 | mshc0 = &mshc_0; |
64a57434 TF |
32 | }; |
33 | ||
2ab9f3c0 SN |
34 | pd_isp: isp-power-domain@10023CA0 { |
35 | compatible = "samsung,exynos4210-pd"; | |
36 | reg = <0x10023CA0 0x20>; | |
64a57434 TF |
37 | }; |
38 | ||
1fd9a015 | 39 | clock: clock-controller@10030000 { |
d8bafc87 TA |
40 | compatible = "samsung,exynos4412-clock"; |
41 | reg = <0x10030000 0x20000>; | |
42 | #clock-cells = <1>; | |
43 | }; | |
44 | ||
39e596f0 TF |
45 | mct@10050000 { |
46 | compatible = "samsung,exynos4412-mct"; | |
47 | reg = <0x10050000 0x800>; | |
48 | interrupt-parent = <&mct_map>; | |
84ee1c15 | 49 | interrupts = <0>, <1>, <2>, <3>, <4>; |
39e596f0 TF |
50 | clocks = <&clock 3>, <&clock 344>; |
51 | clock-names = "fin_pll", "mct"; | |
52 | ||
53 | mct_map: mct-map { | |
84ee1c15 | 54 | #interrupt-cells = <1>; |
39e596f0 TF |
55 | #address-cells = <0>; |
56 | #size-cells = <0>; | |
84ee1c15 TF |
57 | interrupt-map = <0 &gic 0 57 0>, |
58 | <1 &combiner 12 5>, | |
59 | <2 &combiner 12 6>, | |
60 | <3 &combiner 12 7>, | |
61 | <4 &gic 1 12 0>; | |
39e596f0 TF |
62 | }; |
63 | }; | |
64 | ||
64a57434 | 65 | pinctrl_0: pinctrl@11400000 { |
b533c868 | 66 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
67 | reg = <0x11400000 0x1000>; |
68 | interrupts = <0 47 0>; | |
69 | }; | |
70 | ||
71 | pinctrl_1: pinctrl@11000000 { | |
b533c868 | 72 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
73 | reg = <0x11000000 0x1000>; |
74 | interrupts = <0 46 0>; | |
75 | ||
76 | wakup_eint: wakeup-interrupt-controller { | |
77 | compatible = "samsung,exynos4210-wakeup-eint"; | |
78 | interrupt-parent = <&gic>; | |
79 | interrupts = <0 32 0>; | |
80 | }; | |
81 | }; | |
82 | ||
83 | pinctrl_2: pinctrl@03860000 { | |
b533c868 | 84 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
85 | reg = <0x03860000 0x1000>; |
86 | interrupt-parent = <&combiner>; | |
87 | interrupts = <10 0>; | |
88 | }; | |
89 | ||
90 | pinctrl_3: pinctrl@106E0000 { | |
b533c868 | 91 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
92 | reg = <0x106E0000 0x1000>; |
93 | interrupts = <0 72 0>; | |
94 | }; | |
3a0d48f6 SK |
95 | |
96 | g2d@10800000 { | |
97 | compatible = "samsung,exynos4212-g2d"; | |
98 | reg = <0x10800000 0x1000>; | |
99 | interrupts = <0 89 0>; | |
cfc5652d SK |
100 | clocks = <&clock 177>, <&clock 277>; |
101 | clock-names = "sclk_fimg2d", "fimg2d"; | |
3a0d48f6 SK |
102 | status = "disabled"; |
103 | }; | |
582435b3 SN |
104 | |
105 | camera { | |
106 | clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; | |
107 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; | |
108 | ||
109 | fimc_0: fimc@11800000 { | |
110 | compatible = "samsung,exynos4212-fimc"; | |
111 | samsung,pix-limits = <4224 8192 1920 4224>; | |
112 | samsung,mainscaler-ext; | |
113 | samsung,isp-wb; | |
114 | samsung,cam-if; | |
115 | }; | |
116 | ||
117 | fimc_1: fimc@11810000 { | |
118 | compatible = "samsung,exynos4212-fimc"; | |
119 | samsung,pix-limits = <4224 8192 1920 4224>; | |
120 | samsung,mainscaler-ext; | |
121 | samsung,isp-wb; | |
122 | samsung,cam-if; | |
123 | }; | |
124 | ||
125 | fimc_2: fimc@11820000 { | |
126 | compatible = "samsung,exynos4212-fimc"; | |
127 | samsung,pix-limits = <4224 8192 1920 4224>; | |
128 | samsung,mainscaler-ext; | |
129 | samsung,isp-wb; | |
130 | samsung,lcd-wb; | |
131 | samsung,cam-if; | |
132 | }; | |
133 | ||
134 | fimc_3: fimc@11830000 { | |
135 | compatible = "samsung,exynos4212-fimc"; | |
136 | samsung,pix-limits = <1920 8192 1366 1920>; | |
137 | samsung,rotators = <0>; | |
138 | samsung,mainscaler-ext; | |
139 | samsung,isp-wb; | |
140 | samsung,lcd-wb; | |
141 | }; | |
142 | ||
143 | fimc_lite_0: fimc-lite@12390000 { | |
144 | compatible = "samsung,exynos4212-fimc-lite"; | |
145 | reg = <0x12390000 0x1000>; | |
146 | interrupts = <0 105 0>; | |
147 | samsung,power-domain = <&pd_isp>; | |
148 | clocks = <&clock 353>; | |
149 | clock-names = "flite"; | |
150 | status = "disabled"; | |
151 | }; | |
152 | ||
153 | fimc_lite_1: fimc-lite@123A0000 { | |
154 | compatible = "samsung,exynos4212-fimc-lite"; | |
155 | reg = <0x123A0000 0x1000>; | |
156 | interrupts = <0 106 0>; | |
157 | samsung,power-domain = <&pd_isp>; | |
158 | clocks = <&clock 354>; | |
159 | clock-names = "flite"; | |
160 | status = "disabled"; | |
161 | }; | |
162 | ||
163 | fimc_is: fimc-is@12000000 { | |
164 | compatible = "samsung,exynos4212-fimc-is", "simple-bus"; | |
165 | reg = <0x12000000 0x260000>; | |
166 | interrupts = <0 90 0>, <0 95 0>; | |
167 | samsung,power-domain = <&pd_isp>; | |
168 | clocks = <&clock 353>, <&clock 354>, <&clock 355>, | |
169 | <&clock 356>, <&clock 17>, <&clock 357>, | |
170 | <&clock 358>, <&clock 359>, <&clock 360>, | |
171 | <&clock 450>,<&clock 451>, <&clock 452>, | |
172 | <&clock 453>, <&clock 176>, <&clock 13>, | |
173 | <&clock 454>, <&clock 395>, <&clock 455>; | |
174 | clock-names = "lite0", "lite1", "ppmuispx", | |
175 | "ppmuispmx", "mpll", "isp", | |
176 | "drc", "fd", "mcuisp", | |
177 | "ispdiv0", "ispdiv1", "mcuispdiv0", | |
178 | "mcuispdiv1", "uart", "aclk200", | |
179 | "div_aclk200", "aclk400mcuisp", | |
180 | "div_aclk400mcuisp"; | |
181 | #address-cells = <1>; | |
182 | #size-cells = <1>; | |
183 | ranges; | |
184 | status = "disabled"; | |
185 | ||
186 | pmu { | |
187 | reg = <0x10020000 0x3000>; | |
188 | }; | |
189 | ||
190 | i2c1_isp: i2c-isp@12140000 { | |
191 | compatible = "samsung,exynos4212-i2c-isp"; | |
192 | reg = <0x12140000 0x100>; | |
193 | clocks = <&clock 370>; | |
194 | clock-names = "i2c_isp"; | |
195 | #address-cells = <1>; | |
196 | #size-cells = <0>; | |
197 | }; | |
198 | }; | |
199 | }; | |
56d52bfb TF |
200 | |
201 | mshc_0: mmc@12550000 { | |
202 | compatible = "samsung,exynos4412-dw-mshc"; | |
203 | reg = <0x12550000 0x1000>; | |
204 | interrupts = <0 77 0>; | |
205 | #address-cells = <1>; | |
206 | #size-cells = <0>; | |
207 | fifo-depth = <0x80>; | |
208 | clocks = <&clock 301>, <&clock 149>; | |
209 | clock-names = "biu", "ciu"; | |
210 | status = "disabled"; | |
211 | }; | |
0f7238a1 | 212 | }; |