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sun7i: dts: add bananapro.
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CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
bc3875f1
LW		 12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
bc3a59c1
DA		 14
15/ {
16 interrupt-parent = <&icoll>;
17
ce4c6f9b 18 aliases {
6bf6eb09
FE		 19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
ce4c6f9b
SG		 21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
530f1d41
SG		 26 saif0 = &saif0;
27 saif1 = &saif1;
80d969e4
FE		 28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
6bf6eb09
FE		 33 spi0 = &ssp1;
34 spi1 = &ssp2;
ce4c6f9b
SG		 35 };
36
bc3a59c1 37 cpus {
7925e89f
LP		 38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
bc3a59c1
DA		 44 };
45 };
46
47 apb@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x80000>;
52 ranges;
53
54 apbh@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x3c900>;
59 ranges;
60
61 icoll: interrupt-controller@80000000 {
83a84efc 62 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
66 };
67
296f8cd3 68 hsadc: hsadc@80002000 {
0f06cde7 69 reg = <0x80002000 0x2000>;
7f2b9288 70 interrupts = <13>;
f30fb03d
SG		 71 dmas = <&dma_apbh 12>;
72 dma-names = "rx";
bc3a59c1
DA		 73 status = "disabled";
74 };
75
f30fb03d 76 dma_apbh: dma-apbh@80004000 {
84f3570a 77 compatible = "fsl,imx28-dma-apbh";
0f06cde7 78 reg = <0x80004000 0x2000>;
f30fb03d
SG		 79 interrupts = <82 83 84 85
80 88 88 88 88
81 88 88 88 88
82 87 86 0 0>;
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
87 #dma-cells = <1>;
88 dma-channels = <16>;
b598b9f3 89 clocks = <&clks 25>;
bc3a59c1
DA		 90 };
91
296f8cd3 92 perfmon: perfmon@80006000 {
0f06cde7 93 reg = <0x80006000 0x800>;
bc3a59c1
DA		 94 interrupts = <27>;
95 status = "disabled";
96 };
97
296f8cd3 98 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
101 #size-cells = <1>;
0f06cde7 102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 103 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 104 interrupts = <41>;
105 interrupt-names = "bch";
b598b9f3 106 clocks = <&clks 50>;
b6442559 107 clock-names = "gpmi_io";
f30fb03d
SG		 108 dmas = <&dma_apbh 4>;
109 dma-names = "rx-tx";
bc3a59c1
DA		 110 status = "disabled";
111 };
112
113 ssp0: ssp@80010000 {
41bf5706
MR		 114 #address-cells = <1>;
115 #size-cells = <0>;
0f06cde7 116 reg = <0x80010000 0x2000>;
7f2b9288 117 interrupts = <96>;
b598b9f3 118 clocks = <&clks 46>;
f30fb03d
SG		 119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx";
bc3a59c1
DA		 121 status = "disabled";
122 };
123
124 ssp1: ssp@80012000 {
41bf5706
MR		 125 #address-cells = <1>;
126 #size-cells = <0>;
0f06cde7 127 reg = <0x80012000 0x2000>;
7f2b9288 128 interrupts = <97>;
b598b9f3 129 clocks = <&clks 47>;
f30fb03d
SG		 130 dmas = <&dma_apbh 1>;
131 dma-names = "rx-tx";
bc3a59c1
DA		 132 status = "disabled";
133 };
134
135 ssp2: ssp@80014000 {
41bf5706
MR		 136 #address-cells = <1>;
137 #size-cells = <0>;
0f06cde7 138 reg = <0x80014000 0x2000>;
7f2b9288 139 interrupts = <98>;
b598b9f3 140 clocks = <&clks 48>;
f30fb03d
SG		 141 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx";
bc3a59c1
DA		 143 status = "disabled";
144 };
145
146 ssp3: ssp@80016000 {
41bf5706
MR		 147 #address-cells = <1>;
148 #size-cells = <0>;
0f06cde7 149 reg = <0x80016000 0x2000>;
7f2b9288 150 interrupts = <99>;
b598b9f3 151 clocks = <&clks 49>;
f30fb03d
SG		 152 dmas = <&dma_apbh 3>;
153 dma-names = "rx-tx";
bc3a59c1
DA		 154 status = "disabled";
155 };
156
296f8cd3 157 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 158 #address-cells = <1>;
159 #size-cells = <0>;
ce4c6f9b 160 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 161 reg = <0x80018000 0x2000>;
bc3a59c1 162
ce4c6f9b
SG		 163 gpio0: gpio@0 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <127>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio1: gpio@1 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <126>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 gpio2: gpio@2 {
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupts = <125>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio3: gpio@3 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192 interrupts = <124>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpio4: gpio@4 {
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
201 interrupts = <123>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
bc3a59c1
DA		 208 duart_pins_a: duart@0 {
209 reg = <0>;
f14da767 210 fsl,pinmux-ids = <
bc3875f1
LW		 211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
f14da767 213 >;
4191c340
LW		 214 fsl,drive-strength = <MXS_DRIVE_4mA>;
215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
216 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 217 };
218
8385e7c1
MR		 219 duart_pins_b: duart@1 {
220 reg = <1>;
f14da767 221 fsl,pinmux-ids = <
bc3875f1
LW		 222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 224 >;
4191c340
LW		 225 fsl,drive-strength = <MXS_DRIVE_4mA>;
226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
227 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 228 };
229
e1a4d18f
SG		 230 duart_4pins_a: duart-4pins@0 {
231 reg = <0>;
232 fsl,pinmux-ids = <
bc3875f1
LW		 233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 237 >;
4191c340
LW		 238 fsl,drive-strength = <MXS_DRIVE_4mA>;
239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
240 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 241 };
242
7a8e5149
HS		 243 gpmi_pins_a: gpmi-nand@0 {
244 reg = <0>;
f14da767 245 fsl,pinmux-ids = <
bc3875f1
LW		 246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 261 >;
4191c340
LW		 262 fsl,drive-strength = <MXS_DRIVE_4mA>;
263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
264 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 265 };
266
267 gpmi_status_cfg: gpmi-status-cfg {
f14da767 268 fsl,pinmux-ids = <
bc3875f1
LW		 269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 272 >;
4191c340 273 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 274 };
275
80d969e4
FE		 276 auart0_pins_a: auart0@0 {
277 reg = <0>;
f14da767 278 fsl,pinmux-ids = <
bc3875f1
LW		 279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 283 >;
4191c340
LW		 284 fsl,drive-strength = <MXS_DRIVE_4mA>;
285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
286 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 287 };
288
289 auart0_2pins_a: auart0-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
bc3875f1
LW		 292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 294 >;
4191c340
LW		 295 fsl,drive-strength = <MXS_DRIVE_4mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 298 };
299
e1a4d18f
SG		 300 auart1_pins_a: auart1@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
bc3875f1
LW		 303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 307 >;
4191c340
LW		 308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 311 };
312
3143bbb4
SG		 313 auart1_2pins_a: auart1-2pins@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
bc3875f1
LW		 316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 318 >;
4191c340
LW		 319 fsl,drive-strength = <MXS_DRIVE_4mA>;
320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
321 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 322 };
323
324 auart2_2pins_a: auart2-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
bc3875f1
LW		 327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 329 >;
4191c340
LW		 330 fsl,drive-strength = <MXS_DRIVE_4mA>;
331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
332 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 333 };
334
f8040cf5
EB		 335 auart2_2pins_b: auart2-2pins@1 {
336 reg = <1>;
337 fsl,pinmux-ids = <
bc3875f1
LW		 338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 340 >;
4191c340
LW		 341 fsl,drive-strength = <MXS_DRIVE_4mA>;
342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
343 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 344 };
345
80d969e4
FE		 346 auart3_pins_a: auart3@0 {
347 reg = <0>;
f14da767 348 fsl,pinmux-ids = <
bc3875f1
LW		 349 MX28_PAD_AUART3_RX__AUART3_RX
350 MX28_PAD_AUART3_TX__AUART3_TX
351 MX28_PAD_AUART3_CTS__AUART3_CTS
352 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 353 >;
4191c340
LW		 354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 357 };
358
3143bbb4
SG		 359 auart3_2pins_a: auart3-2pins@0 {
360 reg = <0>;
361 fsl,pinmux-ids = <
bc3875f1
LW		 362 MX28_PAD_SSP2_MISO__AUART3_RX
363 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 364 >;
4191c340
LW		 365 fsl,drive-strength = <MXS_DRIVE_4mA>;
366 fsl,voltage = <MXS_VOLTAGE_HIGH>;
367 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 368 };
369
4812e746
EB		 370 auart3_2pins_b: auart3-2pins@1 {
371 reg = <1>;
372 fsl,pinmux-ids = <
bc3875f1
LW		 373 MX28_PAD_AUART3_RX__AUART3_RX
374 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 375 >;
4191c340
LW		 376 fsl,drive-strength = <MXS_DRIVE_4mA>;
377 fsl,voltage = <MXS_VOLTAGE_HIGH>;
378 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 379 };
380
33678d12
EB		 381 auart4_2pins_a: auart4@0 {
382 reg = <0>;
383 fsl,pinmux-ids = <
bc3875f1
LW		 384 MX28_PAD_SSP3_SCK__AUART4_TX
385 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 386 >;
4191c340
LW		 387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 390 };
391
bc3a59c1
DA		 392 mac0_pins_a: mac0@0 {
393 reg = <0>;
f14da767 394 fsl,pinmux-ids = <
bc3875f1
LW		 395 MX28_PAD_ENET0_MDC__ENET0_MDC
396 MX28_PAD_ENET0_MDIO__ENET0_MDIO
397 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
398 MX28_PAD_ENET0_RXD0__ENET0_RXD0
399 MX28_PAD_ENET0_RXD1__ENET0_RXD1
400 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
401 MX28_PAD_ENET0_TXD0__ENET0_TXD0
402 MX28_PAD_ENET0_TXD1__ENET0_TXD1
403 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 404 >;
4191c340
LW		 405 fsl,drive-strength = <MXS_DRIVE_8mA>;
406 fsl,voltage = <MXS_VOLTAGE_HIGH>;
407 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 408 };
409
410 mac1_pins_a: mac1@0 {
411 reg = <0>;
f14da767 412 fsl,pinmux-ids = <
bc3875f1
LW		 413 MX28_PAD_ENET0_CRS__ENET1_RX_EN
414 MX28_PAD_ENET0_RXD2__ENET1_RXD0
415 MX28_PAD_ENET0_RXD3__ENET1_RXD1
416 MX28_PAD_ENET0_COL__ENET1_TX_EN
417 MX28_PAD_ENET0_TXD2__ENET1_TXD0
418 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 419 >;
4191c340
LW		 420 fsl,drive-strength = <MXS_DRIVE_8mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 423 };
35d23047
SG		 424
425 mmc0_8bit_pins_a: mmc0-8bit@0 {
426 reg = <0>;
f14da767 427 fsl,pinmux-ids = <
bc3875f1
LW		 428 MX28_PAD_SSP0_DATA0__SSP0_D0
429 MX28_PAD_SSP0_DATA1__SSP0_D1
430 MX28_PAD_SSP0_DATA2__SSP0_D2
431 MX28_PAD_SSP0_DATA3__SSP0_D3
432 MX28_PAD_SSP0_DATA4__SSP0_D4
433 MX28_PAD_SSP0_DATA5__SSP0_D5
434 MX28_PAD_SSP0_DATA6__SSP0_D6
435 MX28_PAD_SSP0_DATA7__SSP0_D7
436 MX28_PAD_SSP0_CMD__SSP0_CMD
437 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
438 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 439 >;
4191c340
LW		 440 fsl,drive-strength = <MXS_DRIVE_8mA>;
441 fsl,voltage = <MXS_VOLTAGE_HIGH>;
442 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 443 };
444
8385e7c1
MR		 445 mmc0_4bit_pins_a: mmc0-4bit@0 {
446 reg = <0>;
f14da767 447 fsl,pinmux-ids = <
bc3875f1
LW		 448 MX28_PAD_SSP0_DATA0__SSP0_D0
449 MX28_PAD_SSP0_DATA1__SSP0_D1
450 MX28_PAD_SSP0_DATA2__SSP0_D2
451 MX28_PAD_SSP0_DATA3__SSP0_D3
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 455 >;
4191c340
LW		 456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 459 };
460
35d23047 461 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 462 fsl,pinmux-ids = <
bc3875f1 463 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 464 >;
4191c340 465 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 466 };
467
468 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 469 fsl,pinmux-ids = <
bc3875f1 470 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 471 >;
4191c340
LW		 472 fsl,drive-strength = <MXS_DRIVE_12mA>;
473 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 474 };
2a96e391 475
5550e8e9
MV		 476 mmc2_4bit_pins_a: mmc2-4bit@0 {
477 reg = <0>;
478 fsl,pinmux-ids = <
479 MX28_PAD_SSP0_DATA4__SSP2_D0
480 MX28_PAD_SSP1_SCK__SSP2_D1
481 MX28_PAD_SSP1_CMD__SSP2_D2
482 MX28_PAD_SSP0_DATA5__SSP2_D3
483 MX28_PAD_SSP0_DATA6__SSP2_CMD
484 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
485 MX28_PAD_SSP0_DATA7__SSP2_SCK
486 >;
487 fsl,drive-strength = <MXS_DRIVE_8mA>;
488 fsl,voltage = <MXS_VOLTAGE_HIGH>;
489 fsl,pull-up = <MXS_PULL_ENABLE>;
490 };
491
492 mmc2_cd_cfg: mmc2-cd-cfg {
493 fsl,pinmux-ids = <
494 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
495 >;
496 fsl,pull-up = <MXS_PULL_DISABLE>;
497 };
498
499 mmc2_sck_cfg: mmc2-sck-cfg {
500 fsl,pinmux-ids = <
501 MX28_PAD_SSP0_DATA7__SSP2_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_12mA>;
504 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 505 };
2a96e391
SG		 506
507 i2c0_pins_a: i2c0@0 {
508 reg = <0>;
f14da767 509 fsl,pinmux-ids = <
bc3875f1
LW		 510 MX28_PAD_I2C0_SCL__I2C0_SCL
511 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 512 >;
4191c340
LW		 513 fsl,drive-strength = <MXS_DRIVE_8mA>;
514 fsl,voltage = <MXS_VOLTAGE_HIGH>;
515 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 516 };
530f1d41 517
5c697ea2
MR		 518 i2c0_pins_b: i2c0@1 {
519 reg = <1>;
520 fsl,pinmux-ids = <
bc3875f1
LW		 521 MX28_PAD_AUART0_RX__I2C0_SCL
522 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 523 >;
4191c340
LW		 524 fsl,drive-strength = <MXS_DRIVE_8mA>;
525 fsl,voltage = <MXS_VOLTAGE_HIGH>;
526 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 527 };
528
de7e934f
MR		 529 i2c1_pins_a: i2c1@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
bc3875f1
LW		 532 MX28_PAD_PWM0__I2C1_SCL
533 MX28_PAD_PWM1__I2C1_SDA
de7e934f 534 >;
4191c340
LW		 535 fsl,drive-strength = <MXS_DRIVE_8mA>;
536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
537 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 538 };
539
530f1d41
SG		 540 saif0_pins_a: saif0@0 {
541 reg = <0>;
f14da767 542 fsl,pinmux-ids = <
bc3875f1
LW		 543 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
544 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
545 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
546 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 547 >;
4191c340
LW		 548 fsl,drive-strength = <MXS_DRIVE_12mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 551 };
552
2e1dd9fc
LW		 553 saif0_pins_b: saif0@1 {
554 reg = <1>;
555 fsl,pinmux-ids = <
bc3875f1
LW		 556 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
557 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
558 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 559 >;
4191c340
LW		 560 fsl,drive-strength = <MXS_DRIVE_12mA>;
561 fsl,voltage = <MXS_VOLTAGE_HIGH>;
562 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 563 };
564
530f1d41
SG		 565 saif1_pins_a: saif1@0 {
566 reg = <0>;
f14da767 567 fsl,pinmux-ids = <
bc3875f1 568 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 569 >;
4191c340
LW		 570 fsl,drive-strength = <MXS_DRIVE_12mA>;
571 fsl,voltage = <MXS_VOLTAGE_HIGH>;
572 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 573 };
52f7176b 574
e1a4d18f
SG		 575 pwm0_pins_a: pwm0@0 {
576 reg = <0>;
577 fsl,pinmux-ids = <
bc3875f1 578 MX28_PAD_PWM0__PWM_0
e1a4d18f 579 >;
4191c340
LW		 580 fsl,drive-strength = <MXS_DRIVE_4mA>;
581 fsl,voltage = <MXS_VOLTAGE_HIGH>;
582 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 583 };
584
52f7176b
SG		 585 pwm2_pins_a: pwm2@0 {
586 reg = <0>;
587 fsl,pinmux-ids = <
bc3875f1 588 MX28_PAD_PWM2__PWM_2
52f7176b 589 >;
4191c340
LW		 590 fsl,drive-strength = <MXS_DRIVE_4mA>;
591 fsl,voltage = <MXS_VOLTAGE_HIGH>;
592 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 593 };
a915ee42 594
2bde51cb
JB		 595 pwm3_pins_a: pwm3@0 {
596 reg = <0>;
597 fsl,pinmux-ids = <
bc3875f1 598 MX28_PAD_PWM3__PWM_3
2bde51cb 599 >;
4191c340
LW		 600 fsl,drive-strength = <MXS_DRIVE_4mA>;
601 fsl,voltage = <MXS_VOLTAGE_HIGH>;
602 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 603 };
604
d248620c
MR		 605 pwm3_pins_b: pwm3@1 {
606 reg = <1>;
607 fsl,pinmux-ids = <
bc3875f1 608 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 609 >;
4191c340
LW		 610 fsl,drive-strength = <MXS_DRIVE_4mA>;
611 fsl,voltage = <MXS_VOLTAGE_HIGH>;
612 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 613 };
614
2f44211f
MR		 615 pwm4_pins_a: pwm4@0 {
616 reg = <0>;
617 fsl,pinmux-ids = <
bc3875f1 618 MX28_PAD_PWM4__PWM_4
2f44211f 619 >;
4191c340
LW		 620 fsl,drive-strength = <MXS_DRIVE_4mA>;
621 fsl,voltage = <MXS_VOLTAGE_HIGH>;
622 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 623 };
624
a915ee42
SG		 625 lcdif_24bit_pins_a: lcdif-24bit@0 {
626 reg = <0>;
627 fsl,pinmux-ids = <
bc3875f1
LW		 628 MX28_PAD_LCD_D00__LCD_D0
629 MX28_PAD_LCD_D01__LCD_D1
630 MX28_PAD_LCD_D02__LCD_D2
631 MX28_PAD_LCD_D03__LCD_D3
632 MX28_PAD_LCD_D04__LCD_D4
633 MX28_PAD_LCD_D05__LCD_D5
634 MX28_PAD_LCD_D06__LCD_D6
635 MX28_PAD_LCD_D07__LCD_D7
636 MX28_PAD_LCD_D08__LCD_D8
637 MX28_PAD_LCD_D09__LCD_D9
638 MX28_PAD_LCD_D10__LCD_D10
639 MX28_PAD_LCD_D11__LCD_D11
640 MX28_PAD_LCD_D12__LCD_D12
641 MX28_PAD_LCD_D13__LCD_D13
642 MX28_PAD_LCD_D14__LCD_D14
643 MX28_PAD_LCD_D15__LCD_D15
644 MX28_PAD_LCD_D16__LCD_D16
645 MX28_PAD_LCD_D17__LCD_D17
646 MX28_PAD_LCD_D18__LCD_D18
647 MX28_PAD_LCD_D19__LCD_D19
648 MX28_PAD_LCD_D20__LCD_D20
649 MX28_PAD_LCD_D21__LCD_D21
650 MX28_PAD_LCD_D22__LCD_D22
651 MX28_PAD_LCD_D23__LCD_D23
a915ee42 652 >;
4191c340
LW		 653 fsl,drive-strength = <MXS_DRIVE_4mA>;
654 fsl,voltage = <MXS_VOLTAGE_HIGH>;
655 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 656 };
6ca44acf 657
4ced2a40
GGM		 658 lcdif_16bit_pins_a: lcdif-16bit@0 {
659 reg = <0>;
660 fsl,pinmux-ids = <
bc3875f1
LW		 661 MX28_PAD_LCD_D00__LCD_D0
662 MX28_PAD_LCD_D01__LCD_D1
663 MX28_PAD_LCD_D02__LCD_D2
664 MX28_PAD_LCD_D03__LCD_D3
665 MX28_PAD_LCD_D04__LCD_D4
666 MX28_PAD_LCD_D05__LCD_D5
667 MX28_PAD_LCD_D06__LCD_D6
668 MX28_PAD_LCD_D07__LCD_D7
669 MX28_PAD_LCD_D08__LCD_D8
670 MX28_PAD_LCD_D09__LCD_D9
671 MX28_PAD_LCD_D10__LCD_D10
672 MX28_PAD_LCD_D11__LCD_D11
673 MX28_PAD_LCD_D12__LCD_D12
674 MX28_PAD_LCD_D13__LCD_D13
675 MX28_PAD_LCD_D14__LCD_D14
676 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 677 >;
4191c340
LW		 678 fsl,drive-strength = <MXS_DRIVE_4mA>;
679 fsl,voltage = <MXS_VOLTAGE_HIGH>;
680 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 681 };
682
23ad6f65
LW		 683 lcdif_sync_pins_a: lcdif-sync@0 {
684 reg = <0>;
685 fsl,pinmux-ids = <
bc3875f1
LW		 686 MX28_PAD_LCD_RS__LCD_DOTCLK
687 MX28_PAD_LCD_CS__LCD_ENABLE
688 MX28_PAD_LCD_RD_E__LCD_VSYNC
689 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 690 >;
4191c340
LW		 691 fsl,drive-strength = <MXS_DRIVE_4mA>;
692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
693 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 694 };
695
6ca44acf
SG		 696 can0_pins_a: can0@0 {
697 reg = <0>;
698 fsl,pinmux-ids = <
bc3875f1
LW		 699 MX28_PAD_GPMI_RDY2__CAN0_TX
700 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 701 >;
4191c340
LW		 702 fsl,drive-strength = <MXS_DRIVE_4mA>;
703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
704 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 705 };
706
707 can1_pins_a: can1@0 {
708 reg = <0>;
709 fsl,pinmux-ids = <
bc3875f1
LW		 710 MX28_PAD_GPMI_CE2N__CAN1_TX
711 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 712 >;
4191c340
LW		 713 fsl,drive-strength = <MXS_DRIVE_4mA>;
714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
715 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 716 };
7f122213
MV		 717
718 spi2_pins_a: spi2@0 {
719 reg = <0>;
720 fsl,pinmux-ids = <
bc3875f1
LW		 721 MX28_PAD_SSP2_SCK__SSP2_SCK
722 MX28_PAD_SSP2_MOSI__SSP2_CMD
723 MX28_PAD_SSP2_MISO__SSP2_D0
724 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 725 >;
4191c340
LW		 726 fsl,drive-strength = <MXS_DRIVE_8mA>;
727 fsl,voltage = <MXS_VOLTAGE_HIGH>;
728 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 729 };
bb2f1261 730
3314d2be
LW		 731 spi3_pins_a: spi3@0 {
732 reg = <0>;
733 fsl,pinmux-ids = <
bc3875f1
LW		 734 MX28_PAD_AUART2_RX__SSP3_D4
735 MX28_PAD_AUART2_TX__SSP3_D5
736 MX28_PAD_SSP3_SCK__SSP3_SCK
737 MX28_PAD_SSP3_MOSI__SSP3_CMD
738 MX28_PAD_SSP3_MISO__SSP3_D0
739 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 740 >;
4191c340
LW		 741 fsl,drive-strength = <MXS_DRIVE_8mA>;
742 fsl,voltage = <MXS_VOLTAGE_HIGH>;
743 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 744 };
745
bb2f1261
MV		 746 usbphy0_pins_a: usbphy0@0 {
747 reg = <0>;
748 fsl,pinmux-ids = <
bc3875f1 749 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 750 >;
4191c340
LW		 751 fsl,drive-strength = <MXS_DRIVE_12mA>;
752 fsl,voltage = <MXS_VOLTAGE_HIGH>;
753 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 754 };
755
756 usbphy0_pins_b: usbphy0@1 {
757 reg = <1>;
758 fsl,pinmux-ids = <
bc3875f1 759 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 760 >;
4191c340
LW		 761 fsl,drive-strength = <MXS_DRIVE_12mA>;
762 fsl,voltage = <MXS_VOLTAGE_HIGH>;
763 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 764 };
765
766 usbphy1_pins_a: usbphy1@0 {
767 reg = <0>;
768 fsl,pinmux-ids = <
bc3875f1 769 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 770 >;
4191c340
LW		 771 fsl,drive-strength = <MXS_DRIVE_12mA>;
772 fsl,voltage = <MXS_VOLTAGE_HIGH>;
773 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 774 };
69c02f95
FE		 775
776 usb0_id_pins_a: usb0id@0 {
777 reg = <0>;
778 fsl,pinmux-ids = <
e96e1782 779 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 780 >;
e96e1782
LW		 781 fsl,drive-strength = <MXS_DRIVE_12mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 784 };
bc3a59c1
DA		 785 };
786
296f8cd3 787 digctl: digctl@8001c000 {
115581cf 788 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 789 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 790 interrupts = <89>;
791 status = "disabled";
792 };
793
296f8cd3 794 etm: etm@80022000 {
0f06cde7 795 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 796 status = "disabled";
797 };
798
f30fb03d 799 dma_apbx: dma-apbx@80024000 {
84f3570a 800 compatible = "fsl,imx28-dma-apbx";
0f06cde7 801 reg = <0x80024000 0x2000>;
f30fb03d
SG		 802 interrupts = <78 79 66 0
803 80 81 68 69
804 70 71 72 73
805 74 75 76 77>;
806 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
807 "saif0", "saif1", "i2c0", "i2c1",
808 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
809 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
810 #dma-cells = <1>;
811 dma-channels = <16>;
b598b9f3 812 clocks = <&clks 26>;
bc3a59c1
DA		 813 };
814
296f8cd3 815 dcp: dcp@80028000 {
7d56a28f 816 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 817 reg = <0x80028000 0x2000>;
bc3a59c1 818 interrupts = <52 53 54>;
7d56a28f 819 status = "okay";
bc3a59c1
DA		 820 };
821
296f8cd3 822 pxp: pxp@8002a000 {
0f06cde7 823 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 824 interrupts = <39>;
825 status = "disabled";
826 };
827
296f8cd3 828 ocotp: ocotp@8002c000 {
69d75a02 829 compatible = "fsl,ocotp";
0f06cde7 830 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 831 status = "disabled";
832 };
833
834 axi-ahb@8002e000 {
0f06cde7 835 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 836 status = "disabled";
837 };
838
296f8cd3 839 lcdif: lcdif@80030000 {
a915ee42 840 compatible = "fsl,imx28-lcdif";
0f06cde7 841 reg = <0x80030000 0x2000>;
7f2b9288 842 interrupts = <38>;
b598b9f3 843 clocks = <&clks 55>;
f30fb03d
SG		 844 dmas = <&dma_apbh 13>;
845 dma-names = "rx";
bc3a59c1
DA		 846 status = "disabled";
847 };
848
849 can0: can@80032000 {
6ca44acf 850 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 851 reg = <0x80032000 0x2000>;
bc3a59c1 852 interrupts = <8>;
b598b9f3
SG		 853 clocks = <&clks 58>, <&clks 58>;
854 clock-names = "ipg", "per";
bc3a59c1
DA		 855 status = "disabled";
856 };
857
858 can1: can@80034000 {
6ca44acf 859 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 860 reg = <0x80034000 0x2000>;
bc3a59c1 861 interrupts = <9>;
b598b9f3
SG		 862 clocks = <&clks 59>, <&clks 59>;
863 clock-names = "ipg", "per";
bc3a59c1
DA		 864 status = "disabled";
865 };
866
296f8cd3 867 simdbg: simdbg@8003c000 {
0f06cde7 868 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 869 status = "disabled";
870 };
871
296f8cd3 872 simgpmisel: simgpmisel@8003c200 {
0f06cde7 873 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 874 status = "disabled";
875 };
876
296f8cd3 877 simsspsel: simsspsel@8003c300 {
0f06cde7 878 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 879 status = "disabled";
880 };
881
296f8cd3 882 simmemsel: simmemsel@8003c400 {
0f06cde7 883 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 884 status = "disabled";
885 };
886
296f8cd3 887 gpiomon: gpiomon@8003c500 {
0f06cde7 888 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 889 status = "disabled";
890 };
891
296f8cd3 892 simenet: simenet@8003c700 {
0f06cde7 893 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 894 status = "disabled";
895 };
896
296f8cd3 897 armjtag: armjtag@8003c800 {
0f06cde7 898 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 899 status = "disabled";
900 };
07a3ce7f 901 };
bc3a59c1
DA		 902
903 apbx@80040000 {
904 compatible = "simple-bus";
905 #address-cells = <1>;
906 #size-cells = <1>;
907 reg = <0x80040000 0x40000>;
908 ranges;
909
b598b9f3 910 clks: clkctrl@80040000 {
8f7cf881 911 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 912 reg = <0x80040000 0x2000>;
b598b9f3 913 #clock-cells = <1>;
bc3a59c1
DA		 914 };
915
916 saif0: saif@80042000 {
530f1d41 917 compatible = "fsl,imx28-saif";
0f06cde7 918 reg = <0x80042000 0x2000>;
7f2b9288 919 interrupts = <59>;
66acaf3f 920 #clock-cells = <0>;
b598b9f3 921 clocks = <&clks 53>;
f30fb03d
SG		 922 dmas = <&dma_apbx 4>;
923 dma-names = "rx-tx";
bc3a59c1
DA		 924 status = "disabled";
925 };
926
296f8cd3 927 power: power@80044000 {
0f06cde7 928 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 929 status = "disabled";
930 };
931
932 saif1: saif@80046000 {
530f1d41 933 compatible = "fsl,imx28-saif";
0f06cde7 934 reg = <0x80046000 0x2000>;
7f2b9288 935 interrupts = <58>;
b598b9f3 936 clocks = <&clks 54>;
f30fb03d
SG		 937 dmas = <&dma_apbx 5>;
938 dma-names = "rx-tx";
bc3a59c1
DA		 939 status = "disabled";
940 };
941
296f8cd3 942 lradc: lradc@80050000 {
aef35104 943 compatible = "fsl,imx28-lradc";
0f06cde7 944 reg = <0x80050000 0x2000>;
aef35104
MV		 945 interrupts = <10 14 15 16 17 18 19
946 20 21 22 23 24 25>;
bc3a59c1 947 status = "disabled";
18da755d 948 clocks = <&clks 41>;
bc3a59c1
DA		 949 };
950
296f8cd3 951 spdif: spdif@80054000 {
0f06cde7 952 reg = <0x80054000 0x2000>;
7f2b9288 953 interrupts = <45>;
f30fb03d
SG		 954 dmas = <&dma_apbx 2>;
955 dma-names = "tx";
bc3a59c1
DA		 956 status = "disabled";
957 };
958
296f8cd3 959 mxs_rtc: rtc@80056000 {
f98c990c 960 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 961 reg = <0x80056000 0x2000>;
f98c990c 962 interrupts = <29>;
bc3a59c1
DA		 963 };
964
965 i2c0: i2c@80058000 {
2a96e391
SG		 966 #address-cells = <1>;
967 #size-cells = <0>;
968 compatible = "fsl,imx28-i2c";
0f06cde7 969 reg = <0x80058000 0x2000>;
7f2b9288 970 interrupts = <111>;
cd4f2d4a 971 clock-frequency = <100000>;
f30fb03d
SG		 972 dmas = <&dma_apbx 6>;
973 dma-names = "rx-tx";
bc3a59c1
DA		 974 status = "disabled";
975 };
976
977 i2c1: i2c@8005a000 {
2a96e391
SG		 978 #address-cells = <1>;
979 #size-cells = <0>;
980 compatible = "fsl,imx28-i2c";
0f06cde7 981 reg = <0x8005a000 0x2000>;
7f2b9288 982 interrupts = <110>;
cd4f2d4a 983 clock-frequency = <100000>;
f30fb03d
SG		 984 dmas = <&dma_apbx 7>;
985 dma-names = "rx-tx";
bc3a59c1
DA		 986 status = "disabled";
987 };
988
52f7176b
SG		 989 pwm: pwm@80064000 {
990 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 991 reg = <0x80064000 0x2000>;
b598b9f3 992 clocks = <&clks 44>;
52f7176b
SG		 993 #pwm-cells = <2>;
994 fsl,pwm-number = <8>;
bc3a59c1
DA		 995 status = "disabled";
996 };
997
296f8cd3 998 timer: timrot@80068000 {
eeca6e60 999 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1000 reg = <0x80068000 0x2000>;
eeca6e60 1001 interrupts = <48 49 50 51>;
2efb9504 1002 clocks = <&clks 26>;
bc3a59c1
DA		 1003 };
1004
1005 auart0: serial@8006a000 {
80d969e4 1006 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1007 reg = <0x8006a000 0x2000>;
7f2b9288 1008 interrupts = <112>;
f30fb03d
SG		 1009 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1010 dma-names = "rx", "tx";
b598b9f3 1011 clocks = <&clks 45>;
bc3a59c1
DA		 1012 status = "disabled";
1013 };
1014
1015 auart1: serial@8006c000 {
80d969e4 1016 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1017 reg = <0x8006c000 0x2000>;
7f2b9288 1018 interrupts = <113>;
f30fb03d
SG		 1019 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1020 dma-names = "rx", "tx";
b598b9f3 1021 clocks = <&clks 45>;
bc3a59c1
DA		 1022 status = "disabled";
1023 };
1024
1025 auart2: serial@8006e000 {
80d969e4 1026 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1027 reg = <0x8006e000 0x2000>;
7f2b9288 1028 interrupts = <114>;
f30fb03d
SG		 1029 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1030 dma-names = "rx", "tx";
b598b9f3 1031 clocks = <&clks 45>;
bc3a59c1
DA		 1032 status = "disabled";
1033 };
1034
1035 auart3: serial@80070000 {
80d969e4 1036 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1037 reg = <0x80070000 0x2000>;
7f2b9288 1038 interrupts = <115>;
f30fb03d
SG		 1039 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1040 dma-names = "rx", "tx";
b598b9f3 1041 clocks = <&clks 45>;
bc3a59c1
DA		 1042 status = "disabled";
1043 };
1044
1045 auart4: serial@80072000 {
80d969e4 1046 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1047 reg = <0x80072000 0x2000>;
7f2b9288 1048 interrupts = <116>;
f30fb03d
SG		 1049 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1050 dma-names = "rx", "tx";
b598b9f3 1051 clocks = <&clks 45>;
bc3a59c1
DA		 1052 status = "disabled";
1053 };
1054
1055 duart: serial@80074000 {
1056 compatible = "arm,pl011", "arm,primecell";
1057 reg = <0x80074000 0x1000>;
1058 interrupts = <47>;
b598b9f3
SG		 1059 clocks = <&clks 45>, <&clks 26>;
1060 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1061 status = "disabled";
1062 };
1063
1064 usbphy0: usbphy@8007c000 {
5da01270 1065 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1066 reg = <0x8007c000 0x2000>;
b598b9f3 1067 clocks = <&clks 62>;
bc3a59c1
DA		 1068 status = "disabled";
1069 };
1070
1071 usbphy1: usbphy@8007e000 {
5da01270 1072 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1073 reg = <0x8007e000 0x2000>;
b598b9f3 1074 clocks = <&clks 63>;
bc3a59c1
DA		 1075 status = "disabled";
1076 };
1077 };
1078 };
1079
1080 ahb@80080000 {
1081 compatible = "simple-bus";
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 reg = <0x80080000 0x80000>;
1085 ranges;
1086
5da01270
RZ		 1087 usb0: usb@80080000 {
1088 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1089 reg = <0x80080000 0x10000>;
5da01270 1090 interrupts = <93>;
b598b9f3 1091 clocks = <&clks 60>;
5da01270 1092 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1093 status = "disabled";
1094 };
1095
5da01270
RZ		 1096 usb1: usb@80090000 {
1097 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1098 reg = <0x80090000 0x10000>;
5da01270 1099 interrupts = <92>;
b598b9f3 1100 clocks = <&clks 61>;
5da01270 1101 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 1102 status = "disabled";
1103 };
1104
296f8cd3 1105 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1106 reg = <0x800c0000 0x10000>;
1107 status = "disabled";
1108 };
1109
1110 mac0: ethernet@800f0000 {
1111 compatible = "fsl,imx28-fec";
1112 reg = <0x800f0000 0x4000>;
1113 interrupts = <101>;
f231a9fe
WS		 1114 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1115 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1116 status = "disabled";
1117 };
1118
1119 mac1: ethernet@800f4000 {
1120 compatible = "fsl,imx28-fec";
1121 reg = <0x800f4000 0x4000>;
1122 interrupts = <102>;
b598b9f3
SG		 1123 clocks = <&clks 57>, <&clks 57>;
1124 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1125 status = "disabled";
1126 };
1127
296f8cd3 1128 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1129 reg = <0x800f8000 0x8000>;
1130 status = "disabled";
1131 };
bc3a59c1
DA		 1132 };
1133};
Arne's tree of linux kernel.