[people/arne_f/kernel.git] / arch / arm / boot / dts / imx53-mba53.dts

/*
 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx53-tqma53.dtsi"

/ {
	model = "TQ MBa53 starter kit";
	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";

	reg_backlight: fixed@0 {
		compatible = "regulator-fixed";
		regulator-name = "lcd-supply";
		gpio = <&gpio2 5 0>;
		startup-delay-us = <5000>;
		enable-active-low;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 50000>;
		brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
		default-brightness-level = <10>;
		enable-gpios = <&gpio7 7 0>;
		power-supply = <&reg_backlight>;
	};

	disp1: display@disp1 {
		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp1_1>;
		crtcs = <&ipu 1>;
		interface-pix-fmt = "rgb24";
		status = "disabled";
	};

	reg_3p2v: 3p2v {
		compatible = "regulator-fixed";
		regulator-name = "3P2V";
		regulator-min-microvolt = <3200000>;
		regulator-max-microvolt = <3200000>;
		regulator-always-on;
	};

	sound {
		compatible = "tq,imx53-mba53-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx53-mba53-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <2>;
		mux-ext-port = <5>;
	};
};

&ldb {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_1>;
	status = "disabled";
};

&iomuxc {
	lvds1 {
		pinctrl_lvds1_1: lvds1-grp1 {
			fsl,pins = <
				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
			>;
		};

		pinctrl_lvds1_2: lvds1-grp2 {
			fsl,pins = <
				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
			>;
		};
	};

	disp1 {
		pinctrl_disp1_1: disp1-grp1 {
			fsl,pins = <
				MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
				MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
				MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
				MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
			>;
		};
	};

	tve {
		pinctrl_vga_sync_1: vgasync-grp1 {
			fsl,pins = <
				/* VGA_VSYNC, HSYNC with max drive strength */
				MX53_PAD_EIM_CS1__IPU_DI1_PIN6	   0xe6
				MX53_PAD_EIM_DA15__IPU_DI1_PIN4	   0xe6
			>;
		};
	};
};

&cspi {
	status = "okay";
};

&audmux {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux_1>;
};

&i2c2 {
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 150>;
		VDDA-supply = <&reg_3p2v>;
		VDDIO-supply = <&reg_3p2v>;
	};

	expander: pca9554@20 {
		compatible = "pca9554";
		reg = <0x20>;
		interrupts = <109>;
		#gpio-cells = <2>;
		gpio-controller;
	};

	sensor2: lm75@49 {
		compatible = "lm75";
		reg = <0x49>;
	};
};

&fec {
	phy-reset-gpios = <&gpio7 6 0>;
	status = "okay";
};

&esdhc2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ecspi1 {
	status = "okay";
};

&usbotg {
	dr_mode = "host";
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart2 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&tve {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_vga_sync_1>;
	ddc = <&i2c3>;
	fsl,tve-mode = "vga";
	fsl,hsync-pin = <4>;
	fsl,vsync-pin = <6>;
	status = "okay";
};
Commit	Line	Data
be3a568d ST	1	/*
	2	* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
	3	* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/dts-v1/;
36dffd8f	14	#include "imx53-tqma53.dtsi"
be3a568d ST	15
	16	/ {
	17	model = "TQ MBa53 starter kit";
	18	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
4fa8cf79 SH	19
	20	reg_backlight: fixed@0 {
	21	compatible = "regulator-fixed";
	22	regulator-name = "lcd-supply";
	23	gpio = <&gpio2 5 0>;
	24	startup-delay-us = <5000>;
	25	enable-active-low;
	26	};
	27
	28	backlight {
	29	compatible = "pwm-backlight";
15968f1b	30	pwms = <&pwm2 0 50000>;
4fa8cf79 SH	31	brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
	32	default-brightness-level = <10>;
	33	enable-gpios = <&gpio7 7 0>;
	34	power-supply = <&reg_backlight>;
	35	};
	36
	37	disp1: display@disp1 {
	38	compatible = "fsl,imx-parallel-display";
	39	pinctrl-names = "default";
	40	pinctrl-0 = <&pinctrl_disp1_1>;
	41	crtcs = <&ipu 1>;
	42	interface-pix-fmt = "rgb24";
	43	status = "disabled";
	44	};
eefb8008 MN	45
	46	reg_3p2v: 3p2v {
	47	compatible = "regulator-fixed";
	48	regulator-name = "3P2V";
	49	regulator-min-microvolt = <3200000>;
	50	regulator-max-microvolt = <3200000>;
	51	regulator-always-on;
	52	};
	53
	54	sound {
	55	compatible = "tq,imx53-mba53-sgtl5000",
	56	"fsl,imx-audio-sgtl5000";
	57	model = "imx53-mba53-sgtl5000";
	58	ssi-controller = <&ssi2>;
	59	audio-codec = <&codec>;
	60	audio-routing =
	61	"MIC_IN", "Mic Jack",
	62	"Mic Jack", "Mic Bias",
	63	"Headphone Jack", "HP_OUT";
	64	mux-int-port = <2>;
	65	mux-ext-port = <5>;
	66	};
4fa8cf79 SH	67	};
	68
	69	&ldb {
	70	pinctrl-names = "default";
	71	pinctrl-0 = <&pinctrl_lvds1_1>;
	72	status = "disabled";
be3a568d ST	73	};
	74
	75	&iomuxc {
	76	lvds1 {
	77	pinctrl_lvds1_1: lvds1-grp1 {
e1641531	78	fsl,pins = <
188e97db ST	79	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
	80	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
	81	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
	82	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
	83	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
e1641531	84	>;
be3a568d ST	85	};
	86
	87	pinctrl_lvds1_2: lvds1-grp2 {
e1641531	88	fsl,pins = <
188e97db ST	89	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
	90	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
	91	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
	92	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
	93	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
e1641531	94	>;
be3a568d ST	95	};
	96	};
	97
	98	disp1 {
	99	pinctrl_disp1_1: disp1-grp1 {
e1641531	100	fsl,pins = <
81b8a3cd	101	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
188e97db ST	102	MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
	103	MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
	104	MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
	105	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
	106	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
	107	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
	108	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
	109	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
	110	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
	111	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
	112	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
	113	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
	114	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
	115	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
	116	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
	117	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
	118	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
	119	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
	120	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
	121	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
	122	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
	123	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
	124	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
	125	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
	126	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
	127	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
	128	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
e1641531	129	>;
be3a568d ST	130	};
be3a568d ST	131	};
d7db5392 PZ	132
	133	tve {
	134	pinctrl_vga_sync_1: vgasync-grp1 {
	135	fsl,pins = <
	136	/* VGA_VSYNC, HSYNC with max drive strength */
	137	MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
	138	MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
	139	>;
	140	};
	141	};
be3a568d ST	142	};
	143
	144	&cspi {
	145	status = "okay";
	146	};
	147
eefb8008 MN	148	&audmux {
	149	status = "okay";
	150	pinctrl-names = "default";
	151	pinctrl-0 = <&pinctrl_audmux_1>;
	152	};
	153
be3a568d ST	154	&i2c2 {
	155	codec: sgtl5000@a {
	156	compatible = "fsl,sgtl5000";
	157	reg = <0x0a>;
eefb8008 MN	158	clocks = <&clks 150>;
	159	VDDA-supply = <&reg_3p2v>;
	160	VDDIO-supply = <&reg_3p2v>;
be3a568d ST	161	};
	162
	163	expander: pca9554@20 {
	164	compatible = "pca9554";
	165	reg = <0x20>;
	166	interrupts = <109>;
74154be0 MN	167	#gpio-cells = <2>;
74154be0 MN	168	gpio-controller;
be3a568d ST	169	};
	170
	171	sensor2: lm75@49 {
	172	compatible = "lm75";
	173	reg = <0x49>;
	174	};
	175	};
	176
	177	&fec {
deb19eb7	178	phy-reset-gpios = <&gpio7 6 0>;
be3a568d ST	179	status = "okay";
	180	};
	181
	182	&esdhc2 {
	183	status = "okay";
	184	};
	185
	186	&uart3 {
	187	status = "okay";
	188	};
	189
	190	&ecspi1 {
	191	status = "okay";
	192	};
	193
3b1a0f23 MO	194	&usbotg {
	195	dr_mode = "host";
	196	status = "okay";
	197	};
	198
	199	&usbh1 {
	200	status = "okay";
	201	};
	202
be3a568d ST	203	&uart1 {
	204	status = "okay";
	205	};
	206
eefb8008 MN	207	&ssi2 {
	208	fsl,mode = "i2s-slave";
	209	status = "okay";
	210	};
	211
be3a568d ST	212	&uart2 {
	213	status = "okay";
	214	};
	215
	216	&can1 {
	217	status = "okay";
	218	};
	219
	220	&can2 {
	221	status = "okay";
	222	};
	223
	224	&i2c3 {
	225	status = "okay";
	226	};
d7db5392 PZ	227
	228	&tve {
	229	pinctrl-names = "default";
	230	pinctrl-0 = <&pinctrl_vga_sync_1>;
	231	ddc = <&i2c3>;
	232	fsl,tve-mode = "vga";
	233	fsl,hsync-pin = <4>;
	234	fsl,vsync-pin = <6>;
	235	status = "okay";
	236	};