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Commit | Line | Data |
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3c8276c6 RZ |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
36dffd8f | 14 | #include "imx6q.dtsi" |
3c8276c6 RZ |
15 | |
16 | / { | |
17 | model = "Freescale i.MX6 Quad SABRE Lite Board"; | |
18 | compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; | |
19 | ||
20 | memory { | |
21 | reg = <0x10000000 0x40000000>; | |
22 | }; | |
23 | ||
cf37a8ee RZ |
24 | regulators { |
25 | compatible = "simple-bus"; | |
26 | ||
27 | reg_2p5v: 2p5v { | |
28 | compatible = "regulator-fixed"; | |
29 | regulator-name = "2P5V"; | |
30 | regulator-min-microvolt = <2500000>; | |
31 | regulator-max-microvolt = <2500000>; | |
32 | regulator-always-on; | |
33 | }; | |
34 | ||
35 | reg_3p3v: 3p3v { | |
36 | compatible = "regulator-fixed"; | |
37 | regulator-name = "3P3V"; | |
38 | regulator-min-microvolt = <3300000>; | |
39 | regulator-max-microvolt = <3300000>; | |
40 | regulator-always-on; | |
41 | }; | |
74bd88f7 RZ |
42 | |
43 | reg_usb_otg_vbus: usb_otg_vbus { | |
44 | compatible = "regulator-fixed"; | |
45 | regulator-name = "usb_otg_vbus"; | |
46 | regulator-min-microvolt = <5000000>; | |
47 | regulator-max-microvolt = <5000000>; | |
48 | gpio = <&gpio3 22 0>; | |
49 | enable-active-high; | |
50 | }; | |
cf37a8ee | 51 | }; |
b7879fe6 RZ |
52 | |
53 | sound { | |
54 | compatible = "fsl,imx6q-sabrelite-sgtl5000", | |
55 | "fsl,imx-audio-sgtl5000"; | |
56 | model = "imx6q-sabrelite-sgtl5000"; | |
57 | ssi-controller = <&ssi1>; | |
58 | audio-codec = <&codec>; | |
59 | audio-routing = | |
60 | "MIC_IN", "Mic Jack", | |
61 | "Mic Jack", "Mic Bias", | |
62 | "Headphone Jack", "HP_OUT"; | |
63 | mux-int-port = <1>; | |
64 | mux-ext-port = <4>; | |
65 | }; | |
3c8276c6 | 66 | }; |
be4ccfce | 67 | |
2422d437 | 68 | &audmux { |
0fb1f804 | 69 | status = "okay"; |
2422d437 FE |
70 | pinctrl-names = "default"; |
71 | pinctrl-0 = <&pinctrl_audmux_1>; | |
0fb1f804 RZ |
72 | }; |
73 | ||
be4ccfce SG |
74 | &ecspi1 { |
75 | fsl,spi-num-chipselects = <1>; | |
76 | cs-gpios = <&gpio3 19 0>; | |
77 | pinctrl-names = "default"; | |
78 | pinctrl-0 = <&pinctrl_ecspi1_1>; | |
79 | status = "okay"; | |
80 | ||
81 | flash: m25p80@0 { | |
82 | compatible = "sst,sst25vf016b"; | |
83 | spi-max-frequency = <20000000>; | |
84 | reg = <0>; | |
85 | }; | |
86 | }; | |
87 | ||
2422d437 FE |
88 | &fec { |
89 | pinctrl-names = "default"; | |
90 | pinctrl-0 = <&pinctrl_enet_1>; | |
91 | phy-mode = "rgmii"; | |
92 | phy-reset-gpios = <&gpio3 23 0>; | |
be4ccfce SG |
93 | status = "okay"; |
94 | }; | |
95 | ||
2422d437 FE |
96 | &i2c1 { |
97 | status = "okay"; | |
98 | clock-frequency = <100000>; | |
99 | pinctrl-names = "default"; | |
100 | pinctrl-0 = <&pinctrl_i2c1_1>; | |
101 | ||
102 | codec: sgtl5000@0a { | |
103 | compatible = "fsl,sgtl5000"; | |
104 | reg = <0x0a>; | |
105 | clocks = <&clks 201>; | |
106 | VDDA-supply = <®_2p5v>; | |
107 | VDDIO-supply = <®_3p3v>; | |
108 | }; | |
109 | }; | |
110 | ||
be4ccfce SG |
111 | &iomuxc { |
112 | pinctrl-names = "default"; | |
113 | pinctrl-0 = <&pinctrl_hog>; | |
114 | ||
115 | hog { | |
116 | pinctrl_hog: hoggrp { | |
117 | fsl,pins = < | |
c56009b2 SG |
118 | MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 |
119 | MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 | |
120 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | |
121 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 | |
122 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 | |
123 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 | |
124 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 | |
125 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 | |
c986d35e | 126 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
be4ccfce SG |
127 | >; |
128 | }; | |
129 | }; | |
130 | }; | |
131 | ||
a09644b1 FE |
132 | &ldb { |
133 | status = "okay"; | |
134 | ||
135 | lvds-channel@0 { | |
136 | fsl,data-mapping = "spwg"; | |
137 | fsl,data-width = <18>; | |
138 | status = "okay"; | |
139 | ||
140 | display-timings { | |
141 | native-mode = <&timing0>; | |
142 | timing0: hsd100pxn1 { | |
143 | clock-frequency = <65000000>; | |
144 | hactive = <1024>; | |
145 | vactive = <768>; | |
146 | hback-porch = <220>; | |
147 | hfront-porch = <40>; | |
148 | vback-porch = <21>; | |
149 | vfront-porch = <7>; | |
150 | hsync-len = <60>; | |
151 | vsync-len = <10>; | |
152 | }; | |
153 | }; | |
154 | }; | |
155 | }; | |
156 | ||
2422d437 FE |
157 | &sata { |
158 | status = "okay"; | |
159 | }; | |
160 | ||
161 | &ssi1 { | |
162 | fsl,mode = "i2s-slave"; | |
163 | status = "okay"; | |
164 | }; | |
165 | ||
166 | &uart2 { | |
be4ccfce | 167 | status = "okay"; |
2422d437 FE |
168 | pinctrl-names = "default"; |
169 | pinctrl-0 = <&pinctrl_uart2_1>; | |
be4ccfce SG |
170 | }; |
171 | ||
172 | &usbh1 { | |
173 | status = "okay"; | |
174 | }; | |
175 | ||
2422d437 FE |
176 | &usbotg { |
177 | vbus-supply = <®_usb_otg_vbus>; | |
be4ccfce | 178 | pinctrl-names = "default"; |
2422d437 FE |
179 | pinctrl-0 = <&pinctrl_usbotg_1>; |
180 | disable-over-current; | |
be4ccfce SG |
181 | status = "okay"; |
182 | }; | |
183 | ||
184 | &usdhc3 { | |
185 | pinctrl-names = "default"; | |
186 | pinctrl-0 = <&pinctrl_usdhc3_2>; | |
187 | cd-gpios = <&gpio7 0 0>; | |
188 | wp-gpios = <&gpio7 1 0>; | |
189 | vmmc-supply = <®_3p3v>; | |
190 | status = "okay"; | |
191 | }; | |
192 | ||
193 | &usdhc4 { | |
194 | pinctrl-names = "default"; | |
195 | pinctrl-0 = <&pinctrl_usdhc4_2>; | |
196 | cd-gpios = <&gpio2 6 0>; | |
197 | wp-gpios = <&gpio2 7 0>; | |
198 | vmmc-supply = <®_3p3v>; | |
199 | status = "okay"; | |
200 | }; |