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[people/arne_f/kernel.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
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1bd0bd49 1#include "tegra30.dtsi"
64c4e9f8 2
640a7af5
LD		 3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
64c4e9f8
PDS		 26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
553c0a20 30 aliases {
763fbff2 31 rtc0 = "/i2c@7000d000/tps65911@2d";
553c0a20
SW		 32 rtc1 = "/rtc@7000e000";
33 };
34
64c4e9f8 35 memory {
95decf84 36 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 37 };
38
58ecb23f 39 pcie-controller@00003000 {
89e7ada4
JA		 40 status = "okay";
41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
42 vdd-supply = <&ldo1_reg>;
43 avdd-supply = <&ldo2_reg>;
44
45 pci@1,0 {
46 nvidia,num-lanes = <4>;
47 };
48
49 pci@2,0 {
50 nvidia,num-lanes = <1>;
51 };
52
53 pci@3,0 {
54 status = "okay";
55 nvidia,num-lanes = <1>;
56 };
57 };
58
02b1fea2
TR		 59 host1x@50000000 {
60 dc@54200000 {
61 rgb {
62 status = "okay";
63
64 nvidia,panel = <&panel>;
65 };
66 };
67 };
68
58ecb23f 69 pinmux@70000868 {
e5cbeef0
SW		 70 pinctrl-names = "default";
71 pinctrl-0 = <&state_default>;
72
73 state_default: pinmux {
74 sdmmc1_clk_pz0 {
75 nvidia,pins = "sdmmc1_clk_pz0";
76 nvidia,function = "sdmmc1";
a47c662a
LD		 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 79 };
80 sdmmc1_cmd_pz1 {
81 nvidia,pins = "sdmmc1_cmd_pz1",
82 "sdmmc1_dat0_py7",
83 "sdmmc1_dat1_py6",
84 "sdmmc1_dat2_py5",
85 "sdmmc1_dat3_py4";
86 nvidia,function = "sdmmc1";
a47c662a
LD		 87 nvidia,pull = <TEGRA_PIN_PULL_UP>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 89 };
6fb11131
WN		 90 sdmmc3_clk_pa6 {
91 nvidia,pins = "sdmmc3_clk_pa6";
92 nvidia,function = "sdmmc3";
a47c662a
LD		 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 95 };
96 sdmmc3_cmd_pa7 {
97 nvidia,pins = "sdmmc3_cmd_pa7",
98 "sdmmc3_dat0_pb7",
99 "sdmmc3_dat1_pb6",
100 "sdmmc3_dat2_pb5",
101 "sdmmc3_dat3_pb4";
102 nvidia,function = "sdmmc3";
a47c662a
LD		 103 nvidia,pull = <TEGRA_PIN_PULL_UP>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 105 };
e5cbeef0
SW		 106 sdmmc4_clk_pcc4 {
107 nvidia,pins = "sdmmc4_clk_pcc4",
108 "sdmmc4_rst_n_pcc3";
109 nvidia,function = "sdmmc4";
a47c662a
LD		 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 112 };
113 sdmmc4_dat0_paa0 {
114 nvidia,pins = "sdmmc4_dat0_paa0",
115 "sdmmc4_dat1_paa1",
116 "sdmmc4_dat2_paa2",
117 "sdmmc4_dat3_paa3",
118 "sdmmc4_dat4_paa4",
119 "sdmmc4_dat5_paa5",
120 "sdmmc4_dat6_paa6",
121 "sdmmc4_dat7_paa7";
122 nvidia,function = "sdmmc4";
a47c662a
LD		 123 nvidia,pull = <TEGRA_PIN_PULL_UP>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 125 };
8c6a3852
SW		 126 dap2_fs_pa2 {
127 nvidia,pins = "dap2_fs_pa2",
128 "dap2_sclk_pa3",
129 "dap2_din_pa4",
130 "dap2_dout_pa5";
131 nvidia,function = "i2s1";
a47c662a
LD		 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 134 };
6fb11131
WN		 135 sdio3 {
136 nvidia,pins = "drive_sdio3";
a47c662a
LD		 137 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
138 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 139 nvidia,pull-down-strength = <46>;
140 nvidia,pull-up-strength = <42>;
a47c662a
LD		 141 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
142 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 143 };
ecfd6c7f
LD		 144 uart3_txd_pw6 {
145 nvidia,pins = "uart3_txd_pw6",
146 "uart3_cts_n_pa1",
147 "uart3_rts_n_pc0",
148 "uart3_rxd_pw7";
149 nvidia,function = "uartc";
a47c662a
LD		 150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 152 };
e5cbeef0
SW		 153 };
154 };
155
64c4e9f8 156 serial@70006000 {
2a5fdc9a 157 status = "okay";
64c4e9f8
PDS		 158 };
159
ecfd6c7f
LD		 160 serial@70006200 {
161 compatible = "nvidia,tegra30-hsuart";
162 status = "okay";
ecfd6c7f
LD		 163 };
164
02b1fea2
TR		 165 pwm@7000a000 {
166 status = "okay";
167 };
168
169 panelddc: i2c@7000c000 {
2a5fdc9a 170 status = "okay";
64c4e9f8
PDS		 171 clock-frequency = <100000>;
172 };
173
174 i2c@7000c400 {
2a5fdc9a 175 status = "okay";
64c4e9f8
PDS		 176 clock-frequency = <100000>;
177 };
178
179 i2c@7000c500 {
2a5fdc9a 180 status = "okay";
64c4e9f8 181 clock-frequency = <100000>;
b46b0b54
LD		 182
183 /* ALS and Proximity sensor */
184 isl29028@44 {
185 compatible = "isil,isl29028";
186 reg = <0x44>;
187 interrupt-parent = <&gpio>;
6cecf916 188 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 189 };
64c4e9f8
PDS		 190 };
191
192 i2c@7000c700 {
2a5fdc9a 193 status = "okay";
64c4e9f8
PDS		 194 clock-frequency = <100000>;
195 };
196
197 i2c@7000d000 {
2a5fdc9a 198 status = "okay";
64c4e9f8 199 clock-frequency = <100000>;
8c6a3852
SW		 200
201 wm8903: wm8903@1a {
202 compatible = "wlf,wm8903";
203 reg = <0x1a>;
204 interrupt-parent = <&gpio>;
6cecf916 205 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 206
207 gpio-controller;
208 #gpio-cells = <2>;
209
210 micdet-cfg = <0>;
211 micdet-delay = <100>;
212 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
213 };
331da58c 214
167e6279
LD		 215 pmic: tps65911@2d {
216 compatible = "ti,tps65911";
217 reg = <0x2d>;
218
6cecf916 219 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 220 #interrupt-cells = <2>;
221 interrupt-controller;
222
44b12ef7
SW		 223 ti,system-power-controller;
224
167e6279
LD		 225 #gpio-cells = <2>;
226 gpio-controller;
227
228 vcc1-supply = <&vdd_ac_bat_reg>;
229 vcc2-supply = <&vdd_ac_bat_reg>;
230 vcc3-supply = <&vio_reg>;
fa4a9252 231 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 232 vcc5-supply = <&vdd_ac_bat_reg>;
233 vcc6-supply = <&vdd2_reg>;
234 vcc7-supply = <&vdd_ac_bat_reg>;
235 vccio-supply = <&vdd_ac_bat_reg>;
236
237 regulators {
b9c665d7 238 vdd1_reg: vdd1 {
167e6279
LD		 239 regulator-name = "vddio_ddr_1v2";
240 regulator-min-microvolt = <1200000>;
241 regulator-max-microvolt = <1200000>;
242 regulator-always-on;
243 };
244
b9c665d7 245 vdd2_reg: vdd2 {
167e6279
LD		 246 regulator-name = "vdd_1v5_gen";
247 regulator-min-microvolt = <1500000>;
248 regulator-max-microvolt = <1500000>;
249 regulator-always-on;
250 };
251
b9c665d7 252 vddctrl_reg: vddctrl {
167e6279
LD		 253 regulator-name = "vdd_cpu,vdd_sys";
254 regulator-min-microvolt = <1000000>;
255 regulator-max-microvolt = <1000000>;
256 regulator-always-on;
257 };
258
b9c665d7 259 vio_reg: vio {
167e6279
LD		 260 regulator-name = "vdd_1v8_gen";
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 regulator-always-on;
264 };
265
b9c665d7 266 ldo1_reg: ldo1 {
167e6279
LD		 267 regulator-name = "vdd_pexa,vdd_pexb";
268 regulator-min-microvolt = <1050000>;
269 regulator-max-microvolt = <1050000>;
270 };
271
b9c665d7 272 ldo2_reg: ldo2 {
167e6279
LD		 273 regulator-name = "vdd_sata,avdd_plle";
274 regulator-min-microvolt = <1050000>;
275 regulator-max-microvolt = <1050000>;
276 };
277
278 /* LDO3 is not connected to anything */
279
b9c665d7 280 ldo4_reg: ldo4 {
167e6279
LD		 281 regulator-name = "vdd_rtc";
282 regulator-min-microvolt = <1200000>;
283 regulator-max-microvolt = <1200000>;
284 regulator-always-on;
285 };
286
b9c665d7 287 ldo5_reg: ldo5 {
fa4a9252
LD		 288 regulator-name = "vddio_sdmmc,avdd_vdac";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-always-on;
292 };
293
b9c665d7 294 ldo6_reg: ldo6 {
167e6279
LD		 295 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
296 regulator-min-microvolt = <1200000>;
297 regulator-max-microvolt = <1200000>;
298 };
299
b9c665d7 300 ldo7_reg: ldo7 {
167e6279
LD		 301 regulator-name = "vdd_pllm,x,u,a_p_c_s";
302 regulator-min-microvolt = <1200000>;
303 regulator-max-microvolt = <1200000>;
304 regulator-always-on;
305 };
306
b9c665d7 307 ldo8_reg: ldo8 {
167e6279
LD		 308 regulator-name = "vdd_ddr_hs";
309 regulator-min-microvolt = <1000000>;
310 regulator-max-microvolt = <1000000>;
311 regulator-always-on;
312 };
313 };
314 };
74ecab27 315
7c7de6b0 316 temperature-sensor@4c {
74ecab27
WN		 317 compatible = "onnn,nct1008";
318 reg = <0x4c>;
7c7de6b0 319 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 320 interrupt-parent = <&gpio>;
321 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
322 };
2b8584d5 323
58ecb23f 324 tps62361@60 {
2b8584d5
SW		 325 compatible = "ti,tps62361";
326 reg = <0x60>;
327
328 regulator-name = "tps62361-vout";
329 regulator-min-microvolt = <500000>;
330 regulator-max-microvolt = <1500000>;
331 regulator-boot-on;
332 regulator-always-on;
333 ti,vsel0-state-high;
334 ti,vsel1-state-high;
335 };
64c4e9f8 336 };
850c4c8f 337
c42cb1c3
LD		 338 spi@7000da00 {
339 status = "okay";
340 spi-max-frequency = <25000000>;
341 spi-flash@1 {
342 compatible = "winbond,w25q32";
343 reg = <1>;
344 spi-max-frequency = <20000000>;
345 };
346 };
347
58ecb23f 348 pmc@7000e400 {
167e6279
LD		 349 status = "okay";
350 nvidia,invert-interrupt;
47d2d63b 351 nvidia,suspend-mode = <1>;
a44a019d
JL		 352 nvidia,cpu-pwr-good-time = <2000>;
353 nvidia,cpu-pwr-off-time = <200>;
354 nvidia,core-pwr-good-time = <3845 3845>;
355 nvidia,core-pwr-off-time = <0>;
356 nvidia,core-power-req-active-high;
357 nvidia,sys-clock-req-active-high;
167e6279
LD		 358 };
359
57899053
SW		 360 ahub@70080000 {
361 i2s@70080400 {
362 status = "okay";
363 };
364 };
365
c04abb3a 366 sdhci@78000000 {
2a5fdc9a 367 status = "okay";
3325f1bc
SW		 368 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
369 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
370 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 371 bus-width = <4>;
c04abb3a
SW		 372 };
373
c04abb3a 374 sdhci@78000600 {
2a5fdc9a 375 status = "okay";
7f217794 376 bus-width = <8>;
7a2617a6 377 non-removable;
c04abb3a
SW		 378 };
379
cc34c9f7
TT		 380 usb@7d008000 {
381 status = "okay";
382 };
383
384 usb-phy@7d008000 {
385 vbus-supply = <&usb3_vbus_reg>;
386 status = "okay";
387 };
388
02b1fea2
TR		 389 backlight: backlight {
390 compatible = "pwm-backlight";
391
392 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
393 power-supply = <&vdd_bl_reg>;
394 pwms = <&pwm 0 5000000>;
395
396 brightness-levels = <0 4 8 16 32 64 128 255>;
397 default-brightness-level = <6>;
398 };
399
7021d122
JL		 400 clocks {
401 compatible = "simple-bus";
402 #address-cells = <1>;
403 #size-cells = <0>;
404
58ecb23f 405 clk32k_in: clock@0 {
7021d122
JL		 406 compatible = "fixed-clock";
407 reg=<0>;
408 #clock-cells = <0>;
409 clock-frequency = <32768>;
410 };
411 };
412
02b1fea2
TR		 413 panel: panel {
414 compatible = "chunghwa,claa101wb01", "simple-panel";
415 ddc-i2c-bus = <&panelddc>;
416
417 power-supply = <&vdd_pnl1_reg>;
418 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
419
420 backlight = <&backlight>;
421 };
422
167e6279
LD		 423 regulators {
424 compatible = "simple-bus";
425 #address-cells = <1>;
426 #size-cells = <0>;
427
428 vdd_ac_bat_reg: regulator@0 {
429 compatible = "regulator-fixed";
430 reg = <0>;
431 regulator-name = "vdd_ac_bat";
432 regulator-min-microvolt = <5000000>;
433 regulator-max-microvolt = <5000000>;
434 regulator-always-on;
435 };
fa4a9252
LD		 436
437 cam_1v8_reg: regulator@1 {
438 compatible = "regulator-fixed";
439 reg = <1>;
440 regulator-name = "cam_1v8";
441 regulator-min-microvolt = <1800000>;
442 regulator-max-microvolt = <1800000>;
443 enable-active-high;
3325f1bc 444 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 445 vin-supply = <&vio_reg>;
446 };
447
448 cp_5v_reg: regulator@2 {
449 compatible = "regulator-fixed";
450 reg = <2>;
451 regulator-name = "cp_5v";
452 regulator-min-microvolt = <5000000>;
453 regulator-max-microvolt = <5000000>;
454 regulator-boot-on;
455 regulator-always-on;
456 enable-active-high;
3325f1bc 457 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 458 };
459
460 emmc_3v3_reg: regulator@3 {
461 compatible = "regulator-fixed";
462 reg = <3>;
463 regulator-name = "emmc_3v3";
464 regulator-min-microvolt = <3300000>;
465 regulator-max-microvolt = <3300000>;
466 regulator-always-on;
467 regulator-boot-on;
468 enable-active-high;
3325f1bc 469 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 470 vin-supply = <&sys_3v3_reg>;
471 };
472
473 modem_3v3_reg: regulator@4 {
474 compatible = "regulator-fixed";
475 reg = <4>;
476 regulator-name = "modem_3v3";
477 regulator-min-microvolt = <3300000>;
478 regulator-max-microvolt = <3300000>;
479 enable-active-high;
3325f1bc 480 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 481 };
482
483 pex_hvdd_3v3_reg: regulator@5 {
484 compatible = "regulator-fixed";
485 reg = <5>;
486 regulator-name = "pex_hvdd_3v3";
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 enable-active-high;
3325f1bc 490 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 491 vin-supply = <&sys_3v3_reg>;
492 };
493
494 vdd_cam1_ldo_reg: regulator@6 {
495 compatible = "regulator-fixed";
496 reg = <6>;
497 regulator-name = "vdd_cam1_ldo";
498 regulator-min-microvolt = <2800000>;
499 regulator-max-microvolt = <2800000>;
500 enable-active-high;
3325f1bc 501 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 502 vin-supply = <&sys_3v3_reg>;
503 };
504
505 vdd_cam2_ldo_reg: regulator@7 {
506 compatible = "regulator-fixed";
507 reg = <7>;
508 regulator-name = "vdd_cam2_ldo";
509 regulator-min-microvolt = <2800000>;
510 regulator-max-microvolt = <2800000>;
511 enable-active-high;
3325f1bc 512 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 513 vin-supply = <&sys_3v3_reg>;
514 };
515
516 vdd_cam3_ldo_reg: regulator@8 {
517 compatible = "regulator-fixed";
518 reg = <8>;
519 regulator-name = "vdd_cam3_ldo";
520 regulator-min-microvolt = <3300000>;
521 regulator-max-microvolt = <3300000>;
522 enable-active-high;
3325f1bc 523 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 524 vin-supply = <&sys_3v3_reg>;
525 };
526
527 vdd_com_reg: regulator@9 {
528 compatible = "regulator-fixed";
529 reg = <9>;
530 regulator-name = "vdd_com";
531 regulator-min-microvolt = <3300000>;
532 regulator-max-microvolt = <3300000>;
6fb11131
WN		 533 regulator-always-on;
534 regulator-boot-on;
fa4a9252 535 enable-active-high;
3325f1bc 536 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 537 vin-supply = <&sys_3v3_reg>;
538 };
539
540 vdd_fuse_3v3_reg: regulator@10 {
541 compatible = "regulator-fixed";
542 reg = <10>;
543 regulator-name = "vdd_fuse_3v3";
544 regulator-min-microvolt = <3300000>;
545 regulator-max-microvolt = <3300000>;
546 enable-active-high;
3325f1bc 547 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 548 vin-supply = <&sys_3v3_reg>;
549 };
550
551 vdd_pnl1_reg: regulator@11 {
552 compatible = "regulator-fixed";
553 reg = <11>;
554 regulator-name = "vdd_pnl1";
555 regulator-min-microvolt = <3300000>;
556 regulator-max-microvolt = <3300000>;
557 regulator-always-on;
558 regulator-boot-on;
559 enable-active-high;
3325f1bc 560 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 561 vin-supply = <&sys_3v3_reg>;
562 };
563
564 vdd_vid_reg: regulator@12 {
565 compatible = "regulator-fixed";
566 reg = <12>;
567 regulator-name = "vddio_vid";
568 regulator-min-microvolt = <5000000>;
569 regulator-max-microvolt = <5000000>;
570 enable-active-high;
3325f1bc 571 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 572 gpio-open-drain;
573 vin-supply = <&vdd_5v0_reg>;
574 };
167e6279
LD		 575 };
576
8c6a3852
SW		 577 sound {
578 compatible = "nvidia,tegra-audio-wm8903-cardhu",
579 "nvidia,tegra-audio-wm8903";
580 nvidia,model = "NVIDIA Tegra Cardhu";
581
582 nvidia,audio-routing =
583 "Headphone Jack", "HPOUTR",
584 "Headphone Jack", "HPOUTL",
585 "Int Spk", "ROP",
586 "Int Spk", "RON",
587 "Int Spk", "LOP",
588 "Int Spk", "LON",
589 "Mic Jack", "MICBIAS",
590 "IN1L", "Mic Jack";
591
592 nvidia,i2s-controller = <&tegra_i2s1>;
593 nvidia,audio-codec = <&wm8903>;
594
3325f1bc
SW		 595 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
596 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
597 GPIO_ACTIVE_HIGH>;
f9cd2b3b 598
05849c93
HD		 599 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
600 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
601 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 602 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 603 };
64c4e9f8 604};
Arne's tree of linux kernel.