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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
e2780a68 | 5 | #include <linux/pm.h> |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
e2780a68 | 8 | #include <asm/cpufeature.h> |
e2780a68 | 9 | #include <asm/apicdef.h> |
60063497 | 10 | #include <linux/atomic.h> |
e2780a68 IM |
11 | #include <asm/fixmap.h> |
12 | #include <asm/mpspec.h> | |
13c88fb5 | 13 | #include <asm/msr.h> |
67c5fc5c TG |
14 | |
15 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
16 | ||
67c5fc5c TG |
17 | /* |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
b7c4948e HK |
24 | /* Macros for apic_extnmi which controls external NMI masking */ |
25 | #define APIC_EXTNMI_BSP 0 /* Default */ | |
26 | #define APIC_EXTNMI_ALL 1 | |
27 | #define APIC_EXTNMI_NONE 2 | |
28 | ||
67c5fc5c TG |
29 | /* |
30 | * Define the default level of output to be very little | |
31 | * This can be turned up by using apic=verbose for more | |
32 | * information and apic=debug for _lots_ of information. | |
33 | * apic_verbosity is defined in apic.c | |
34 | */ | |
35 | #define apic_printk(v, s, a...) do { \ | |
36 | if ((v) <= apic_verbosity) \ | |
37 | printk(s, ##a); \ | |
38 | } while (0) | |
39 | ||
40 | ||
160d8dac | 41 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 42 | extern void generic_apic_probe(void); |
160d8dac IM |
43 | #else |
44 | static inline void generic_apic_probe(void) | |
45 | { | |
46 | } | |
47 | #endif | |
67c5fc5c TG |
48 | |
49 | #ifdef CONFIG_X86_LOCAL_APIC | |
50 | ||
baa13188 | 51 | extern unsigned int apic_verbosity; |
67c5fc5c | 52 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 53 | |
3c999f14 | 54 | extern int disable_apic; |
1ade93ef | 55 | extern unsigned int lapic_timer_frequency; |
0939e4fd IM |
56 | |
57 | #ifdef CONFIG_SMP | |
58 | extern void __inquire_remote_apic(int apicid); | |
59 | #else /* CONFIG_SMP */ | |
60 | static inline void __inquire_remote_apic(int apicid) | |
61 | { | |
62 | } | |
63 | #endif /* CONFIG_SMP */ | |
64 | ||
65 | static inline void default_inquire_remote_apic(int apicid) | |
66 | { | |
67 | if (apic_verbosity >= APIC_DEBUG) | |
68 | __inquire_remote_apic(apicid); | |
69 | } | |
70 | ||
8312136f CG |
71 | /* |
72 | * With 82489DX we can't rely on apic feature bit | |
73 | * retrieved via cpuid but still have to deal with | |
74 | * such an apic chip so we assume that SMP configuration | |
75 | * is found from MP table (64bit case uses ACPI mostly | |
76 | * which set smp presence flag as well so we are safe | |
77 | * to use this helper too). | |
78 | */ | |
79 | static inline bool apic_from_smp_config(void) | |
80 | { | |
81 | return smp_found_config && !disable_apic; | |
82 | } | |
83 | ||
67c5fc5c TG |
84 | /* |
85 | * Basic functions accessing APICs. | |
86 | */ | |
87 | #ifdef CONFIG_PARAVIRT | |
88 | #include <asm/paravirt.h> | |
96a388de | 89 | #endif |
67c5fc5c | 90 | |
2b97df06 | 91 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 92 | |
1b374e4d | 93 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 94 | { |
593f4a78 | 95 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 96 | |
a930dc45 | 97 | alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, |
593f4a78 MR |
98 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), |
99 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
100 | } |
101 | ||
1b374e4d | 102 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
103 | { |
104 | return *((volatile u32 *)(APIC_BASE + reg)); | |
105 | } | |
106 | ||
c1eeb2de YL |
107 | extern void native_apic_wait_icr_idle(void); |
108 | extern u32 native_safe_apic_wait_icr_idle(void); | |
109 | extern void native_apic_icr_write(u32 low, u32 id); | |
110 | extern u64 native_apic_icr_read(void); | |
111 | ||
8d806960 TG |
112 | static inline bool apic_is_x2apic_enabled(void) |
113 | { | |
114 | u64 msr; | |
115 | ||
116 | if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) | |
117 | return false; | |
118 | return msr & X2APIC_ENABLE; | |
119 | } | |
120 | ||
e02ae387 PB |
121 | extern void enable_IR_x2apic(void); |
122 | ||
123 | extern int get_physical_broadcast(void); | |
124 | ||
125 | extern int lapic_get_maxlvt(void); | |
126 | extern void clear_local_APIC(void); | |
127 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
128 | extern void disable_local_APIC(void); | |
129 | extern void lapic_shutdown(void); | |
130 | extern void sync_Arb_IDs(void); | |
131 | extern void init_bsp_APIC(void); | |
132 | extern void setup_local_APIC(void); | |
133 | extern void init_apic_mappings(void); | |
134 | void register_lapic_address(unsigned long address); | |
135 | extern void setup_boot_APIC_clock(void); | |
136 | extern void setup_secondary_APIC_clock(void); | |
6731b0d6 | 137 | extern void lapic_update_tsc_freq(void); |
e02ae387 PB |
138 | extern int APIC_init_uniprocessor(void); |
139 | ||
140 | #ifdef CONFIG_X86_64 | |
141 | static inline int apic_force_enable(unsigned long addr) | |
142 | { | |
143 | return -1; | |
144 | } | |
145 | #else | |
146 | extern int apic_force_enable(unsigned long addr); | |
147 | #endif | |
148 | ||
149 | extern int apic_bsp_setup(bool upmode); | |
150 | extern void apic_ap_setup(void); | |
151 | ||
152 | /* | |
153 | * On 32bit this is mach-xxx local | |
154 | */ | |
155 | #ifdef CONFIG_X86_64 | |
156 | extern int apic_is_clustered_box(void); | |
157 | #else | |
158 | static inline int apic_is_clustered_box(void) | |
159 | { | |
160 | return 0; | |
161 | } | |
162 | #endif | |
163 | ||
164 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); | |
165 | ||
166 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
167 | static inline void lapic_shutdown(void) { } | |
168 | #define local_apic_timer_c2_ok 1 | |
169 | static inline void init_apic_mappings(void) { } | |
170 | static inline void disable_local_APIC(void) { } | |
171 | # define setup_boot_APIC_clock x86_init_noop | |
172 | # define setup_secondary_APIC_clock x86_init_noop | |
6731b0d6 | 173 | static inline void lapic_update_tsc_freq(void) { } |
e02ae387 PB |
174 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
175 | ||
d0b03bd1 | 176 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
177 | /* |
178 | * Make previous memory operations globally visible before | |
179 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
180 | * mfence for this. | |
181 | */ | |
182 | static inline void x2apic_wrmsr_fence(void) | |
183 | { | |
184 | asm volatile("mfence" : : : "memory"); | |
185 | } | |
186 | ||
13c88fb5 SS |
187 | static inline void native_apic_msr_write(u32 reg, u32 v) |
188 | { | |
189 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
190 | reg == APIC_LVR) | |
191 | return; | |
192 | ||
193 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
194 | } | |
195 | ||
0ab711ae MT |
196 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
197 | { | |
a585df8e | 198 | __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); |
0ab711ae MT |
199 | } |
200 | ||
13c88fb5 SS |
201 | static inline u32 native_apic_msr_read(u32 reg) |
202 | { | |
0059b243 | 203 | u64 msr; |
13c88fb5 SS |
204 | |
205 | if (reg == APIC_DFR) | |
206 | return -1; | |
207 | ||
0059b243 AK |
208 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
209 | return (u32)msr; | |
13c88fb5 SS |
210 | } |
211 | ||
c1eeb2de YL |
212 | static inline void native_x2apic_wait_icr_idle(void) |
213 | { | |
214 | /* no need to wait for icr idle in x2apic */ | |
215 | return; | |
216 | } | |
217 | ||
218 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
219 | { | |
220 | /* no need to wait for icr idle in x2apic */ | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
225 | { | |
226 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
227 | } | |
228 | ||
229 | static inline u64 native_x2apic_icr_read(void) | |
230 | { | |
231 | unsigned long val; | |
232 | ||
233 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
234 | return val; | |
235 | } | |
236 | ||
81a46dd8 | 237 | extern int x2apic_mode; |
fc1edaf9 | 238 | extern int x2apic_phys; |
d524165c | 239 | extern void __init check_x2apic(void); |
659006bf | 240 | extern void x2apic_setup(void); |
a11b5abe YL |
241 | static inline int x2apic_enabled(void) |
242 | { | |
62436a4d | 243 | return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); |
a11b5abe | 244 | } |
fc1edaf9 | 245 | |
62436a4d | 246 | #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) |
e02ae387 | 247 | #else /* !CONFIG_X86_X2APIC */ |
55eae7de | 248 | static inline void check_x2apic(void) { } |
659006bf | 249 | static inline void x2apic_setup(void) { } |
55eae7de | 250 | static inline int x2apic_enabled(void) { return 0; } |
cf6567fe | 251 | |
81a46dd8 | 252 | #define x2apic_mode (0) |
81a46dd8 | 253 | #define x2apic_supported() (0) |
e02ae387 | 254 | #endif /* !CONFIG_X86_X2APIC */ |
67c5fc5c | 255 | |
1f75ed0c IM |
256 | #ifdef CONFIG_X86_64 |
257 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
258 | #else | |
259 | ||
1f75ed0c IM |
260 | #endif |
261 | ||
e2780a68 IM |
262 | /* |
263 | * Copyright 2004 James Cleverdon, IBM. | |
264 | * Subject to the GNU Public License, v.2 | |
265 | * | |
266 | * Generic APIC sub-arch data struct. | |
267 | * | |
268 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
269 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
270 | * James Cleverdon. | |
271 | */ | |
be163a15 | 272 | struct apic { |
e2780a68 IM |
273 | char *name; |
274 | ||
275 | int (*probe)(void); | |
276 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
fa63030e | 277 | int (*apic_id_valid)(int apicid); |
e2780a68 IM |
278 | int (*apic_id_registered)(void); |
279 | ||
280 | u32 irq_delivery_mode; | |
281 | u32 irq_dest_mode; | |
282 | ||
283 | const struct cpumask *(*target_cpus)(void); | |
284 | ||
285 | int disable_esr; | |
286 | ||
287 | int dest_logical; | |
7abc0753 | 288 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
e2780a68 | 289 | |
1ac322d0 SS |
290 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
291 | const struct cpumask *mask); | |
e2780a68 IM |
292 | void (*init_apic_ldr)(void); |
293 | ||
7abc0753 | 294 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
e2780a68 IM |
295 | |
296 | void (*setup_apic_routing)(void); | |
e2780a68 | 297 | int (*cpu_present_to_apicid)(int mps_cpu); |
7abc0753 | 298 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); |
e11dadab | 299 | int (*check_phys_apicid_present)(int phys_apicid); |
e2780a68 IM |
300 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); |
301 | ||
e2780a68 IM |
302 | unsigned int (*get_apic_id)(unsigned long x); |
303 | unsigned long (*set_apic_id)(unsigned int id); | |
e2780a68 | 304 | |
ff164324 AG |
305 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, |
306 | const struct cpumask *andmask, | |
307 | unsigned int *apicid); | |
e2780a68 IM |
308 | |
309 | /* ipi */ | |
539da787 | 310 | void (*send_IPI)(int cpu, int vector); |
e2780a68 IM |
311 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); |
312 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
313 | int vector); | |
314 | void (*send_IPI_allbutself)(int vector); | |
315 | void (*send_IPI_all)(int vector); | |
316 | void (*send_IPI_self)(int vector); | |
317 | ||
318 | /* wakeup_secondary_cpu */ | |
1f5bcabf | 319 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 | 320 | |
e2780a68 IM |
321 | void (*inquire_remote_apic)(int apicid); |
322 | ||
323 | /* apic ops */ | |
324 | u32 (*read)(u32 reg); | |
325 | void (*write)(u32 reg, u32 v); | |
2a43195d MT |
326 | /* |
327 | * ->eoi_write() has the same signature as ->write(). | |
328 | * | |
329 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
330 | * callback value. Kernel can override ->eoi_write() and fall back | |
331 | * on write for EOI. | |
332 | */ | |
333 | void (*eoi_write)(u32 reg, u32 v); | |
8ca22552 | 334 | void (*native_eoi_write)(u32 reg, u32 v); |
e2780a68 IM |
335 | u64 (*icr_read)(void); |
336 | void (*icr_write)(u32 low, u32 high); | |
337 | void (*wait_icr_idle)(void); | |
338 | u32 (*safe_wait_icr_idle)(void); | |
acb8bc09 TH |
339 | |
340 | #ifdef CONFIG_X86_32 | |
341 | /* | |
342 | * Called very early during boot from get_smp_config(). It should | |
343 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
344 | * initialized before this function is called. | |
345 | * | |
346 | * If logical apicid can't be determined that early, the function | |
347 | * may return BAD_APICID. Logical apicid will be configured after | |
348 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
349 | * won't be applied properly during early boot in this case. | |
350 | */ | |
351 | int (*x86_32_early_logical_apicid)(int cpu); | |
352 | #endif | |
e2780a68 IM |
353 | }; |
354 | ||
0917c01f IM |
355 | /* |
356 | * Pointer to the local APIC driver in use on this system (there's | |
357 | * always just one such driver in use - the kernel decides via an | |
358 | * early probing process which one it picks - and then sticks to it): | |
359 | */ | |
be163a15 | 360 | extern struct apic *apic; |
0917c01f | 361 | |
107e0e0c SS |
362 | /* |
363 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
364 | * section. So the order is important and enforced by the ordering | |
365 | * of different apic driver files in the Makefile. | |
366 | * | |
367 | * For the files having two apic drivers, we use apic_drivers() | |
368 | * to enforce the order with in them. | |
369 | */ | |
370 | #define apic_driver(sym) \ | |
75fdd155 | 371 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
372 | __aligned(sizeof(struct apic *)) \ |
373 | __section(.apicdrivers) = { &sym } | |
374 | ||
375 | #define apic_drivers(sym1, sym2) \ | |
376 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
377 | __aligned(sizeof(struct apic *)) \ | |
378 | __section(.apicdrivers) = { &sym1, &sym2 } | |
379 | ||
380 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
381 | ||
0917c01f IM |
382 | /* |
383 | * APIC functionality to boot other CPUs - only used on SMP: | |
384 | */ | |
385 | #ifdef CONFIG_SMP | |
2b6163bf | 386 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); |
0917c01f | 387 | #endif |
e2780a68 | 388 | |
d674cd19 | 389 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 390 | |
e2780a68 IM |
391 | static inline u32 apic_read(u32 reg) |
392 | { | |
393 | return apic->read(reg); | |
394 | } | |
395 | ||
396 | static inline void apic_write(u32 reg, u32 val) | |
397 | { | |
398 | apic->write(reg, val); | |
399 | } | |
400 | ||
2a43195d MT |
401 | static inline void apic_eoi(void) |
402 | { | |
403 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
404 | } | |
405 | ||
e2780a68 IM |
406 | static inline u64 apic_icr_read(void) |
407 | { | |
408 | return apic->icr_read(); | |
409 | } | |
410 | ||
411 | static inline void apic_icr_write(u32 low, u32 high) | |
412 | { | |
413 | apic->icr_write(low, high); | |
414 | } | |
415 | ||
416 | static inline void apic_wait_icr_idle(void) | |
417 | { | |
418 | apic->wait_icr_idle(); | |
419 | } | |
420 | ||
421 | static inline u32 safe_apic_wait_icr_idle(void) | |
422 | { | |
423 | return apic->safe_wait_icr_idle(); | |
424 | } | |
425 | ||
1551df64 MT |
426 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
427 | ||
d674cd19 CG |
428 | #else /* CONFIG_X86_LOCAL_APIC */ |
429 | ||
430 | static inline u32 apic_read(u32 reg) { return 0; } | |
431 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 432 | static inline void apic_eoi(void) { } |
d674cd19 CG |
433 | static inline u64 apic_icr_read(void) { return 0; } |
434 | static inline void apic_icr_write(u32 low, u32 high) { } | |
435 | static inline void apic_wait_icr_idle(void) { } | |
436 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 437 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
438 | |
439 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 IM |
440 | |
441 | static inline void ack_APIC_irq(void) | |
442 | { | |
443 | /* | |
444 | * ack_APIC_irq() actually gets compiled as a single instruction | |
445 | * ... yummie. | |
446 | */ | |
2a43195d | 447 | apic_eoi(); |
e2780a68 IM |
448 | } |
449 | ||
450 | static inline unsigned default_get_apic_id(unsigned long x) | |
451 | { | |
452 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
453 | ||
42937e81 | 454 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
455 | return (x >> 24) & 0xFF; |
456 | else | |
457 | return (x >> 24) & 0x0F; | |
458 | } | |
459 | ||
460 | /* | |
6ab1b27c | 461 | * Warm reset vector position: |
e2780a68 | 462 | */ |
6ab1b27c DR |
463 | #define TRAMPOLINE_PHYS_LOW 0x467 |
464 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
e2780a68 | 465 | |
2b6163bf | 466 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
467 | extern void apic_send_IPI_self(int vector); |
468 | ||
e2780a68 IM |
469 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
470 | ||
471 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 472 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
473 | #endif |
474 | ||
838312be | 475 | extern void generic_bigsmp_probe(void); |
e2780a68 IM |
476 | |
477 | ||
478 | #ifdef CONFIG_X86_LOCAL_APIC | |
479 | ||
480 | #include <asm/smp.h> | |
481 | ||
482 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
483 | ||
484 | static inline const struct cpumask *default_target_cpus(void) | |
485 | { | |
486 | #ifdef CONFIG_SMP | |
487 | return cpu_online_mask; | |
488 | #else | |
489 | return cpumask_of(0); | |
490 | #endif | |
491 | } | |
492 | ||
bf721d3a AG |
493 | static inline const struct cpumask *online_target_cpus(void) |
494 | { | |
495 | return cpu_online_mask; | |
496 | } | |
497 | ||
0816b0f0 | 498 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 IM |
499 | |
500 | ||
501 | static inline unsigned int read_apic_id(void) | |
502 | { | |
503 | unsigned int reg; | |
504 | ||
505 | reg = apic_read(APIC_ID); | |
506 | ||
507 | return apic->get_apic_id(reg); | |
508 | } | |
509 | ||
fa63030e DB |
510 | static inline int default_apic_id_valid(int apicid) |
511 | { | |
b7157acf | 512 | return (apicid < 255); |
fa63030e DB |
513 | } |
514 | ||
a491cc90 JL |
515 | extern int default_acpi_madt_oem_check(char *, char *); |
516 | ||
e2780a68 IM |
517 | extern void default_setup_apic_routing(void); |
518 | ||
9844ab11 CG |
519 | extern struct apic apic_noop; |
520 | ||
e2780a68 | 521 | #ifdef CONFIG_X86_32 |
2c1b284e | 522 | |
acb8bc09 TH |
523 | static inline int noop_x86_32_early_logical_apicid(int cpu) |
524 | { | |
525 | return BAD_APICID; | |
526 | } | |
527 | ||
e2780a68 IM |
528 | /* |
529 | * Set up the logical destination ID. | |
530 | * | |
531 | * Intel recommends to set DFR, LDR and TPR before enabling | |
532 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
533 | * document number 292116). So here it goes... | |
534 | */ | |
535 | extern void default_init_apic_ldr(void); | |
536 | ||
537 | static inline int default_apic_id_registered(void) | |
538 | { | |
539 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
540 | } | |
541 | ||
f56e5034 YL |
542 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
543 | { | |
544 | return cpuid_apic >> index_msb; | |
545 | } | |
546 | ||
f56e5034 YL |
547 | #endif |
548 | ||
ff164324 | 549 | static inline int |
a5a39156 AG |
550 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
551 | const struct cpumask *andmask, | |
552 | unsigned int *apicid) | |
e2780a68 | 553 | { |
a5a39156 AG |
554 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & |
555 | cpumask_bits(andmask)[0] & | |
556 | cpumask_bits(cpu_online_mask)[0] & | |
557 | APIC_ALL_CPUS; | |
558 | ||
ff164324 AG |
559 | if (likely(cpu_mask)) { |
560 | *apicid = (unsigned int)cpu_mask; | |
561 | return 0; | |
562 | } else { | |
563 | return -EINVAL; | |
564 | } | |
565 | } | |
566 | ||
ff164324 | 567 | extern int |
6398268d | 568 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
569 | const struct cpumask *andmask, |
570 | unsigned int *apicid); | |
6398268d | 571 | |
b39f25a8 | 572 | static inline void |
1ac322d0 SS |
573 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, |
574 | const struct cpumask *mask) | |
9d8e1066 AG |
575 | { |
576 | /* Careful. Some cpus do not strictly honor the set of cpus | |
577 | * specified in the interrupt destination when using lowest | |
578 | * priority interrupt delivery mode. | |
579 | * | |
580 | * In particular there was a hyperthreading cpu observed to | |
581 | * deliver interrupts to the wrong hyperthread when only one | |
582 | * hyperthread was specified in the interrupt desitination. | |
583 | */ | |
584 | cpumask_clear(retmask); | |
585 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
586 | } | |
587 | ||
b39f25a8 | 588 | static inline void |
1ac322d0 SS |
589 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, |
590 | const struct cpumask *mask) | |
9d8e1066 AG |
591 | { |
592 | cpumask_copy(retmask, cpumask_of(cpu)); | |
593 | } | |
594 | ||
7abc0753 | 595 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
e2780a68 | 596 | { |
7abc0753 | 597 | return physid_isset(apicid, *map); |
e2780a68 IM |
598 | } |
599 | ||
7abc0753 | 600 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
e2780a68 | 601 | { |
7abc0753 | 602 | *retmap = *phys_map; |
e2780a68 IM |
603 | } |
604 | ||
e2780a68 IM |
605 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
606 | { | |
607 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
608 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
609 | else | |
610 | return BAD_APICID; | |
611 | } | |
612 | ||
613 | static inline int | |
e11dadab | 614 | __default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 615 | { |
e11dadab | 616 | return physid_isset(phys_apicid, phys_cpu_present_map); |
e2780a68 IM |
617 | } |
618 | ||
619 | #ifdef CONFIG_X86_32 | |
620 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
621 | { | |
622 | return __default_cpu_present_to_apicid(mps_cpu); | |
623 | } | |
624 | ||
625 | static inline int | |
e11dadab | 626 | default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 627 | { |
e11dadab | 628 | return __default_check_phys_apicid_present(phys_apicid); |
e2780a68 IM |
629 | } |
630 | #else | |
631 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 632 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
633 | #endif |
634 | ||
e2780a68 | 635 | #endif /* CONFIG_X86_LOCAL_APIC */ |
eddc0e92 SA |
636 | extern void irq_enter(void); |
637 | extern void irq_exit(void); | |
638 | ||
639 | static inline void entering_irq(void) | |
640 | { | |
641 | irq_enter(); | |
eddc0e92 SA |
642 | } |
643 | ||
644 | static inline void entering_ack_irq(void) | |
645 | { | |
eddc0e92 | 646 | entering_irq(); |
7834c103 | 647 | ack_APIC_irq(); |
eddc0e92 SA |
648 | } |
649 | ||
6dc17876 TG |
650 | static inline void ipi_entering_ack_irq(void) |
651 | { | |
6dc17876 | 652 | irq_enter(); |
b0f48706 | 653 | ack_APIC_irq(); |
6dc17876 TG |
654 | } |
655 | ||
eddc0e92 SA |
656 | static inline void exiting_irq(void) |
657 | { | |
658 | irq_exit(); | |
659 | } | |
660 | ||
661 | static inline void exiting_ack_irq(void) | |
662 | { | |
eddc0e92 | 663 | ack_APIC_irq(); |
b0f48706 | 664 | irq_exit(); |
eddc0e92 | 665 | } |
e2780a68 | 666 | |
17405453 YY |
667 | extern void ioapic_zap_locks(void); |
668 | ||
1965aae3 | 669 | #endif /* _ASM_X86_APIC_H */ |