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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
3637efb0 | 44 | #include <linux/jump_label.h> |
e9eee03e | 45 | |
3f5a7896 | 46 | #include <asm/intel-family.h> |
d88203d1 | 47 | #include <asm/processor.h> |
95927475 | 48 | #include <asm/traps.h> |
375074cc | 49 | #include <asm/tlbflush.h> |
e9eee03e IM |
50 | #include <asm/mce.h> |
51 | #include <asm/msr.h> | |
1da177e4 | 52 | |
bd19a5e6 | 53 | #include "mce-internal.h" |
711c2e48 | 54 | |
93b62c3c | 55 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 56 | |
9a7783d0 | 57 | #define mce_log_get_idx_check(p) \ |
e90328b8 | 58 | ({ \ |
f78f5b90 PM |
59 | RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \ |
60 | !lockdep_is_held(&mce_chrdev_read_mutex), \ | |
3959df1d | 61 | "suspicious mce_log_get_idx_check() usage"); \ |
e90328b8 PM |
62 | smp_load_acquire(&(p)); \ |
63 | }) | |
f56e8a07 | 64 | |
8968f9d3 HS |
65 | #define CREATE_TRACE_POINTS |
66 | #include <trace/events/mce.h> | |
67 | ||
3f2f0680 | 68 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 69 | |
01ca79f1 AK |
70 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
71 | ||
1462594b | 72 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 73 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 74 | |
d203f0b8 | 75 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 76 | .bootlog = -1, |
d203f0b8 BP |
77 | /* |
78 | * Tolerant levels: | |
79 | * 0: always panic on uncorrected errors, log corrected errors | |
80 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
81 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
82 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
83 | */ | |
84c2559d BP |
84 | .tolerant = 1, |
85 | .monarch_timeout = -1 | |
d203f0b8 BP |
86 | }; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
0644414e NR |
98 | /* |
99 | * MCA banks polled by the period polling timer for corrected events. | |
100 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
101 | */ | |
ee031c31 AK |
102 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
103 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
104 | }; | |
105 | ||
c3d1fb56 NR |
106 | /* |
107 | * MCA banks controlled through firmware first for corrected errors. | |
108 | * This is a global list of banks for which we won't enable CMCI and we | |
109 | * won't poll. Firmware controls these banks and is responsible for | |
110 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
111 | * errors are still notified through a machine check. | |
112 | */ | |
113 | mce_banks_t mce_banks_ce_disabled; | |
114 | ||
061120ae CG |
115 | static struct work_struct mce_work; |
116 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 117 | |
61b0fccd TL |
118 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
119 | ||
3653ada5 BP |
120 | /* |
121 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
122 | * MCE errors in a human-readable form. | |
123 | */ | |
648ed940 | 124 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 125 | |
b5f2fa4e AK |
126 | /* Do initial initialization of a struct mce */ |
127 | void mce_setup(struct mce *m) | |
128 | { | |
129 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 130 | m->cpu = m->extcpu = smp_processor_id(); |
8ee08347 AK |
131 | /* We hope get_seconds stays lockless */ |
132 | m->time = get_seconds(); | |
133 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
134 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 135 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
136 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
137 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
3f5a7896 TL |
138 | |
139 | if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) | |
140 | rdmsrl(MSR_PPIN, m->ppin); | |
b5f2fa4e AK |
141 | } |
142 | ||
ea149b36 AK |
143 | DEFINE_PER_CPU(struct mce, injectm); |
144 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
145 | ||
1da177e4 LT |
146 | /* |
147 | * Lockless MCE logging infrastructure. | |
148 | * This avoids deadlocks on printk locks without having to break locks. Also | |
149 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
150 | */ | |
151 | ||
231fd906 | 152 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
153 | .signature = MCE_LOG_SIGNATURE, |
154 | .len = MCE_LOG_LEN, | |
155 | .recordlen = sizeof(struct mce), | |
d88203d1 | 156 | }; |
1da177e4 LT |
157 | |
158 | void mce_log(struct mce *mce) | |
159 | { | |
160 | unsigned next, entry; | |
e9eee03e | 161 | |
8968f9d3 HS |
162 | /* Emit the trace record: */ |
163 | trace_mce_record(mce); | |
164 | ||
f29a7aff CG |
165 | if (!mce_gen_pool_add(mce)) |
166 | irq_work_queue(&mce_irq_work); | |
f0cb5452 | 167 | |
7644143c | 168 | wmb(); |
1da177e4 | 169 | for (;;) { |
9a7783d0 | 170 | entry = mce_log_get_idx_check(mcelog.next); |
673242c1 | 171 | for (;;) { |
696e409d | 172 | |
e9eee03e IM |
173 | /* |
174 | * When the buffer fills up discard new entries. | |
175 | * Assume that the earlier errors are the more | |
176 | * interesting ones: | |
177 | */ | |
673242c1 | 178 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
179 | set_bit(MCE_OVERFLOW, |
180 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
181 | return; |
182 | } | |
e9eee03e | 183 | /* Old left over entry. Skip: */ |
673242c1 AK |
184 | if (mcelog.entry[entry].finished) { |
185 | entry++; | |
186 | continue; | |
187 | } | |
7644143c | 188 | break; |
1da177e4 | 189 | } |
1da177e4 LT |
190 | smp_rmb(); |
191 | next = entry + 1; | |
192 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
193 | break; | |
194 | } | |
195 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 196 | wmb(); |
1da177e4 | 197 | mcelog.entry[entry].finished = 1; |
7644143c | 198 | wmb(); |
1da177e4 | 199 | |
1020bcbc | 200 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
201 | } |
202 | ||
a79da384 | 203 | void mce_inject_log(struct mce *m) |
09371957 | 204 | { |
a79da384 BP |
205 | mutex_lock(&mce_chrdev_read_mutex); |
206 | mce_log(m); | |
207 | mutex_unlock(&mce_chrdev_read_mutex); | |
09371957 | 208 | } |
a79da384 | 209 | EXPORT_SYMBOL_GPL(mce_inject_log); |
09371957 | 210 | |
fd4cf79f | 211 | static struct notifier_block mce_srao_nb; |
09371957 | 212 | |
cd9c57ca BP |
213 | static atomic_t num_notifiers; |
214 | ||
3653ada5 BP |
215 | void mce_register_decode_chain(struct notifier_block *nb) |
216 | { | |
cd9c57ca BP |
217 | atomic_inc(&num_notifiers); |
218 | ||
fd4cf79f CG |
219 | /* Ensure SRAO notifier has the highest priority in the decode chain. */ |
220 | if (nb != &mce_srao_nb && nb->priority == INT_MAX) | |
221 | nb->priority -= 1; | |
222 | ||
3653ada5 BP |
223 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); |
224 | } | |
225 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
226 | ||
227 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
228 | { | |
cd9c57ca BP |
229 | atomic_dec(&num_notifiers); |
230 | ||
3653ada5 BP |
231 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); |
232 | } | |
233 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
234 | ||
a9750a31 YG |
235 | static inline u32 ctl_reg(int bank) |
236 | { | |
237 | return MSR_IA32_MCx_CTL(bank); | |
238 | } | |
239 | ||
240 | static inline u32 status_reg(int bank) | |
241 | { | |
242 | return MSR_IA32_MCx_STATUS(bank); | |
243 | } | |
244 | ||
245 | static inline u32 addr_reg(int bank) | |
246 | { | |
247 | return MSR_IA32_MCx_ADDR(bank); | |
248 | } | |
249 | ||
250 | static inline u32 misc_reg(int bank) | |
251 | { | |
252 | return MSR_IA32_MCx_MISC(bank); | |
253 | } | |
254 | ||
255 | static inline u32 smca_ctl_reg(int bank) | |
256 | { | |
257 | return MSR_AMD64_SMCA_MCx_CTL(bank); | |
258 | } | |
259 | ||
260 | static inline u32 smca_status_reg(int bank) | |
261 | { | |
262 | return MSR_AMD64_SMCA_MCx_STATUS(bank); | |
263 | } | |
264 | ||
265 | static inline u32 smca_addr_reg(int bank) | |
266 | { | |
267 | return MSR_AMD64_SMCA_MCx_ADDR(bank); | |
268 | } | |
269 | ||
270 | static inline u32 smca_misc_reg(int bank) | |
271 | { | |
272 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
273 | } | |
274 | ||
275 | struct mca_msr_regs msr_ops = { | |
276 | .ctl = ctl_reg, | |
277 | .status = status_reg, | |
278 | .addr = addr_reg, | |
279 | .misc = misc_reg | |
280 | }; | |
281 | ||
cd9c57ca | 282 | static void __print_mce(struct mce *m) |
1da177e4 | 283 | { |
cd9c57ca BP |
284 | pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", |
285 | m->extcpu, | |
286 | (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), | |
287 | m->mcgstatus, m->bank, m->status); | |
f436f8bb | 288 | |
65ea5b03 | 289 | if (m->ip) { |
a2d7b0d4 | 290 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb | 291 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
cd9c57ca | 292 | m->cs, m->ip); |
f436f8bb | 293 | |
1da177e4 | 294 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 295 | print_symbol("{%s}", m->ip); |
f436f8bb | 296 | pr_cont("\n"); |
1da177e4 | 297 | } |
f436f8bb | 298 | |
a2d7b0d4 | 299 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 300 | if (m->addr) |
f436f8bb | 301 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 302 | if (m->misc) |
f436f8bb | 303 | pr_cont("MISC %llx ", m->misc); |
549d042d | 304 | |
4b711f92 YG |
305 | if (mce_flags.smca) { |
306 | if (m->synd) | |
307 | pr_cont("SYND %llx ", m->synd); | |
308 | if (m->ipid) | |
309 | pr_cont("IPID %llx ", m->ipid); | |
310 | } | |
311 | ||
f436f8bb | 312 | pr_cont("\n"); |
506ed6b5 AK |
313 | /* |
314 | * Note this output is parsed by external tools and old fields | |
315 | * should not be changed. | |
316 | */ | |
881e23e5 | 317 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
318 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
319 | cpu_data(m->extcpu).microcode); | |
cd9c57ca BP |
320 | } |
321 | ||
322 | static void print_mce(struct mce *m) | |
323 | { | |
324 | int ret = 0; | |
325 | ||
326 | __print_mce(m); | |
f436f8bb IM |
327 | |
328 | /* | |
329 | * Print out human-readable details about the MCE error, | |
fb253195 | 330 | * (if the CPU has an implementation for that) |
f436f8bb | 331 | */ |
dffa4b2f BP |
332 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
333 | if (ret == NOTIFY_STOP) | |
334 | return; | |
335 | ||
336 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
337 | } |
338 | ||
f94b61c2 AK |
339 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
340 | ||
c7c9b392 | 341 | static atomic_t mce_panicked; |
f94b61c2 | 342 | |
bf783f9f | 343 | static int fake_panic; |
c7c9b392 | 344 | static atomic_t mce_fake_panicked; |
bf783f9f | 345 | |
f94b61c2 AK |
346 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
347 | static void wait_for_panic(void) | |
348 | { | |
349 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 350 | |
f94b61c2 AK |
351 | preempt_disable(); |
352 | local_irq_enable(); | |
353 | while (timeout-- > 0) | |
354 | udelay(1); | |
29b0f591 | 355 | if (panic_timeout == 0) |
7af19e4a | 356 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
357 | panic("Panicing machine check CPU died"); |
358 | } | |
359 | ||
6c80f87e | 360 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 361 | { |
5541c93c TL |
362 | int apei_err = 0; |
363 | struct llist_node *pending; | |
364 | struct mce_evt_llist *l; | |
e02e68d3 | 365 | |
bf783f9f HY |
366 | if (!fake_panic) { |
367 | /* | |
368 | * Make sure only one CPU runs in machine check panic | |
369 | */ | |
c7c9b392 | 370 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
371 | wait_for_panic(); |
372 | barrier(); | |
f94b61c2 | 373 | |
bf783f9f HY |
374 | bust_spinlocks(1); |
375 | console_verbose(); | |
376 | } else { | |
377 | /* Don't log too much for fake panic */ | |
c7c9b392 | 378 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
379 | return; |
380 | } | |
5541c93c | 381 | pending = mce_gen_pool_prepare_records(); |
a0189c70 | 382 | /* First print corrected ones that are still unlogged */ |
5541c93c TL |
383 | llist_for_each_entry(l, pending, llnode) { |
384 | struct mce *m = &l->mce; | |
482908b4 | 385 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 386 | print_mce(m); |
482908b4 HY |
387 | if (!apei_err) |
388 | apei_err = apei_write_mce(m); | |
389 | } | |
a0189c70 AK |
390 | } |
391 | /* Now print uncorrected but with the final one last */ | |
5541c93c TL |
392 | llist_for_each_entry(l, pending, llnode) { |
393 | struct mce *m = &l->mce; | |
77e26cca HS |
394 | if (!(m->status & MCI_STATUS_UC)) |
395 | continue; | |
5541c93c | 396 | if (!final || mce_cmp(m, final)) { |
77e26cca | 397 | print_mce(m); |
482908b4 HY |
398 | if (!apei_err) |
399 | apei_err = apei_write_mce(m); | |
400 | } | |
1da177e4 | 401 | } |
482908b4 | 402 | if (final) { |
77e26cca | 403 | print_mce(final); |
482908b4 HY |
404 | if (!apei_err) |
405 | apei_err = apei_write_mce(final); | |
406 | } | |
3c079792 | 407 | if (cpu_missing) |
a2d7b0d4 | 408 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 409 | if (exp) |
a2d7b0d4 | 410 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
411 | if (!fake_panic) { |
412 | if (panic_timeout == 0) | |
7af19e4a | 413 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
414 | panic(msg); |
415 | } else | |
a2d7b0d4 | 416 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 417 | } |
1da177e4 | 418 | |
ea149b36 AK |
419 | /* Support code for software error injection */ |
420 | ||
421 | static int msr_to_offset(u32 msr) | |
422 | { | |
0a3aee0d | 423 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 424 | |
84c2559d | 425 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 426 | return offsetof(struct mce, ip); |
d9d73fcc | 427 | if (msr == msr_ops.status(bank)) |
ea149b36 | 428 | return offsetof(struct mce, status); |
d9d73fcc | 429 | if (msr == msr_ops.addr(bank)) |
ea149b36 | 430 | return offsetof(struct mce, addr); |
d9d73fcc | 431 | if (msr == msr_ops.misc(bank)) |
ea149b36 AK |
432 | return offsetof(struct mce, misc); |
433 | if (msr == MSR_IA32_MCG_STATUS) | |
434 | return offsetof(struct mce, mcgstatus); | |
435 | return -1; | |
436 | } | |
437 | ||
5f8c1a54 AK |
438 | /* MSR access wrappers used for error injection */ |
439 | static u64 mce_rdmsrl(u32 msr) | |
440 | { | |
441 | u64 v; | |
11868a2d | 442 | |
0a3aee0d | 443 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 444 | int offset = msr_to_offset(msr); |
11868a2d | 445 | |
ea149b36 AK |
446 | if (offset < 0) |
447 | return 0; | |
89cbc767 | 448 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 449 | } |
11868a2d IM |
450 | |
451 | if (rdmsrl_safe(msr, &v)) { | |
38c54ccb | 452 | WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); |
11868a2d IM |
453 | /* |
454 | * Return zero in case the access faulted. This should | |
455 | * not happen normally but can happen if the CPU does | |
456 | * something weird, or if the code is buggy. | |
457 | */ | |
458 | v = 0; | |
459 | } | |
460 | ||
5f8c1a54 AK |
461 | return v; |
462 | } | |
463 | ||
464 | static void mce_wrmsrl(u32 msr, u64 v) | |
465 | { | |
0a3aee0d | 466 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 467 | int offset = msr_to_offset(msr); |
11868a2d | 468 | |
ea149b36 | 469 | if (offset >= 0) |
89cbc767 | 470 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
471 | return; |
472 | } | |
5f8c1a54 AK |
473 | wrmsrl(msr, v); |
474 | } | |
475 | ||
b8325c5b HS |
476 | /* |
477 | * Collect all global (w.r.t. this processor) status about this machine | |
478 | * check into our "mce" struct so that we can use it later to assess | |
479 | * the severity of the problem as we read per-bank specific details. | |
480 | */ | |
481 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
482 | { | |
483 | mce_setup(m); | |
484 | ||
485 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
486 | if (regs) { | |
487 | /* | |
488 | * Get the address of the instruction at the time of | |
489 | * the machine check error. | |
490 | */ | |
491 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
492 | m->ip = regs->ip; | |
493 | m->cs = regs->cs; | |
a129a7c8 AK |
494 | |
495 | /* | |
496 | * When in VM86 mode make the cs look like ring 3 | |
497 | * always. This is a lie, but it's better than passing | |
498 | * the additional vm86 bit around everywhere. | |
499 | */ | |
500 | if (v8086_mode(regs)) | |
501 | m->cs |= 3; | |
b8325c5b HS |
502 | } |
503 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
504 | if (mca_cfg.rip_msr) |
505 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
506 | } |
507 | } | |
508 | ||
88ccbedd | 509 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 510 | { |
1462594b | 511 | if (mca_cfg.disabled) |
5b4408fd | 512 | return 0; |
3d1712c9 | 513 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
514 | } |
515 | ||
9b1beaf2 AK |
516 | static void mce_schedule_work(void) |
517 | { | |
a2c2727d | 518 | if (!mce_gen_pool_empty()) |
061120ae | 519 | schedule_work(&mce_work); |
9b1beaf2 AK |
520 | } |
521 | ||
b77e70bf | 522 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 523 | { |
9ff36ee9 | 524 | mce_notify_irq(); |
9b1beaf2 | 525 | mce_schedule_work(); |
ccc3c319 | 526 | } |
ccc3c319 AK |
527 | |
528 | static void mce_report_event(struct pt_regs *regs) | |
529 | { | |
530 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 531 | mce_notify_irq(); |
9b1beaf2 AK |
532 | /* |
533 | * Triggering the work queue here is just an insurance | |
534 | * policy in case the syscall exit notify handler | |
535 | * doesn't run soon enough or ends up running on the | |
536 | * wrong CPU (can happen when audit sleeps) | |
537 | */ | |
538 | mce_schedule_work(); | |
ccc3c319 AK |
539 | return; |
540 | } | |
541 | ||
061120ae | 542 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
543 | } |
544 | ||
feab21f8 BP |
545 | /* |
546 | * Check if the address reported by the CPU is in a format we can parse. | |
547 | * It would be possible to add code for most other cases, but all would | |
548 | * be somewhat complicated (e.g. segment offset would require an instruction | |
549 | * parser). So only support physical addresses up to page granuality for now. | |
550 | */ | |
551 | static int mce_usable_address(struct mce *m) | |
552 | { | |
553 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
554 | return 0; | |
555 | ||
556 | /* Checks after this one are Intel-specific: */ | |
557 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
558 | return 1; | |
559 | ||
560 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) | |
561 | return 0; | |
562 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) | |
563 | return 0; | |
564 | return 1; | |
565 | } | |
566 | ||
fd4cf79f CG |
567 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
568 | void *data) | |
569 | { | |
570 | struct mce *mce = (struct mce *)data; | |
571 | unsigned long pfn; | |
572 | ||
573 | if (!mce) | |
574 | return NOTIFY_DONE; | |
575 | ||
c0ec382e | 576 | if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { |
fd4cf79f CG |
577 | pfn = mce->addr >> PAGE_SHIFT; |
578 | memory_failure(pfn, MCE_VECTOR, 0); | |
579 | } | |
580 | ||
581 | return NOTIFY_OK; | |
ccc3c319 | 582 | } |
fd4cf79f CG |
583 | static struct notifier_block mce_srao_nb = { |
584 | .notifier_call = srao_decode_notifier, | |
585 | .priority = INT_MAX, | |
586 | }; | |
ccc3c319 | 587 | |
cd9c57ca BP |
588 | static int mce_default_notifier(struct notifier_block *nb, unsigned long val, |
589 | void *data) | |
590 | { | |
591 | struct mce *m = (struct mce *)data; | |
592 | ||
593 | if (!m) | |
594 | return NOTIFY_DONE; | |
595 | ||
596 | /* | |
597 | * Run the default notifier if we have only the SRAO | |
598 | * notifier and us registered. | |
599 | */ | |
600 | if (atomic_read(&num_notifiers) > 2) | |
601 | return NOTIFY_DONE; | |
602 | ||
603 | __print_mce(m); | |
604 | ||
605 | return NOTIFY_DONE; | |
606 | } | |
607 | ||
608 | static struct notifier_block mce_default_nb = { | |
609 | .notifier_call = mce_default_notifier, | |
610 | /* lowest prio, we want it to run last. */ | |
611 | .priority = 0, | |
612 | }; | |
613 | ||
85f92694 TL |
614 | /* |
615 | * Read ADDR and MISC registers. | |
616 | */ | |
617 | static void mce_read_aux(struct mce *m, int i) | |
618 | { | |
619 | if (m->status & MCI_STATUS_MISCV) | |
d9d73fcc | 620 | m->misc = mce_rdmsrl(msr_ops.misc(i)); |
db819d60 | 621 | |
85f92694 | 622 | if (m->status & MCI_STATUS_ADDRV) { |
d9d73fcc | 623 | m->addr = mce_rdmsrl(msr_ops.addr(i)); |
85f92694 TL |
624 | |
625 | /* | |
626 | * Mask the reported address by the reported granularity. | |
627 | */ | |
1462594b | 628 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
629 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
630 | m->addr >>= shift; | |
631 | m->addr <<= shift; | |
632 | } | |
4f29b73b YG |
633 | |
634 | /* | |
635 | * Extract [55:<lsb>] where lsb is the least significant | |
636 | * *valid* bit of the address bits. | |
637 | */ | |
638 | if (mce_flags.smca) { | |
639 | u8 lsb = (m->addr >> 56) & 0x3f; | |
640 | ||
641 | m->addr &= GENMASK_ULL(55, lsb); | |
642 | } | |
85f92694 | 643 | } |
db819d60 | 644 | |
5828c46f YG |
645 | if (mce_flags.smca) { |
646 | m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); | |
647 | ||
648 | if (m->status & MCI_STATUS_SYNDV) | |
649 | m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); | |
650 | } | |
85f92694 TL |
651 | } |
652 | ||
fa92c586 CY |
653 | static bool memory_error(struct mce *m) |
654 | { | |
655 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
656 | ||
657 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
db548a28 BP |
658 | /* ErrCodeExt[20:16] */ |
659 | u8 xec = (m->status >> 16) & 0x1f; | |
660 | ||
661 | return (xec == 0x0 || xec == 0x8); | |
fa92c586 CY |
662 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { |
663 | /* | |
664 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
665 | * | |
666 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
667 | * indicating a memory error. Bit 8 is used for indicating a | |
668 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
669 | * is used for indicating a `generic' cache hierarchy error | |
670 | * But we can't just blindly check the above bits, because if | |
671 | * bit 11 is set, then it is a bus/interconnect error - and | |
672 | * either way the above bits just gives more detail on what | |
673 | * bus/interconnect error happened. Note that bit 12 can be | |
674 | * ignored, as it's the "filter" bit. | |
675 | */ | |
676 | return (m->status & 0xef80) == BIT(7) || | |
677 | (m->status & 0xef00) == BIT(8) || | |
678 | (m->status & 0xeffc) == 0xc; | |
679 | } | |
680 | ||
681 | return false; | |
682 | } | |
683 | ||
ca84f696 AK |
684 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
685 | ||
d88203d1 | 686 | /* |
b79109c3 AK |
687 | * Poll for corrected events or events that happened before reset. |
688 | * Those are just logged through /dev/mcelog. | |
689 | * | |
690 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
691 | * |
692 | * Note: spec recommends to panic for fatal unsignalled | |
693 | * errors here. However this would be quite problematic -- | |
694 | * we would need to reimplement the Monarch handling and | |
695 | * it would mess up the exclusion between exception handler | |
696 | * and poll hander -- * so we skip this for now. | |
697 | * These cases should not happen anyways, or only when the CPU | |
698 | * is already totally * confused. In this case it's likely it will | |
699 | * not fully execute the machine check handler either. | |
b79109c3 | 700 | */ |
3f2f0680 | 701 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 702 | { |
8b38937b | 703 | bool error_seen = false; |
b79109c3 | 704 | struct mce m; |
fa92c586 | 705 | int severity; |
b79109c3 AK |
706 | int i; |
707 | ||
c6ae41e7 | 708 | this_cpu_inc(mce_poll_count); |
ca84f696 | 709 | |
b8325c5b | 710 | mce_gather_info(&m, NULL); |
b79109c3 | 711 | |
669c00f0 BP |
712 | if (flags & MCP_TIMESTAMP) |
713 | m.tsc = rdtsc(); | |
54467353 | 714 | |
d203f0b8 | 715 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 716 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
717 | continue; |
718 | ||
719 | m.misc = 0; | |
720 | m.addr = 0; | |
721 | m.bank = i; | |
b79109c3 AK |
722 | |
723 | barrier(); | |
d9d73fcc | 724 | m.status = mce_rdmsrl(msr_ops.status(i)); |
b79109c3 AK |
725 | if (!(m.status & MCI_STATUS_VAL)) |
726 | continue; | |
727 | ||
728 | /* | |
ed7290d0 AK |
729 | * Uncorrected or signalled events are handled by the exception |
730 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
731 | * |
732 | * TBD do the same check for MCI_STATUS_EN here? | |
733 | */ | |
ed7290d0 | 734 | if (!(flags & MCP_UC) && |
1462594b | 735 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
736 | continue; |
737 | ||
8b38937b TL |
738 | error_seen = true; |
739 | ||
85f92694 | 740 | mce_read_aux(&m, i); |
b79109c3 | 741 | |
fa92c586 CY |
742 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); |
743 | ||
c0ec382e BP |
744 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) |
745 | if (m.status & MCI_STATUS_ADDRV) | |
fd4cf79f | 746 | m.severity = severity; |
fa92c586 | 747 | |
b79109c3 AK |
748 | /* |
749 | * Don't get the IP here because it's unlikely to | |
750 | * have anything to do with the actual error location. | |
751 | */ | |
8b38937b | 752 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 753 | mce_log(&m); |
c0ec382e | 754 | else if (mce_usable_address(&m)) { |
8b38937b TL |
755 | /* |
756 | * Although we skipped logging this, we still want | |
757 | * to take action. Add to the pool so the registered | |
758 | * notifiers will see it. | |
759 | */ | |
760 | if (!mce_gen_pool_add(&m)) | |
761 | mce_schedule_work(); | |
3f2f0680 | 762 | } |
b79109c3 AK |
763 | |
764 | /* | |
765 | * Clear state for this bank. | |
766 | */ | |
d9d73fcc | 767 | mce_wrmsrl(msr_ops.status(i), 0); |
b79109c3 AK |
768 | } |
769 | ||
770 | /* | |
771 | * Don't clear MCG_STATUS here because it's only defined for | |
772 | * exceptions. | |
773 | */ | |
88921be3 AK |
774 | |
775 | sync_core(); | |
3f2f0680 | 776 | |
8b38937b | 777 | return error_seen; |
b79109c3 | 778 | } |
ea149b36 | 779 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 780 | |
bd19a5e6 AK |
781 | /* |
782 | * Do a quick check if any of the events requires a panic. | |
783 | * This decides if we keep the events around or clear them. | |
784 | */ | |
61b0fccd TL |
785 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
786 | struct pt_regs *regs) | |
bd19a5e6 | 787 | { |
95022b8c | 788 | int i, ret = 0; |
17fea54b | 789 | char *tmp; |
bd19a5e6 | 790 | |
d203f0b8 | 791 | for (i = 0; i < mca_cfg.banks; i++) { |
d9d73fcc | 792 | m->status = mce_rdmsrl(msr_ops.status(i)); |
61b0fccd | 793 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 794 | __set_bit(i, validp); |
61b0fccd TL |
795 | if (quirk_no_way_out) |
796 | quirk_no_way_out(i, m, regs); | |
797 | } | |
17fea54b BP |
798 | |
799 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
800 | *msg = tmp; | |
95022b8c | 801 | ret = 1; |
17fea54b | 802 | } |
bd19a5e6 | 803 | } |
95022b8c | 804 | return ret; |
bd19a5e6 AK |
805 | } |
806 | ||
3c079792 AK |
807 | /* |
808 | * Variable to establish order between CPUs while scanning. | |
809 | * Each CPU spins initially until executing is equal its number. | |
810 | */ | |
811 | static atomic_t mce_executing; | |
812 | ||
813 | /* | |
814 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
815 | */ | |
816 | static atomic_t mce_callin; | |
817 | ||
818 | /* | |
819 | * Check if a timeout waiting for other CPUs happened. | |
820 | */ | |
6c80f87e | 821 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
822 | { |
823 | /* | |
824 | * The others already did panic for some reason. | |
825 | * Bail out like in a timeout. | |
826 | * rmb() to tell the compiler that system_state | |
827 | * might have been modified by someone else. | |
828 | */ | |
829 | rmb(); | |
c7c9b392 | 830 | if (atomic_read(&mce_panicked)) |
3c079792 | 831 | wait_for_panic(); |
84c2559d | 832 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
833 | goto out; |
834 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 835 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 836 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
837 | cpu_missing = 1; |
838 | return 1; | |
839 | } | |
840 | *t -= SPINUNIT; | |
841 | out: | |
842 | touch_nmi_watchdog(); | |
843 | return 0; | |
844 | } | |
845 | ||
846 | /* | |
847 | * The Monarch's reign. The Monarch is the CPU who entered | |
848 | * the machine check handler first. It waits for the others to | |
849 | * raise the exception too and then grades them. When any | |
850 | * error is fatal panic. Only then let the others continue. | |
851 | * | |
852 | * The other CPUs entering the MCE handler will be controlled by the | |
853 | * Monarch. They are called Subjects. | |
854 | * | |
855 | * This way we prevent any potential data corruption in a unrecoverable case | |
856 | * and also makes sure always all CPU's errors are examined. | |
857 | * | |
680b6cfd | 858 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
859 | * space (not detected by any CPUs) In this case some external agent wants |
860 | * us to shut down, so panic too. | |
861 | * | |
862 | * The other CPUs might still decide to panic if the handler happens | |
863 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
864 | * state and won't corrupt anything by itself. It's ok to let the others | |
865 | * continue for a bit first. | |
866 | * | |
867 | * All the spin loops have timeouts; when a timeout happens a CPU | |
868 | * typically elects itself to be Monarch. | |
869 | */ | |
870 | static void mce_reign(void) | |
871 | { | |
872 | int cpu; | |
873 | struct mce *m = NULL; | |
874 | int global_worst = 0; | |
875 | char *msg = NULL; | |
876 | char *nmsg = NULL; | |
877 | ||
878 | /* | |
879 | * This CPU is the Monarch and the other CPUs have run | |
880 | * through their handlers. | |
881 | * Grade the severity of the errors of all the CPUs. | |
882 | */ | |
883 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
884 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
885 | mca_cfg.tolerant, | |
e3480271 | 886 | &nmsg, true); |
3c079792 AK |
887 | if (severity > global_worst) { |
888 | msg = nmsg; | |
889 | global_worst = severity; | |
890 | m = &per_cpu(mces_seen, cpu); | |
891 | } | |
892 | } | |
893 | ||
894 | /* | |
895 | * Cannot recover? Panic here then. | |
896 | * This dumps all the mces in the log buffer and stops the | |
897 | * other CPUs. | |
898 | */ | |
d203f0b8 | 899 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 900 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
901 | |
902 | /* | |
903 | * For UC somewhere we let the CPU who detects it handle it. | |
904 | * Also must let continue the others, otherwise the handling | |
905 | * CPU could deadlock on a lock. | |
906 | */ | |
907 | ||
908 | /* | |
909 | * No machine check event found. Must be some external | |
910 | * source or one CPU is hung. Panic. | |
911 | */ | |
d203f0b8 | 912 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 913 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
914 | |
915 | /* | |
916 | * Now clear all the mces_seen so that they don't reappear on | |
917 | * the next mce. | |
918 | */ | |
919 | for_each_possible_cpu(cpu) | |
920 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
921 | } | |
922 | ||
923 | static atomic_t global_nwo; | |
924 | ||
925 | /* | |
926 | * Start of Monarch synchronization. This waits until all CPUs have | |
927 | * entered the exception handler and then determines if any of them | |
928 | * saw a fatal event that requires panic. Then it executes them | |
929 | * in the entry order. | |
930 | * TBD double check parallel CPU hotunplug | |
931 | */ | |
7fb06fc9 | 932 | static int mce_start(int *no_way_out) |
3c079792 | 933 | { |
7fb06fc9 | 934 | int order; |
3c079792 | 935 | int cpus = num_online_cpus(); |
84c2559d | 936 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 937 | |
7fb06fc9 HS |
938 | if (!timeout) |
939 | return -1; | |
3c079792 | 940 | |
7fb06fc9 | 941 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf | 942 | /* |
bf92b1fe DB |
943 | * Rely on the implied barrier below, such that global_nwo |
944 | * is updated before mce_callin. | |
184e1fdf | 945 | */ |
a95436e4 | 946 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
947 | |
948 | /* | |
949 | * Wait for everyone. | |
950 | */ | |
951 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
952 | if (mce_timed_out(&timeout, |
953 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 954 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 955 | return -1; |
3c079792 AK |
956 | } |
957 | ndelay(SPINUNIT); | |
958 | } | |
959 | ||
184e1fdf HY |
960 | /* |
961 | * mce_callin should be read before global_nwo | |
962 | */ | |
963 | smp_rmb(); | |
3c079792 | 964 | |
7fb06fc9 HS |
965 | if (order == 1) { |
966 | /* | |
967 | * Monarch: Starts executing now, the others wait. | |
968 | */ | |
3c079792 | 969 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
970 | } else { |
971 | /* | |
972 | * Subject: Now start the scanning loop one by one in | |
973 | * the original callin order. | |
974 | * This way when there are any shared banks it will be | |
975 | * only seen by one CPU before cleared, avoiding duplicates. | |
976 | */ | |
977 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
978 | if (mce_timed_out(&timeout, |
979 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
980 | atomic_set(&global_nwo, 0); |
981 | return -1; | |
982 | } | |
983 | ndelay(SPINUNIT); | |
984 | } | |
3c079792 AK |
985 | } |
986 | ||
987 | /* | |
7fb06fc9 | 988 | * Cache the global no_way_out state. |
3c079792 | 989 | */ |
7fb06fc9 HS |
990 | *no_way_out = atomic_read(&global_nwo); |
991 | ||
992 | return order; | |
3c079792 AK |
993 | } |
994 | ||
995 | /* | |
996 | * Synchronize between CPUs after main scanning loop. | |
997 | * This invokes the bulk of the Monarch processing. | |
998 | */ | |
999 | static int mce_end(int order) | |
1000 | { | |
1001 | int ret = -1; | |
84c2559d | 1002 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
1003 | |
1004 | if (!timeout) | |
1005 | goto reset; | |
1006 | if (order < 0) | |
1007 | goto reset; | |
1008 | ||
1009 | /* | |
1010 | * Allow others to run. | |
1011 | */ | |
1012 | atomic_inc(&mce_executing); | |
1013 | ||
1014 | if (order == 1) { | |
1015 | /* CHECKME: Can this race with a parallel hotplug? */ | |
1016 | int cpus = num_online_cpus(); | |
1017 | ||
1018 | /* | |
1019 | * Monarch: Wait for everyone to go through their scanning | |
1020 | * loops. | |
1021 | */ | |
1022 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
1023 | if (mce_timed_out(&timeout, |
1024 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
1025 | goto reset; |
1026 | ndelay(SPINUNIT); | |
1027 | } | |
1028 | ||
1029 | mce_reign(); | |
1030 | barrier(); | |
1031 | ret = 0; | |
1032 | } else { | |
1033 | /* | |
1034 | * Subject: Wait for Monarch to finish. | |
1035 | */ | |
1036 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
1037 | if (mce_timed_out(&timeout, |
1038 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
1039 | goto reset; |
1040 | ndelay(SPINUNIT); | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Don't reset anything. That's done by the Monarch. | |
1045 | */ | |
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | /* | |
1050 | * Reset all global state. | |
1051 | */ | |
1052 | reset: | |
1053 | atomic_set(&global_nwo, 0); | |
1054 | atomic_set(&mce_callin, 0); | |
1055 | barrier(); | |
1056 | ||
1057 | /* | |
1058 | * Let others run again. | |
1059 | */ | |
1060 | atomic_set(&mce_executing, 0); | |
1061 | return ret; | |
1062 | } | |
1063 | ||
1064 | static void mce_clear_state(unsigned long *toclear) | |
1065 | { | |
1066 | int i; | |
1067 | ||
d203f0b8 | 1068 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1069 | if (test_bit(i, toclear)) |
d9d73fcc | 1070 | mce_wrmsrl(msr_ops.status(i), 0); |
3c079792 AK |
1071 | } |
1072 | } | |
1073 | ||
b2f9d678 TL |
1074 | static int do_memory_failure(struct mce *m) |
1075 | { | |
1076 | int flags = MF_ACTION_REQUIRED; | |
1077 | int ret; | |
1078 | ||
1079 | pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); | |
1080 | if (!(m->mcgstatus & MCG_STATUS_RIPV)) | |
1081 | flags |= MF_MUST_KILL; | |
1082 | ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags); | |
1083 | if (ret) | |
1084 | pr_err("Memory error not recovered"); | |
1085 | return ret; | |
1086 | } | |
1087 | ||
b79109c3 AK |
1088 | /* |
1089 | * The actual machine check handler. This only handles real | |
1090 | * exceptions when something got corrupted coming in through int 18. | |
1091 | * | |
1092 | * This is executed in NMI context not subject to normal locking rules. This | |
1093 | * implies that most kernel services cannot be safely used. Don't even | |
1094 | * think about putting a printk in there! | |
3c079792 AK |
1095 | * |
1096 | * On Intel systems this is entered on all CPUs in parallel through | |
1097 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1098 | * so be always careful when synchronizing with others. | |
1da177e4 | 1099 | */ |
e9eee03e | 1100 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1101 | { |
1462594b | 1102 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1103 | struct mce m, *final; |
1da177e4 | 1104 | int i; |
3c079792 AK |
1105 | int worst = 0; |
1106 | int severity; | |
fead35c6 | 1107 | |
3c079792 AK |
1108 | /* |
1109 | * Establish sequential order between the CPUs entering the machine | |
1110 | * check handler. | |
1111 | */ | |
fead35c6 | 1112 | int order = -1; |
bd78432c TH |
1113 | /* |
1114 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1115 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1116 | */ |
1117 | int no_way_out = 0; | |
1118 | /* | |
1119 | * If kill_it gets set, there might be a way to recover from this | |
1120 | * error. | |
1121 | */ | |
1122 | int kill_it = 0; | |
b79109c3 | 1123 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1124 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1125 | char *msg = "Unknown"; |
fead35c6 YG |
1126 | |
1127 | /* | |
1128 | * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES | |
1129 | * on Intel. | |
1130 | */ | |
1131 | int lmce = 1; | |
1da177e4 | 1132 | |
d90167a9 AR |
1133 | /* If this CPU is offline, just bail out. */ |
1134 | if (cpu_is_offline(smp_processor_id())) { | |
1135 | u64 mcgstatus; | |
1136 | ||
1137 | mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
1138 | if (mcgstatus & MCG_STATUS_RIPV) { | |
1139 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
1140 | return; | |
1141 | } | |
1142 | } | |
1143 | ||
8c84014f | 1144 | ist_enter(regs); |
95927475 | 1145 | |
c6ae41e7 | 1146 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1147 | |
1462594b | 1148 | if (!cfg->banks) |
32561696 | 1149 | goto out; |
1da177e4 | 1150 | |
b8325c5b | 1151 | mce_gather_info(&m, regs); |
669c00f0 | 1152 | m.tsc = rdtsc(); |
b5f2fa4e | 1153 | |
89cbc767 | 1154 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1155 | *final = m; |
1156 | ||
95022b8c | 1157 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1158 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1159 | |
1da177e4 LT |
1160 | barrier(); |
1161 | ||
ed7290d0 | 1162 | /* |
a8c321fb TL |
1163 | * When no restart IP might need to kill or panic. |
1164 | * Assume the worst for now, but if we find the | |
1165 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1166 | */ |
1167 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1168 | kill_it = 1; | |
1169 | ||
3c079792 | 1170 | /* |
fead35c6 YG |
1171 | * Check if this MCE is signaled to only this logical processor, |
1172 | * on Intel only. | |
3c079792 | 1173 | */ |
fead35c6 YG |
1174 | if (m.cpuvendor == X86_VENDOR_INTEL) |
1175 | lmce = m.mcgstatus & MCG_STATUS_LMCES; | |
1176 | ||
1177 | /* | |
1178 | * Go through all banks in exclusion of the other CPUs. This way we | |
1179 | * don't report duplicated events on shared banks because the first one | |
1180 | * to see it will clear it. If this is a Local MCE, then no need to | |
1181 | * perform rendezvous. | |
1182 | */ | |
1183 | if (!lmce) | |
243d657e | 1184 | order = mce_start(&no_way_out); |
243d657e | 1185 | |
1462594b | 1186 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1187 | __clear_bit(i, toclear); |
95022b8c TL |
1188 | if (!test_bit(i, valid_banks)) |
1189 | continue; | |
cebe1820 | 1190 | if (!mce_banks[i].ctl) |
1da177e4 | 1191 | continue; |
d88203d1 TG |
1192 | |
1193 | m.misc = 0; | |
1da177e4 LT |
1194 | m.addr = 0; |
1195 | m.bank = i; | |
1da177e4 | 1196 | |
d9d73fcc | 1197 | m.status = mce_rdmsrl(msr_ops.status(i)); |
1da177e4 LT |
1198 | if ((m.status & MCI_STATUS_VAL) == 0) |
1199 | continue; | |
1200 | ||
b79109c3 | 1201 | /* |
ed7290d0 AK |
1202 | * Non uncorrected or non signaled errors are handled by |
1203 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1204 | */ |
1462594b | 1205 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1206 | !no_way_out) |
b79109c3 AK |
1207 | continue; |
1208 | ||
1209 | /* | |
1210 | * Set taint even when machine check was not enabled. | |
1211 | */ | |
373d4d09 | 1212 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1213 | |
e3480271 | 1214 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1215 | |
ed7290d0 | 1216 | /* |
e3480271 CY |
1217 | * When machine check was for corrected/deferred handler don't |
1218 | * touch, unless we're panicing. | |
ed7290d0 | 1219 | */ |
e3480271 CY |
1220 | if ((severity == MCE_KEEP_SEVERITY || |
1221 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1222 | continue; |
1223 | __set_bit(i, toclear); | |
1224 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1225 | /* |
1226 | * Machine check event was not enabled. Clear, but | |
1227 | * ignore. | |
1228 | */ | |
1229 | continue; | |
1da177e4 LT |
1230 | } |
1231 | ||
85f92694 | 1232 | mce_read_aux(&m, i); |
1da177e4 | 1233 | |
fd4cf79f CG |
1234 | /* assuming valid severity level != 0 */ |
1235 | m.severity = severity; | |
9b1beaf2 | 1236 | |
b79109c3 | 1237 | mce_log(&m); |
1da177e4 | 1238 | |
3c079792 AK |
1239 | if (severity > worst) { |
1240 | *final = m; | |
1241 | worst = severity; | |
1da177e4 | 1242 | } |
1da177e4 LT |
1243 | } |
1244 | ||
a8c321fb TL |
1245 | /* mce_clear_state will clear *final, save locally for use later */ |
1246 | m = *final; | |
1247 | ||
3c079792 AK |
1248 | if (!no_way_out) |
1249 | mce_clear_state(toclear); | |
1250 | ||
e9eee03e | 1251 | /* |
3c079792 AK |
1252 | * Do most of the synchronization with other CPUs. |
1253 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1254 | */ |
243d657e AR |
1255 | if (!lmce) { |
1256 | if (mce_end(order) < 0) | |
1257 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1258 | } else { | |
1259 | /* | |
1260 | * Local MCE skipped calling mce_reign() | |
1261 | * If we found a fatal error, we need to panic here. | |
1262 | */ | |
1263 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1264 | mce_panic("Machine check from unknown source", | |
1265 | NULL, NULL); | |
1266 | } | |
bd78432c TH |
1267 | |
1268 | /* | |
b2f9d678 TL |
1269 | * If tolerant is at an insane level we drop requests to kill |
1270 | * processes and continue even when there is no way out. | |
bd78432c | 1271 | */ |
b2f9d678 TL |
1272 | if (cfg->tolerant == 3) |
1273 | kill_it = 0; | |
1274 | else if (no_way_out) | |
1275 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
e02e68d3 | 1276 | |
3c079792 AK |
1277 | if (worst > 0) |
1278 | mce_report_event(regs); | |
5f8c1a54 | 1279 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1280 | out: |
88921be3 | 1281 | sync_core(); |
d4812e16 | 1282 | |
b2f9d678 TL |
1283 | if (worst != MCE_AR_SEVERITY && !kill_it) |
1284 | goto out_ist; | |
d4812e16 | 1285 | |
b2f9d678 TL |
1286 | /* Fault was in user mode and we need to take some action */ |
1287 | if ((m.cs & 3) == 3) { | |
1288 | ist_begin_non_atomic(regs); | |
1289 | local_irq_enable(); | |
1290 | ||
1291 | if (kill_it || do_memory_failure(&m)) | |
1292 | force_sig(SIGBUS, current); | |
1293 | local_irq_disable(); | |
1294 | ist_end_non_atomic(); | |
1295 | } else { | |
1296 | if (!fixup_exception(regs, X86_TRAP_MC)) | |
1297 | mce_panic("Failed kernel mode recovery", &m, NULL); | |
d4812e16 | 1298 | } |
b2f9d678 TL |
1299 | |
1300 | out_ist: | |
8c84014f | 1301 | ist_exit(regs); |
1da177e4 | 1302 | } |
ea149b36 | 1303 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1304 | |
cd42f4a3 TL |
1305 | #ifndef CONFIG_MEMORY_FAILURE |
1306 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1307 | { |
a8c321fb TL |
1308 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1309 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1310 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1311 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1312 | pfn); | |
cd42f4a3 TL |
1313 | |
1314 | return 0; | |
9b1beaf2 | 1315 | } |
cd42f4a3 | 1316 | #endif |
9b1beaf2 | 1317 | |
a8c321fb TL |
1318 | /* |
1319 | * Action optional processing happens here (picking up | |
1320 | * from the list of faulting pages that do_machine_check() | |
fd4cf79f | 1321 | * placed into the genpool). |
a8c321fb | 1322 | */ |
9b1beaf2 AK |
1323 | static void mce_process_work(struct work_struct *dummy) |
1324 | { | |
fd4cf79f | 1325 | mce_gen_pool_process(); |
9b1beaf2 AK |
1326 | } |
1327 | ||
1da177e4 | 1328 | /* |
8a336b0a TH |
1329 | * Periodic polling timer for "silent" machine check errors. If the |
1330 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1331 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1332 | */ |
3f2f0680 | 1333 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1334 | |
82f7af09 | 1335 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1336 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1337 | |
55babd8f CG |
1338 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1339 | { | |
1340 | return interval; | |
1341 | } | |
1342 | ||
3f2f0680 | 1343 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1344 | |
3f2f0680 | 1345 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1346 | { |
3f2f0680 BP |
1347 | unsigned long when = jiffies + interval; |
1348 | unsigned long flags; | |
27f6c573 | 1349 | |
3f2f0680 | 1350 | local_irq_save(flags); |
27f6c573 | 1351 | |
3f2f0680 BP |
1352 | if (timer_pending(t)) { |
1353 | if (time_before(when, t->expires)) | |
f9c287ba | 1354 | mod_timer(t, when); |
3f2f0680 BP |
1355 | } else { |
1356 | t->expires = round_jiffies(when); | |
1357 | add_timer_on(t, smp_processor_id()); | |
1358 | } | |
1359 | ||
1360 | local_irq_restore(flags); | |
27f6c573 CG |
1361 | } |
1362 | ||
82f7af09 | 1363 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1364 | { |
89cbc767 | 1365 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1366 | int cpu = smp_processor_id(); |
82f7af09 | 1367 | unsigned long iv; |
52d168e2 | 1368 | |
3f2f0680 BP |
1369 | WARN_ON(cpu != data); |
1370 | ||
1371 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1372 | |
89cbc767 | 1373 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
54467353 | 1374 | machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); |
3f2f0680 BP |
1375 | |
1376 | if (mce_intel_cmci_poll()) { | |
1377 | iv = mce_adjust_timer(iv); | |
1378 | goto done; | |
1379 | } | |
e9eee03e | 1380 | } |
1da177e4 LT |
1381 | |
1382 | /* | |
3f2f0680 BP |
1383 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1384 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1385 | */ |
3f2f0680 | 1386 | if (mce_notify_irq()) |
958fb3c5 | 1387 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1388 | else |
82f7af09 | 1389 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1390 | |
1391 | done: | |
82f7af09 | 1392 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1393 | __restart_timer(t, iv); |
55babd8f | 1394 | } |
e02e68d3 | 1395 | |
55babd8f CG |
1396 | /* |
1397 | * Ensure that the timer is firing in @interval from now. | |
1398 | */ | |
1399 | void mce_timer_kick(unsigned long interval) | |
1400 | { | |
89cbc767 | 1401 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1402 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1403 | ||
3f2f0680 BP |
1404 | __restart_timer(t, interval); |
1405 | ||
55babd8f CG |
1406 | if (interval < iv) |
1407 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1408 | } |
1409 | ||
9aaef96f HS |
1410 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1411 | static void mce_timer_delete_all(void) | |
1412 | { | |
1413 | int cpu; | |
1414 | ||
1415 | for_each_online_cpu(cpu) | |
1416 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1417 | } | |
1418 | ||
9bd98405 AK |
1419 | static void mce_do_trigger(struct work_struct *work) |
1420 | { | |
1020bcbc | 1421 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1422 | } |
1423 | ||
1424 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1425 | ||
e02e68d3 | 1426 | /* |
9bd98405 AK |
1427 | * Notify the user(s) about new machine check events. |
1428 | * Can be called from interrupt context, but not from machine check/NMI | |
1429 | * context. | |
e02e68d3 | 1430 | */ |
9ff36ee9 | 1431 | int mce_notify_irq(void) |
e02e68d3 | 1432 | { |
8457c84d AK |
1433 | /* Not more than two messages every minute */ |
1434 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1435 | ||
1020bcbc | 1436 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1437 | /* wake processes polling /dev/mcelog */ |
1438 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1439 | |
4d899be5 | 1440 | if (mce_helper[0]) |
9bd98405 | 1441 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1442 | |
8457c84d | 1443 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1444 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1445 | |
1446 | return 1; | |
1da177e4 | 1447 | } |
e02e68d3 TH |
1448 | return 0; |
1449 | } | |
9ff36ee9 | 1450 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1451 | |
148f9bb8 | 1452 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1453 | { |
1454 | int i; | |
d203f0b8 | 1455 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1456 | |
d203f0b8 | 1457 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1458 | if (!mce_banks) |
1459 | return -ENOMEM; | |
d203f0b8 BP |
1460 | |
1461 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1462 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1463 | |
cebe1820 AK |
1464 | b->ctl = -1ULL; |
1465 | b->init = 1; | |
1466 | } | |
1467 | return 0; | |
1468 | } | |
1469 | ||
d88203d1 | 1470 | /* |
1da177e4 LT |
1471 | * Initialize Machine Checks for a CPU. |
1472 | */ | |
148f9bb8 | 1473 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1474 | { |
0d7482e3 | 1475 | unsigned b; |
e9eee03e | 1476 | u64 cap; |
1da177e4 LT |
1477 | |
1478 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1479 | |
1480 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1481 | if (!mca_cfg.banks) |
c767a54b | 1482 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1483 | |
0d7482e3 | 1484 | if (b > MAX_NR_BANKS) { |
c767a54b | 1485 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1486 | MAX_NR_BANKS, b); |
1487 | b = MAX_NR_BANKS; | |
1488 | } | |
1489 | ||
1490 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1491 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1492 | mca_cfg.banks = b; | |
1493 | ||
cebe1820 | 1494 | if (!mce_banks) { |
cffd377e | 1495 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1496 | |
cebe1820 AK |
1497 | if (err) |
1498 | return err; | |
1da177e4 | 1499 | } |
0d7482e3 | 1500 | |
94ad8474 | 1501 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1502 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1503 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1504 | |
ed7290d0 | 1505 | if (cap & MCG_SER_P) |
1462594b | 1506 | mca_cfg.ser = true; |
ed7290d0 | 1507 | |
0d7482e3 AK |
1508 | return 0; |
1509 | } | |
1510 | ||
5e09954a | 1511 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1512 | { |
84c2559d | 1513 | enum mcp_flags m_fl = 0; |
e9eee03e | 1514 | mce_banks_t all_banks; |
0d7482e3 | 1515 | u64 cap; |
0d7482e3 | 1516 | |
84c2559d BP |
1517 | if (!mca_cfg.bootlog) |
1518 | m_fl = MCP_DONTLOG; | |
1519 | ||
b79109c3 AK |
1520 | /* |
1521 | * Log the machine checks left over from the previous reset. | |
1522 | */ | |
ee031c31 | 1523 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1524 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1525 | |
375074cc | 1526 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1527 | |
0d7482e3 | 1528 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1529 | if (cap & MCG_CTL_P) |
1530 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
bb91f8c0 AG |
1531 | } |
1532 | ||
1533 | static void __mcheck_cpu_init_clear_banks(void) | |
1534 | { | |
1535 | int i; | |
1da177e4 | 1536 | |
d203f0b8 | 1537 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1538 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1539 | |
cebe1820 | 1540 | if (!b->init) |
06b7a7a5 | 1541 | continue; |
d9d73fcc YG |
1542 | wrmsrl(msr_ops.ctl(i), b->ctl); |
1543 | wrmsrl(msr_ops.status(i), 0); | |
d88203d1 | 1544 | } |
1da177e4 LT |
1545 | } |
1546 | ||
61b0fccd TL |
1547 | /* |
1548 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1549 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1550 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1551 | * whether the machine check occurred in kernel or user mode, and also | |
1552 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1553 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1554 | */ | |
1555 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1556 | { | |
1557 | if (bank != 0) | |
1558 | return; | |
1559 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1560 | return; | |
1561 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1562 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1563 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1564 | MCACOD)) != | |
1565 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1566 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1567 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1568 | return; | |
1569 | ||
1570 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1571 | m->ip = regs->ip; | |
1572 | m->cs = regs->cs; | |
1573 | } | |
1574 | ||
1da177e4 | 1575 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1576 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1577 | { |
d203f0b8 BP |
1578 | struct mca_config *cfg = &mca_cfg; |
1579 | ||
e412cd25 | 1580 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1581 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1582 | return -EOPNOTSUPP; |
1583 | } | |
1584 | ||
1da177e4 | 1585 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1586 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1587 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1588 | /* |
1589 | * disable GART TBL walk error reporting, which | |
1590 | * trips off incorrectly with the IOMMU & 3ware | |
1591 | * & Cerberus: | |
1592 | */ | |
cebe1820 | 1593 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1594 | } |
10001d91 | 1595 | if (c->x86 < 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1596 | /* |
1597 | * Lots of broken BIOS around that don't clear them | |
1598 | * by default and leave crap in there. Don't log: | |
1599 | */ | |
84c2559d | 1600 | cfg->bootlog = 0; |
e9eee03e | 1601 | } |
2e6f694f AK |
1602 | /* |
1603 | * Various K7s with broken bank 0 around. Always disable | |
1604 | * by default. | |
1605 | */ | |
c9ce8712 | 1606 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1607 | mce_banks[0].ctl = 0; |
575203b4 | 1608 | |
bf80bbd7 AG |
1609 | /* |
1610 | * overflow_recov is supported for F15h Models 00h-0fh | |
1611 | * even though we don't have a CPUID bit for it. | |
1612 | */ | |
1613 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1614 | mce_flags.overflow_recov = 1; | |
1615 | ||
c9ce8712 BP |
1616 | /* |
1617 | * Turn off MC4_MISC thresholding banks on those models since | |
1618 | * they're not supported there. | |
1619 | */ | |
1620 | if (c->x86 == 0x15 && | |
1621 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1622 | int i; | |
1623 | u64 hwcr; | |
1624 | bool need_toggle; | |
1625 | u32 msrs[] = { | |
575203b4 BP |
1626 | 0x00000413, /* MC4_MISC0 */ |
1627 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1628 | }; |
575203b4 | 1629 | |
c9ce8712 | 1630 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1631 | |
c9ce8712 BP |
1632 | /* McStatusWrEn has to be set */ |
1633 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1634 | |
c9ce8712 BP |
1635 | if (need_toggle) |
1636 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1637 | |
c9ce8712 BP |
1638 | /* Clear CntP bit safely */ |
1639 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1640 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1641 | |
c9ce8712 BP |
1642 | /* restore old settings */ |
1643 | if (need_toggle) | |
1644 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1645 | } | |
1da177e4 | 1646 | } |
e583538f | 1647 | |
06b7a7a5 AK |
1648 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1649 | /* | |
1650 | * SDM documents that on family 6 bank 0 should not be written | |
1651 | * because it aliases to another special BIOS controlled | |
1652 | * register. | |
1653 | * But it's not aliased anymore on model 0x1a+ | |
1654 | * Don't ignore bank 0 completely because there could be a | |
1655 | * valid event later, merely don't write CTL0. | |
1656 | */ | |
1657 | ||
d203f0b8 | 1658 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1659 | mce_banks[0].init = 0; |
3c079792 AK |
1660 | |
1661 | /* | |
1662 | * All newer Intel systems support MCE broadcasting. Enable | |
1663 | * synchronization with a one second timeout. | |
1664 | */ | |
1665 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1666 | cfg->monarch_timeout < 0) |
1667 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1668 | |
e412cd25 IM |
1669 | /* |
1670 | * There are also broken BIOSes on some Pentium M and | |
1671 | * earlier systems: | |
1672 | */ | |
84c2559d BP |
1673 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1674 | cfg->bootlog = 0; | |
61b0fccd TL |
1675 | |
1676 | if (c->x86 == 6 && c->x86_model == 45) | |
1677 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1678 | } |
84c2559d BP |
1679 | if (cfg->monarch_timeout < 0) |
1680 | cfg->monarch_timeout = 0; | |
1681 | if (cfg->bootlog != 0) | |
7af19e4a | 1682 | cfg->panic_timeout = 30; |
e412cd25 IM |
1683 | |
1684 | return 0; | |
d88203d1 | 1685 | } |
1da177e4 | 1686 | |
148f9bb8 | 1687 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1688 | { |
1689 | if (c->x86 != 5) | |
3a97fc34 HS |
1690 | return 0; |
1691 | ||
4efc0670 AK |
1692 | switch (c->x86_vendor) { |
1693 | case X86_VENDOR_INTEL: | |
c6978369 | 1694 | intel_p5_mcheck_init(c); |
3a97fc34 | 1695 | return 1; |
4efc0670 AK |
1696 | break; |
1697 | case X86_VENDOR_CENTAUR: | |
1698 | winchip_mcheck_init(c); | |
3a97fc34 | 1699 | return 1; |
4efc0670 | 1700 | break; |
dc34bdd2 BP |
1701 | default: |
1702 | return 0; | |
4efc0670 | 1703 | } |
3a97fc34 HS |
1704 | |
1705 | return 0; | |
4efc0670 AK |
1706 | } |
1707 | ||
5e09954a | 1708 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1709 | { |
1710 | switch (c->x86_vendor) { | |
1711 | case X86_VENDOR_INTEL: | |
1712 | mce_intel_feature_init(c); | |
3f2f0680 | 1713 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1714 | break; |
7559e13f AG |
1715 | |
1716 | case X86_VENDOR_AMD: { | |
14cddfd5 YG |
1717 | mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); |
1718 | mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); | |
1719 | mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); | |
d9d73fcc YG |
1720 | |
1721 | /* | |
1722 | * Install proper ops for Scalable MCA enabled processors | |
1723 | */ | |
1724 | if (mce_flags.smca) { | |
1725 | msr_ops.ctl = smca_ctl_reg; | |
1726 | msr_ops.status = smca_status_reg; | |
1727 | msr_ops.addr = smca_addr_reg; | |
1728 | msr_ops.misc = smca_misc_reg; | |
1729 | } | |
bfbe0eeb | 1730 | mce_amd_feature_init(c); |
c7f54d21 | 1731 | |
89b831ef | 1732 | break; |
7559e13f AG |
1733 | } |
1734 | ||
1da177e4 LT |
1735 | default: |
1736 | break; | |
1737 | } | |
1738 | } | |
1739 | ||
8838eb6c AR |
1740 | static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) |
1741 | { | |
1742 | switch (c->x86_vendor) { | |
1743 | case X86_VENDOR_INTEL: | |
1744 | mce_intel_feature_clear(c); | |
1745 | break; | |
1746 | default: | |
1747 | break; | |
1748 | } | |
1749 | } | |
1750 | ||
26c3c283 | 1751 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1752 | { |
4f75d841 | 1753 | unsigned long iv = check_interval * HZ; |
bc09effa | 1754 | |
7af19e4a | 1755 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1756 | return; |
1757 | ||
4f75d841 BP |
1758 | per_cpu(mce_next_interval, cpu) = iv; |
1759 | ||
82f7af09 | 1760 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1761 | add_timer_on(t, cpu); |
52d168e2 AK |
1762 | } |
1763 | ||
39f152ff SAS |
1764 | static void __mcheck_cpu_setup_timer(void) |
1765 | { | |
1766 | struct timer_list *t = this_cpu_ptr(&mce_timer); | |
1767 | unsigned int cpu = smp_processor_id(); | |
1768 | ||
1769 | setup_pinned_timer(t, mce_timer_fn, cpu); | |
1770 | } | |
1771 | ||
26c3c283 TG |
1772 | static void __mcheck_cpu_init_timer(void) |
1773 | { | |
89cbc767 | 1774 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1775 | unsigned int cpu = smp_processor_id(); |
1776 | ||
f9c287ba | 1777 | setup_pinned_timer(t, mce_timer_fn, cpu); |
26c3c283 TG |
1778 | mce_start_timer(cpu, t); |
1779 | } | |
1780 | ||
9eda8cb3 AK |
1781 | /* Handle unconfigured int18 (should never happen) */ |
1782 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1783 | { | |
c767a54b | 1784 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1785 | smp_processor_id()); |
1786 | } | |
1787 | ||
1788 | /* Call the installed machine check handler for this CPU setup. */ | |
1789 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1790 | unexpected_machine_check; | |
1791 | ||
d88203d1 | 1792 | /* |
1da177e4 | 1793 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1794 | * Must be called with preempt off: |
1da177e4 | 1795 | */ |
148f9bb8 | 1796 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1797 | { |
1462594b | 1798 | if (mca_cfg.disabled) |
4efc0670 AK |
1799 | return; |
1800 | ||
3a97fc34 HS |
1801 | if (__mcheck_cpu_ancient_init(c)) |
1802 | return; | |
4efc0670 | 1803 | |
5b4408fd | 1804 | if (!mce_available(c)) |
1da177e4 LT |
1805 | return; |
1806 | ||
5e09954a | 1807 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1808 | mca_cfg.disabled = true; |
0d7482e3 AK |
1809 | return; |
1810 | } | |
0d7482e3 | 1811 | |
648ed940 CG |
1812 | if (mce_gen_pool_init()) { |
1813 | mca_cfg.disabled = true; | |
1814 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1815 | return; | |
1816 | } | |
1817 | ||
5d727926 AK |
1818 | machine_check_vector = do_machine_check; |
1819 | ||
5e09954a BP |
1820 | __mcheck_cpu_init_generic(); |
1821 | __mcheck_cpu_init_vendor(c); | |
bb91f8c0 | 1822 | __mcheck_cpu_init_clear_banks(); |
39f152ff | 1823 | __mcheck_cpu_setup_timer(); |
1da177e4 LT |
1824 | } |
1825 | ||
8838eb6c AR |
1826 | /* |
1827 | * Called for each booted CPU to clear some machine checks opt-ins | |
1828 | */ | |
1829 | void mcheck_cpu_clear(struct cpuinfo_x86 *c) | |
1830 | { | |
1831 | if (mca_cfg.disabled) | |
1832 | return; | |
1833 | ||
1834 | if (!mce_available(c)) | |
1835 | return; | |
1836 | ||
1837 | /* | |
1838 | * Possibly to clear general settings generic to x86 | |
1839 | * __mcheck_cpu_clear_generic(c); | |
1840 | */ | |
1841 | __mcheck_cpu_clear_vendor(c); | |
1842 | ||
1da177e4 LT |
1843 | } |
1844 | ||
1845 | /* | |
93b62c3c | 1846 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1847 | */ |
1848 | ||
93b62c3c HS |
1849 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1850 | static int mce_chrdev_open_count; /* #times opened */ | |
1851 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1852 | |
93b62c3c | 1853 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1854 | { |
93b62c3c | 1855 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1856 | |
93b62c3c HS |
1857 | if (mce_chrdev_open_exclu || |
1858 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1859 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1860 | |
f528e7ba TH |
1861 | return -EBUSY; |
1862 | } | |
1863 | ||
1864 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1865 | mce_chrdev_open_exclu = 1; |
1866 | mce_chrdev_open_count++; | |
f528e7ba | 1867 | |
93b62c3c | 1868 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1869 | |
bd78432c | 1870 | return nonseekable_open(inode, file); |
f528e7ba TH |
1871 | } |
1872 | ||
93b62c3c | 1873 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1874 | { |
93b62c3c | 1875 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1876 | |
93b62c3c HS |
1877 | mce_chrdev_open_count--; |
1878 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1879 | |
93b62c3c | 1880 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1881 | |
1882 | return 0; | |
1883 | } | |
1884 | ||
d88203d1 TG |
1885 | static void collect_tscs(void *data) |
1886 | { | |
1da177e4 | 1887 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1888 | |
4ea1636b | 1889 | cpu_tsc[smp_processor_id()] = rdtsc(); |
d88203d1 | 1890 | } |
1da177e4 | 1891 | |
482908b4 HY |
1892 | static int mce_apei_read_done; |
1893 | ||
1894 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1895 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1896 | { | |
1897 | int rc; | |
1898 | u64 record_id; | |
1899 | struct mce m; | |
1900 | ||
1901 | if (usize < sizeof(struct mce)) | |
1902 | return -EINVAL; | |
1903 | ||
1904 | rc = apei_read_mce(&m, &record_id); | |
1905 | /* Error or no more MCE record */ | |
1906 | if (rc <= 0) { | |
1907 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1908 | /* |
1909 | * When ERST is disabled, mce_chrdev_read() should return | |
1910 | * "no record" instead of "no device." | |
1911 | */ | |
1912 | if (rc == -ENODEV) | |
1913 | return 0; | |
482908b4 HY |
1914 | return rc; |
1915 | } | |
1916 | rc = -EFAULT; | |
1917 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1918 | return rc; | |
1919 | /* | |
1920 | * In fact, we should have cleared the record after that has | |
1921 | * been flushed to the disk or sent to network in | |
1922 | * /sbin/mcelog, but we have no interface to support that now, | |
1923 | * so just clear it to avoid duplication. | |
1924 | */ | |
1925 | rc = apei_clear_mce(record_id); | |
1926 | if (rc) { | |
1927 | mce_apei_read_done = 1; | |
1928 | return rc; | |
1929 | } | |
1930 | *ubuf += sizeof(struct mce); | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
93b62c3c HS |
1935 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1936 | size_t usize, loff_t *off) | |
1da177e4 | 1937 | { |
e9eee03e | 1938 | char __user *buf = ubuf; |
f0de53bb | 1939 | unsigned long *cpu_tsc; |
ef41df43 | 1940 | unsigned prev, next; |
1da177e4 LT |
1941 | int i, err; |
1942 | ||
6bca67f9 | 1943 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1944 | if (!cpu_tsc) |
1945 | return -ENOMEM; | |
1946 | ||
93b62c3c | 1947 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1948 | |
1949 | if (!mce_apei_read_done) { | |
1950 | err = __mce_read_apei(&buf, usize); | |
1951 | if (err || buf != ubuf) | |
1952 | goto out; | |
1953 | } | |
1954 | ||
9a7783d0 | 1955 | next = mce_log_get_idx_check(mcelog.next); |
1da177e4 LT |
1956 | |
1957 | /* Only supports full reads right now */ | |
482908b4 HY |
1958 | err = -EINVAL; |
1959 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1960 | goto out; | |
1da177e4 LT |
1961 | |
1962 | err = 0; | |
ef41df43 HY |
1963 | prev = 0; |
1964 | do { | |
1965 | for (i = prev; i < next; i++) { | |
1966 | unsigned long start = jiffies; | |
559faa6b | 1967 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1968 | |
559faa6b | 1969 | while (!m->finished) { |
ef41df43 | 1970 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1971 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1972 | goto timeout; |
1973 | } | |
1974 | cpu_relax(); | |
673242c1 | 1975 | } |
ef41df43 | 1976 | smp_rmb(); |
559faa6b HS |
1977 | err |= copy_to_user(buf, m, sizeof(*m)); |
1978 | buf += sizeof(*m); | |
ef41df43 HY |
1979 | timeout: |
1980 | ; | |
673242c1 | 1981 | } |
1da177e4 | 1982 | |
ef41df43 HY |
1983 | memset(mcelog.entry + prev, 0, |
1984 | (next - prev) * sizeof(struct mce)); | |
1985 | prev = next; | |
1986 | next = cmpxchg(&mcelog.next, prev, 0); | |
1987 | } while (next != prev); | |
1da177e4 | 1988 | |
b2b18660 | 1989 | synchronize_sched(); |
1da177e4 | 1990 | |
d88203d1 TG |
1991 | /* |
1992 | * Collect entries that were still getting written before the | |
1993 | * synchronize. | |
1994 | */ | |
15c8b6c1 | 1995 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1996 | |
d88203d1 | 1997 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1998 | struct mce *m = &mcelog.entry[i]; |
1999 | ||
2000 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
2001 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 2002 | smp_rmb(); |
559faa6b HS |
2003 | buf += sizeof(*m); |
2004 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 2005 | } |
d88203d1 | 2006 | } |
482908b4 HY |
2007 | |
2008 | if (err) | |
2009 | err = -EFAULT; | |
2010 | ||
2011 | out: | |
93b62c3c | 2012 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 2013 | kfree(cpu_tsc); |
e9eee03e | 2014 | |
482908b4 | 2015 | return err ? err : buf - ubuf; |
1da177e4 LT |
2016 | } |
2017 | ||
93b62c3c | 2018 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 2019 | { |
93b62c3c | 2020 | poll_wait(file, &mce_chrdev_wait, wait); |
e90328b8 | 2021 | if (READ_ONCE(mcelog.next)) |
e02e68d3 | 2022 | return POLLIN | POLLRDNORM; |
482908b4 HY |
2023 | if (!mce_apei_read_done && apei_check_mce()) |
2024 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
2025 | return 0; |
2026 | } | |
2027 | ||
93b62c3c HS |
2028 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
2029 | unsigned long arg) | |
1da177e4 LT |
2030 | { |
2031 | int __user *p = (int __user *)arg; | |
d88203d1 | 2032 | |
1da177e4 | 2033 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 2034 | return -EPERM; |
e9eee03e | 2035 | |
1da177e4 | 2036 | switch (cmd) { |
d88203d1 | 2037 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
2038 | return put_user(sizeof(struct mce), p); |
2039 | case MCE_GET_LOG_LEN: | |
d88203d1 | 2040 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
2041 | case MCE_GETCLEAR_FLAGS: { |
2042 | unsigned flags; | |
d88203d1 TG |
2043 | |
2044 | do { | |
1da177e4 | 2045 | flags = mcelog.flags; |
d88203d1 | 2046 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 2047 | |
d88203d1 | 2048 | return put_user(flags, p); |
1da177e4 LT |
2049 | } |
2050 | default: | |
d88203d1 TG |
2051 | return -ENOTTY; |
2052 | } | |
1da177e4 LT |
2053 | } |
2054 | ||
66f5ddf3 LT |
2055 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
2056 | size_t usize, loff_t *off); | |
2057 | ||
2058 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
2059 | const char __user *ubuf, | |
2060 | size_t usize, loff_t *off)) | |
2061 | { | |
2062 | mce_write = fn; | |
2063 | } | |
2064 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
2065 | ||
29c6820f PM |
2066 | static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, |
2067 | size_t usize, loff_t *off) | |
66f5ddf3 LT |
2068 | { |
2069 | if (mce_write) | |
2070 | return mce_write(filp, ubuf, usize, off); | |
2071 | else | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
2076 | .open = mce_chrdev_open, |
2077 | .release = mce_chrdev_release, | |
2078 | .read = mce_chrdev_read, | |
66f5ddf3 | 2079 | .write = mce_chrdev_write, |
93b62c3c HS |
2080 | .poll = mce_chrdev_poll, |
2081 | .unlocked_ioctl = mce_chrdev_ioctl, | |
2082 | .llseek = no_llseek, | |
1da177e4 LT |
2083 | }; |
2084 | ||
93b62c3c | 2085 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
2086 | MISC_MCELOG_MINOR, |
2087 | "mcelog", | |
2088 | &mce_chrdev_ops, | |
2089 | }; | |
2090 | ||
c3d1fb56 NR |
2091 | static void __mce_disable_bank(void *arg) |
2092 | { | |
2093 | int bank = *((int *)arg); | |
89cbc767 | 2094 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
2095 | cmci_disable_bank(bank); |
2096 | } | |
2097 | ||
2098 | void mce_disable_bank(int bank) | |
2099 | { | |
2100 | if (bank >= mca_cfg.banks) { | |
2101 | pr_warn(FW_BUG | |
2102 | "Ignoring request to disable invalid MCA bank %d.\n", | |
2103 | bank); | |
2104 | return; | |
2105 | } | |
2106 | set_bit(bank, mce_banks_ce_disabled); | |
2107 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
2108 | } | |
2109 | ||
13503fa9 | 2110 | /* |
62fdac59 HS |
2111 | * mce=off Disables machine check |
2112 | * mce=no_cmci Disables CMCI | |
88d53867 | 2113 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
2114 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
2115 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
2116 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
2117 | * monarchtimeout is how long to wait for other CPUs on machine | |
2118 | * check, or 0 to not wait | |
13503fa9 HS |
2119 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
2120 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 2121 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
3637efb0 | 2122 | * mce=recovery force enable memcpy_mcsafe() |
13503fa9 | 2123 | */ |
1da177e4 LT |
2124 | static int __init mcheck_enable(char *str) |
2125 | { | |
d203f0b8 BP |
2126 | struct mca_config *cfg = &mca_cfg; |
2127 | ||
e3346fc4 | 2128 | if (*str == 0) { |
4efc0670 | 2129 | enable_p5_mce(); |
e3346fc4 BZ |
2130 | return 1; |
2131 | } | |
4efc0670 AK |
2132 | if (*str == '=') |
2133 | str++; | |
1da177e4 | 2134 | if (!strcmp(str, "off")) |
1462594b | 2135 | cfg->disabled = true; |
62fdac59 | 2136 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2137 | cfg->cmci_disabled = true; |
88d53867 AR |
2138 | else if (!strcmp(str, "no_lmce")) |
2139 | cfg->lmce_disabled = true; | |
62fdac59 | 2140 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2141 | cfg->dont_log_ce = true; |
62fdac59 | 2142 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2143 | cfg->ignore_ce = true; |
13503fa9 | 2144 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2145 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2146 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2147 | cfg->bios_cmci_threshold = true; |
0f68c088 TL |
2148 | else if (!strcmp(str, "recovery")) |
2149 | cfg->recovery = true; | |
3c079792 | 2150 | else if (isdigit(str[0])) { |
5c31b280 | 2151 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 2152 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 2153 | } else { |
c767a54b | 2154 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2155 | return 0; |
2156 | } | |
9b41046c | 2157 | return 1; |
1da177e4 | 2158 | } |
4efc0670 | 2159 | __setup("mce", mcheck_enable); |
1da177e4 | 2160 | |
a2202aa2 | 2161 | int __init mcheck_init(void) |
b33a6363 | 2162 | { |
a2202aa2 | 2163 | mcheck_intel_therm_init(); |
eef4dfa0 | 2164 | mce_register_decode_chain(&mce_srao_nb); |
cd9c57ca | 2165 | mce_register_decode_chain(&mce_default_nb); |
43eaa2a1 | 2166 | mcheck_vendor_init_severity(); |
a2202aa2 | 2167 | |
061120ae CG |
2168 | INIT_WORK(&mce_work, mce_process_work); |
2169 | init_irq_work(&mce_irq_work, mce_irq_work_cb); | |
2170 | ||
b33a6363 BP |
2171 | return 0; |
2172 | } | |
b33a6363 | 2173 | |
d88203d1 | 2174 | /* |
c7cece89 | 2175 | * mce_syscore: PM support |
d88203d1 | 2176 | */ |
1da177e4 | 2177 | |
973a2dd1 AK |
2178 | /* |
2179 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2180 | * them later. | |
2181 | */ | |
6e06780a | 2182 | static void mce_disable_error_reporting(void) |
973a2dd1 AK |
2183 | { |
2184 | int i; | |
2185 | ||
d203f0b8 | 2186 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2187 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2188 | |
cebe1820 | 2189 | if (b->init) |
d9d73fcc | 2190 | wrmsrl(msr_ops.ctl(i), 0); |
06b7a7a5 | 2191 | } |
6e06780a AR |
2192 | return; |
2193 | } | |
2194 | ||
2195 | static void vendor_disable_error_reporting(void) | |
2196 | { | |
2197 | /* | |
2198 | * Don't clear on Intel CPUs. Some of these MSRs are socket-wide. | |
2199 | * Disabling them for just a single offlined CPU is bad, since it will | |
2200 | * inhibit reporting for all shared resources on the socket like the | |
2201 | * last level cache (LLC), the integrated memory controller (iMC), etc. | |
2202 | */ | |
2203 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2204 | return; | |
2205 | ||
2206 | mce_disable_error_reporting(); | |
973a2dd1 AK |
2207 | } |
2208 | ||
c7cece89 | 2209 | static int mce_syscore_suspend(void) |
973a2dd1 | 2210 | { |
6e06780a AR |
2211 | vendor_disable_error_reporting(); |
2212 | return 0; | |
973a2dd1 AK |
2213 | } |
2214 | ||
c7cece89 | 2215 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2216 | { |
6e06780a | 2217 | vendor_disable_error_reporting(); |
973a2dd1 AK |
2218 | } |
2219 | ||
e9eee03e IM |
2220 | /* |
2221 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2222 | * Only one CPU is active at this time, the others get re-added later using | |
2223 | * CPU hotplug: | |
2224 | */ | |
c7cece89 | 2225 | static void mce_syscore_resume(void) |
1da177e4 | 2226 | { |
5e09954a | 2227 | __mcheck_cpu_init_generic(); |
89cbc767 | 2228 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
bb91f8c0 | 2229 | __mcheck_cpu_init_clear_banks(); |
1da177e4 LT |
2230 | } |
2231 | ||
f3c6ea1b | 2232 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2233 | .suspend = mce_syscore_suspend, |
2234 | .shutdown = mce_syscore_shutdown, | |
2235 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2236 | }; |
2237 | ||
c7cece89 | 2238 | /* |
8a25a2fd | 2239 | * mce_device: Sysfs support |
c7cece89 HS |
2240 | */ |
2241 | ||
52d168e2 AK |
2242 | static void mce_cpu_restart(void *data) |
2243 | { | |
89cbc767 | 2244 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2245 | return; |
5e09954a | 2246 | __mcheck_cpu_init_generic(); |
bb91f8c0 | 2247 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 2248 | __mcheck_cpu_init_timer(); |
52d168e2 AK |
2249 | } |
2250 | ||
1da177e4 | 2251 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2252 | static void mce_restart(void) |
2253 | { | |
9aaef96f | 2254 | mce_timer_delete_all(); |
52d168e2 | 2255 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2256 | } |
2257 | ||
9af43b54 | 2258 | /* Toggle features for corrected errors */ |
9aaef96f | 2259 | static void mce_disable_cmci(void *data) |
9af43b54 | 2260 | { |
89cbc767 | 2261 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2262 | return; |
9af43b54 HS |
2263 | cmci_clear(); |
2264 | } | |
2265 | ||
2266 | static void mce_enable_ce(void *all) | |
2267 | { | |
89cbc767 | 2268 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2269 | return; |
2270 | cmci_reenable(); | |
2271 | cmci_recheck(); | |
2272 | if (all) | |
5e09954a | 2273 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2274 | } |
2275 | ||
8a25a2fd | 2276 | static struct bus_type mce_subsys = { |
e9eee03e | 2277 | .name = "machinecheck", |
8a25a2fd | 2278 | .dev_name = "machinecheck", |
1da177e4 LT |
2279 | }; |
2280 | ||
d6126ef5 | 2281 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2282 | |
8a25a2fd | 2283 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2284 | { |
2285 | return container_of(attr, struct mce_bank, attr); | |
2286 | } | |
0d7482e3 | 2287 | |
8a25a2fd | 2288 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2289 | char *buf) |
2290 | { | |
cebe1820 | 2291 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2292 | } |
2293 | ||
8a25a2fd | 2294 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2295 | const char *buf, size_t size) |
0d7482e3 | 2296 | { |
9319cec8 | 2297 | u64 new; |
e9eee03e | 2298 | |
164109e3 | 2299 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2300 | return -EINVAL; |
e9eee03e | 2301 | |
cebe1820 | 2302 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2303 | mce_restart(); |
e9eee03e | 2304 | |
9319cec8 | 2305 | return size; |
0d7482e3 | 2306 | } |
a98f0dd3 | 2307 | |
e9eee03e | 2308 | static ssize_t |
8a25a2fd | 2309 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2310 | { |
1020bcbc | 2311 | strcpy(buf, mce_helper); |
a98f0dd3 | 2312 | strcat(buf, "\n"); |
1020bcbc | 2313 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2314 | } |
2315 | ||
8a25a2fd | 2316 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2317 | const char *buf, size_t siz) |
a98f0dd3 AK |
2318 | { |
2319 | char *p; | |
e9eee03e | 2320 | |
1020bcbc HS |
2321 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2322 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2323 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2324 | |
e9084ec9 | 2325 | if (p) |
e9eee03e IM |
2326 | *p = 0; |
2327 | ||
e9084ec9 | 2328 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2329 | } |
2330 | ||
8a25a2fd KS |
2331 | static ssize_t set_ignore_ce(struct device *s, |
2332 | struct device_attribute *attr, | |
9af43b54 HS |
2333 | const char *buf, size_t size) |
2334 | { | |
2335 | u64 new; | |
2336 | ||
164109e3 | 2337 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2338 | return -EINVAL; |
2339 | ||
7af19e4a | 2340 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2341 | if (new) { |
2342 | /* disable ce features */ | |
9aaef96f HS |
2343 | mce_timer_delete_all(); |
2344 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2345 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2346 | } else { |
2347 | /* enable ce features */ | |
7af19e4a | 2348 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2349 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2350 | } | |
2351 | } | |
2352 | return size; | |
2353 | } | |
2354 | ||
8a25a2fd KS |
2355 | static ssize_t set_cmci_disabled(struct device *s, |
2356 | struct device_attribute *attr, | |
9af43b54 HS |
2357 | const char *buf, size_t size) |
2358 | { | |
2359 | u64 new; | |
2360 | ||
164109e3 | 2361 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2362 | return -EINVAL; |
2363 | ||
7af19e4a | 2364 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2365 | if (new) { |
2366 | /* disable cmci */ | |
9aaef96f | 2367 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2368 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2369 | } else { |
2370 | /* enable cmci */ | |
7af19e4a | 2371 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2372 | on_each_cpu(mce_enable_ce, NULL, 1); |
2373 | } | |
2374 | } | |
2375 | return size; | |
2376 | } | |
2377 | ||
8a25a2fd KS |
2378 | static ssize_t store_int_with_restart(struct device *s, |
2379 | struct device_attribute *attr, | |
b56f642d AK |
2380 | const char *buf, size_t size) |
2381 | { | |
8a25a2fd | 2382 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2383 | mce_restart(); |
2384 | return ret; | |
2385 | } | |
2386 | ||
8a25a2fd | 2387 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2388 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2389 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2390 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2391 | |
8a25a2fd KS |
2392 | static struct dev_ext_attribute dev_attr_check_interval = { |
2393 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2394 | &check_interval |
2395 | }; | |
e9eee03e | 2396 | |
8a25a2fd | 2397 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2398 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2399 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2400 | }; |
2401 | ||
8a25a2fd | 2402 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2403 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2404 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2405 | }; |
2406 | ||
8a25a2fd KS |
2407 | static struct device_attribute *mce_device_attrs[] = { |
2408 | &dev_attr_tolerant.attr, | |
2409 | &dev_attr_check_interval.attr, | |
2410 | &dev_attr_trigger, | |
2411 | &dev_attr_monarch_timeout.attr, | |
2412 | &dev_attr_dont_log_ce.attr, | |
2413 | &dev_attr_ignore_ce.attr, | |
2414 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2415 | NULL |
2416 | }; | |
1da177e4 | 2417 | |
8a25a2fd | 2418 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2419 | |
e032d807 GKH |
2420 | static void mce_device_release(struct device *dev) |
2421 | { | |
2422 | kfree(dev); | |
2423 | } | |
2424 | ||
8a25a2fd | 2425 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2426 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2427 | { |
e032d807 | 2428 | struct device *dev; |
1da177e4 | 2429 | int err; |
b1f49f95 | 2430 | int i, j; |
92cb7612 | 2431 | |
90367556 | 2432 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2433 | return -EIO; |
2434 | ||
7f34b935 SAS |
2435 | dev = per_cpu(mce_device, cpu); |
2436 | if (dev) | |
2437 | return 0; | |
2438 | ||
e032d807 GKH |
2439 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2440 | if (!dev) | |
2441 | return -ENOMEM; | |
8a25a2fd KS |
2442 | dev->id = cpu; |
2443 | dev->bus = &mce_subsys; | |
e032d807 | 2444 | dev->release = &mce_device_release; |
91c6d400 | 2445 | |
8a25a2fd | 2446 | err = device_register(dev); |
853d9b18 LK |
2447 | if (err) { |
2448 | put_device(dev); | |
d435d862 | 2449 | return err; |
853d9b18 | 2450 | } |
d435d862 | 2451 | |
8a25a2fd KS |
2452 | for (i = 0; mce_device_attrs[i]; i++) { |
2453 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2454 | if (err) |
2455 | goto error; | |
2456 | } | |
d203f0b8 | 2457 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2458 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2459 | if (err) |
2460 | goto error2; | |
2461 | } | |
8a25a2fd | 2462 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2463 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2464 | |
d435d862 | 2465 | return 0; |
0d7482e3 | 2466 | error2: |
b1f49f95 | 2467 | while (--j >= 0) |
8a25a2fd | 2468 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2469 | error: |
cb491fca | 2470 | while (--i >= 0) |
8a25a2fd | 2471 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2472 | |
8a25a2fd | 2473 | device_unregister(dev); |
d435d862 | 2474 | |
91c6d400 AK |
2475 | return err; |
2476 | } | |
2477 | ||
148f9bb8 | 2478 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2479 | { |
d6126ef5 | 2480 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2481 | int i; |
2482 | ||
8a25a2fd | 2483 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2484 | return; |
2485 | ||
8a25a2fd KS |
2486 | for (i = 0; mce_device_attrs[i]; i++) |
2487 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2488 | |
d203f0b8 | 2489 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2490 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2491 | |
8a25a2fd KS |
2492 | device_unregister(dev); |
2493 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2494 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2495 | } |
91c6d400 | 2496 | |
d6b75584 | 2497 | /* Make sure there are no machine checks on offlined CPUs. */ |
39f152ff | 2498 | static void mce_disable_cpu(void) |
d6b75584 | 2499 | { |
89cbc767 | 2500 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2501 | return; |
767df1bd | 2502 | |
39f152ff | 2503 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2504 | cmci_clear(); |
11868a2d | 2505 | |
6e06780a | 2506 | vendor_disable_error_reporting(); |
d6b75584 AK |
2507 | } |
2508 | ||
39f152ff | 2509 | static void mce_reenable_cpu(void) |
d6b75584 | 2510 | { |
e9eee03e | 2511 | int i; |
d6b75584 | 2512 | |
89cbc767 | 2513 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2514 | return; |
e9eee03e | 2515 | |
39f152ff | 2516 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2517 | cmci_reenable(); |
d203f0b8 | 2518 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2519 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2520 | |
cebe1820 | 2521 | if (b->init) |
d9d73fcc | 2522 | wrmsrl(msr_ops.ctl(i), b->ctl); |
06b7a7a5 | 2523 | } |
d6b75584 AK |
2524 | } |
2525 | ||
0e285d36 | 2526 | static int mce_cpu_dead(unsigned int cpu) |
91c6d400 | 2527 | { |
0e285d36 | 2528 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2529 | |
0e285d36 SAS |
2530 | /* intentionally ignoring frozen here */ |
2531 | if (!cpuhp_tasks_frozen) | |
2532 | cmci_rediscover(); | |
2533 | return 0; | |
91c6d400 AK |
2534 | } |
2535 | ||
8c0eeac8 | 2536 | static int mce_cpu_online(unsigned int cpu) |
91c6d400 | 2537 | { |
52d168e2 | 2538 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
8c0eeac8 | 2539 | int ret; |
91c6d400 | 2540 | |
8c0eeac8 | 2541 | mce_device_create(cpu); |
38356c1f | 2542 | |
8c0eeac8 SAS |
2543 | ret = mce_threshold_create_device(cpu); |
2544 | if (ret) { | |
2545 | mce_device_remove(cpu); | |
2546 | return ret; | |
1a65f970 | 2547 | } |
8c0eeac8 SAS |
2548 | mce_reenable_cpu(); |
2549 | mce_start_timer(cpu, t); | |
2550 | return 0; | |
91c6d400 AK |
2551 | } |
2552 | ||
8c0eeac8 SAS |
2553 | static int mce_cpu_pre_down(unsigned int cpu) |
2554 | { | |
2555 | struct timer_list *t = &per_cpu(mce_timer, cpu); | |
2556 | ||
2557 | mce_disable_cpu(); | |
2558 | del_timer_sync(t); | |
2559 | mce_threshold_remove_device(cpu); | |
2560 | mce_device_remove(cpu); | |
2561 | return 0; | |
2562 | } | |
91c6d400 | 2563 | |
cebe1820 | 2564 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2565 | { |
2566 | int i; | |
2567 | ||
d203f0b8 | 2568 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2569 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2570 | struct device_attribute *a = &b->attr; |
e9eee03e | 2571 | |
a07e4156 | 2572 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2573 | a->attr.name = b->attrname; |
2574 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2575 | |
2576 | a->attr.mode = 0644; | |
2577 | a->show = show_bank; | |
2578 | a->store = set_bank; | |
0d7482e3 | 2579 | } |
0d7482e3 AK |
2580 | } |
2581 | ||
5e09954a | 2582 | static __init int mcheck_init_device(void) |
91c6d400 | 2583 | { |
8c0eeac8 | 2584 | enum cpuhp_state hp_online; |
91c6d400 | 2585 | int err; |
91c6d400 | 2586 | |
9c15a24b MS |
2587 | if (!mce_available(&boot_cpu_data)) { |
2588 | err = -EIO; | |
2589 | goto err_out; | |
2590 | } | |
0d7482e3 | 2591 | |
9c15a24b MS |
2592 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2593 | err = -ENOMEM; | |
2594 | goto err_out; | |
2595 | } | |
996867d0 | 2596 | |
cebe1820 | 2597 | mce_init_banks(); |
0d7482e3 | 2598 | |
8a25a2fd | 2599 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2600 | if (err) |
9c15a24b | 2601 | goto err_out_mem; |
91c6d400 | 2602 | |
0e285d36 SAS |
2603 | err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, |
2604 | mce_cpu_dead); | |
2605 | if (err) | |
2606 | goto err_out_mem; | |
91c6d400 | 2607 | |
8c0eeac8 SAS |
2608 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", |
2609 | mce_cpu_online, mce_cpu_pre_down); | |
2610 | if (err < 0) | |
0e285d36 | 2611 | goto err_out_online; |
8c0eeac8 | 2612 | hp_online = err; |
93b62c3c | 2613 | |
9c15a24b MS |
2614 | register_syscore_ops(&mce_syscore_ops); |
2615 | ||
93b62c3c | 2616 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2617 | err = misc_register(&mce_chrdev_device); |
2618 | if (err) | |
2619 | goto err_register; | |
2620 | ||
2621 | return 0; | |
2622 | ||
2623 | err_register: | |
2624 | unregister_syscore_ops(&mce_syscore_ops); | |
8c0eeac8 | 2625 | cpuhp_remove_state(hp_online); |
9c15a24b | 2626 | |
0e285d36 SAS |
2627 | err_out_online: |
2628 | cpuhp_remove_state(CPUHP_X86_MCE_DEAD); | |
9c15a24b MS |
2629 | |
2630 | err_out_mem: | |
2631 | free_cpumask_var(mce_device_initialized); | |
2632 | ||
2633 | err_out: | |
2634 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2635 | |
1da177e4 | 2636 | return err; |
1da177e4 | 2637 | } |
cef12ee5 | 2638 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2639 | |
d7c3c9a6 AK |
2640 | /* |
2641 | * Old style boot options parsing. Only for compatibility. | |
2642 | */ | |
2643 | static int __init mcheck_disable(char *str) | |
2644 | { | |
1462594b | 2645 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2646 | return 1; |
2647 | } | |
2648 | __setup("nomce", mcheck_disable); | |
a988d334 | 2649 | |
5be9ed25 HY |
2650 | #ifdef CONFIG_DEBUG_FS |
2651 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2652 | { |
5be9ed25 | 2653 | static struct dentry *dmce; |
a988d334 | 2654 | |
5be9ed25 HY |
2655 | if (!dmce) |
2656 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2657 | |
5be9ed25 HY |
2658 | return dmce; |
2659 | } | |
a988d334 | 2660 | |
bf783f9f HY |
2661 | static void mce_reset(void) |
2662 | { | |
2663 | cpu_missing = 0; | |
c7c9b392 | 2664 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2665 | atomic_set(&mce_executing, 0); |
2666 | atomic_set(&mce_callin, 0); | |
2667 | atomic_set(&global_nwo, 0); | |
2668 | } | |
a988d334 | 2669 | |
bf783f9f HY |
2670 | static int fake_panic_get(void *data, u64 *val) |
2671 | { | |
2672 | *val = fake_panic; | |
2673 | return 0; | |
a988d334 IM |
2674 | } |
2675 | ||
bf783f9f | 2676 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2677 | { |
bf783f9f HY |
2678 | mce_reset(); |
2679 | fake_panic = val; | |
2680 | return 0; | |
a988d334 | 2681 | } |
a988d334 | 2682 | |
bf783f9f HY |
2683 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2684 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2685 | |
5e09954a | 2686 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2687 | { |
bf783f9f HY |
2688 | struct dentry *dmce, *ffake_panic; |
2689 | ||
2690 | dmce = mce_get_debugfs_dir(); | |
2691 | if (!dmce) | |
2692 | return -ENOMEM; | |
2693 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2694 | &fake_panic_fops); | |
2695 | if (!ffake_panic) | |
2696 | return -ENOMEM; | |
2697 | ||
2698 | return 0; | |
d7c3c9a6 | 2699 | } |
fd4cf79f CG |
2700 | #else |
2701 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2702 | #endif |
fd4cf79f | 2703 | |
3637efb0 TL |
2704 | DEFINE_STATIC_KEY_FALSE(mcsafe_key); |
2705 | EXPORT_SYMBOL_GPL(mcsafe_key); | |
2706 | ||
fd4cf79f CG |
2707 | static int __init mcheck_late_init(void) |
2708 | { | |
3637efb0 TL |
2709 | if (mca_cfg.recovery) |
2710 | static_branch_inc(&mcsafe_key); | |
2711 | ||
fd4cf79f CG |
2712 | mcheck_debugfs_init(); |
2713 | ||
2714 | /* | |
2715 | * Flush out everything that has been logged during early boot, now that | |
2716 | * everything has been initialized (workqueues, decoders, ...). | |
2717 | */ | |
2718 | mce_schedule_work(); | |
2719 | ||
2720 | return 0; | |
2721 | } | |
2722 | late_initcall(mcheck_late_init); |