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307a2e9a JC |
1 | /* |
2 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. | |
3 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
4 | * Jeffy Chen <jeffy.chen@rock-chips.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk-provider.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/syscore_ops.h> | |
21 | #include <dt-bindings/clock/rk3228-cru.h> | |
22 | #include "clk.h" | |
23 | ||
24 | #define RK3228_GRF_SOC_STATUS0 0x480 | |
25 | ||
26 | enum rk3228_plls { | |
27 | apll, dpll, cpll, gpll, | |
28 | }; | |
29 | ||
30 | static struct rockchip_pll_rate_table rk3228_pll_rates[] = { | |
31 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
32 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
33 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
34 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
46 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
47 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
48 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
49 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
50 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
51 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
52 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
53 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
54 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), | |
59 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), | |
61 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), | |
63 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), | |
64 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), | |
65 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), | |
66 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), | |
67 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), | |
68 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), | |
69 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), | |
70 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), | |
71 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), | |
72 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), | |
73 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), | |
74 | { /* sentinel */ }, | |
75 | }; | |
76 | ||
77 | #define RK3228_DIV_CPU_MASK 0x1f | |
78 | #define RK3228_DIV_CPU_SHIFT 8 | |
79 | ||
80 | #define RK3228_DIV_PERI_MASK 0xf | |
81 | #define RK3228_DIV_PERI_SHIFT 0 | |
82 | #define RK3228_DIV_ACLK_MASK 0x7 | |
83 | #define RK3228_DIV_ACLK_SHIFT 4 | |
84 | #define RK3228_DIV_HCLK_MASK 0x3 | |
85 | #define RK3228_DIV_HCLK_SHIFT 8 | |
86 | #define RK3228_DIV_PCLK_MASK 0x7 | |
87 | #define RK3228_DIV_PCLK_SHIFT 12 | |
88 | ||
f88b8e73 | 89 | #define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \ |
307a2e9a JC |
90 | { \ |
91 | .reg = RK2928_CLKSEL_CON(1), \ | |
92 | .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ | |
f88b8e73 EZ |
93 | RK3228_DIV_PERI_SHIFT) | \ |
94 | HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \ | |
95 | RK3228_DIV_ACLK_SHIFT), \ | |
96 | } | |
307a2e9a | 97 | |
f88b8e73 EZ |
98 | #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \ |
99 | { \ | |
100 | .prate = _prate, \ | |
101 | .divs = { \ | |
102 | RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \ | |
103 | }, \ | |
307a2e9a JC |
104 | } |
105 | ||
106 | static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { | |
f88b8e73 EZ |
107 | RK3228_CPUCLK_RATE(1800000000, 1, 7), |
108 | RK3228_CPUCLK_RATE(1704000000, 1, 7), | |
109 | RK3228_CPUCLK_RATE(1608000000, 1, 7), | |
110 | RK3228_CPUCLK_RATE(1512000000, 1, 7), | |
111 | RK3228_CPUCLK_RATE(1488000000, 1, 5), | |
112 | RK3228_CPUCLK_RATE(1416000000, 1, 5), | |
113 | RK3228_CPUCLK_RATE(1392000000, 1, 5), | |
114 | RK3228_CPUCLK_RATE(1296000000, 1, 5), | |
115 | RK3228_CPUCLK_RATE(1200000000, 1, 5), | |
116 | RK3228_CPUCLK_RATE(1104000000, 1, 5), | |
117 | RK3228_CPUCLK_RATE(1008000000, 1, 5), | |
118 | RK3228_CPUCLK_RATE(912000000, 1, 5), | |
119 | RK3228_CPUCLK_RATE(816000000, 1, 3), | |
120 | RK3228_CPUCLK_RATE(696000000, 1, 3), | |
121 | RK3228_CPUCLK_RATE(600000000, 1, 3), | |
122 | RK3228_CPUCLK_RATE(408000000, 1, 1), | |
123 | RK3228_CPUCLK_RATE(312000000, 1, 1), | |
124 | RK3228_CPUCLK_RATE(216000000, 1, 1), | |
125 | RK3228_CPUCLK_RATE(96000000, 1, 1), | |
307a2e9a JC |
126 | }; |
127 | ||
128 | static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { | |
129 | .core_reg = RK2928_CLKSEL_CON(0), | |
130 | .div_core_shift = 0, | |
131 | .div_core_mask = 0x1f, | |
268aebaa XZ |
132 | .mux_core_alt = 1, |
133 | .mux_core_main = 0, | |
307a2e9a | 134 | .mux_core_shift = 6, |
268aebaa | 135 | .mux_core_mask = 0x1, |
307a2e9a JC |
136 | }; |
137 | ||
138 | PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; | |
139 | ||
140 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; | |
141 | PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; | |
142 | PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; | |
143 | PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; | |
144 | PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; | |
145 | PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; | |
146 | ||
292a391e | 147 | PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" }; |
307a2e9a JC |
148 | PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; |
149 | PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; | |
150 | PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; | |
151 | PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" }; | |
152 | PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; | |
153 | PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; | |
154 | ||
155 | PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; | |
156 | ||
157 | PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; | |
158 | PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; | |
159 | ||
160 | PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; | |
161 | PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; | |
162 | PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; | |
163 | PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; | |
164 | PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; | |
165 | ||
307a2e9a JC |
166 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; |
167 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; | |
168 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; | |
169 | ||
09f68422 XZ |
170 | PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" }; |
171 | PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" }; | |
307a2e9a JC |
172 | PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; |
173 | ||
174 | static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { | |
175 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
176 | RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), | |
177 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), | |
178 | RK2928_MODE_CON, 4, 6, 0, NULL), | |
179 | [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), | |
180 | RK2928_MODE_CON, 8, 8, 0, NULL), | |
181 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), | |
182 | RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), | |
183 | }; | |
184 | ||
185 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
186 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
187 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
188 | ||
cb87df58 XZ |
189 | static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata = |
190 | MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, | |
191 | RK2928_CLKSEL_CON(9), 8, 2, MFLAGS); | |
192 | ||
193 | static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata = | |
194 | MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, | |
195 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); | |
196 | ||
197 | static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata = | |
198 | MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, | |
199 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); | |
200 | ||
201 | static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata = | |
202 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, | |
203 | RK2928_CLKSEL_CON(6), 8, 2, MFLAGS); | |
204 | ||
205 | static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata = | |
206 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, | |
207 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); | |
208 | ||
209 | static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata = | |
210 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, | |
211 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); | |
212 | ||
213 | static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata = | |
214 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, | |
215 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); | |
216 | ||
307a2e9a JC |
217 | static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { |
218 | /* | |
219 | * Clock-Architecture Diagram 1 | |
220 | */ | |
221 | ||
222 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, | |
223 | RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), | |
224 | ||
225 | /* PD_DDR */ | |
226 | GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, | |
227 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
228 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
229 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
230 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, | |
231 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
232 | COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
233 | RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
234 | RK2928_CLKGATE_CON(7), 1, GFLAGS), | |
235 | GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED, | |
236 | RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
36714529 | 237 | FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, |
307a2e9a JC |
238 | RK2928_CLKGATE_CON(7), 0, GFLAGS), |
239 | ||
240 | /* PD_CORE */ | |
241 | GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, | |
242 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
243 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, | |
244 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
245 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, | |
246 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
247 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
248 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
249 | RK2928_CLKGATE_CON(4), 1, GFLAGS), | |
250 | COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, | |
251 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
252 | RK2928_CLKGATE_CON(4), 0, GFLAGS), | |
253 | ||
254 | /* PD_MISC */ | |
255 | MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, | |
256 | RK2928_MISC_CON, 13, 1, MFLAGS), | |
257 | MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, | |
258 | RK2928_MISC_CON, 14, 1, MFLAGS), | |
259 | MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, | |
260 | RK2928_MISC_CON, 15, 1, MFLAGS), | |
261 | ||
262 | /* PD_BUS */ | |
263 | GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, | |
264 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
265 | GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, | |
266 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
267 | GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, | |
268 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
269 | COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, | |
270 | RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), | |
5d259562 | 271 | GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0, |
307a2e9a | 272 | RK2928_CLKGATE_CON(6), 0, GFLAGS), |
5d259562 | 273 | COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0, |
307a2e9a JC |
274 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, |
275 | RK2928_CLKGATE_CON(6), 1, GFLAGS), | |
276 | COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, | |
277 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, | |
278 | RK2928_CLKGATE_CON(6), 2, GFLAGS), | |
5d259562 | 279 | GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0, |
307a2e9a JC |
280 | RK2928_CLKGATE_CON(6), 3, GFLAGS), |
281 | GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, | |
282 | RK2928_CLKGATE_CON(6), 4, GFLAGS), | |
283 | GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, | |
284 | RK2928_CLKGATE_CON(6), 13, GFLAGS), | |
285 | ||
286 | /* PD_VIDEO */ | |
5d259562 | 287 | COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
288 | RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, |
289 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
5d259562 | 290 | FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, |
307a2e9a JC |
291 | RK2928_CLKGATE_CON(4), 4, GFLAGS), |
292 | ||
5d259562 | 293 | COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
294 | RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, |
295 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
5d259562 | 296 | FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, |
307a2e9a JC |
297 | RK2928_CLKGATE_CON(4), 5, GFLAGS), |
298 | ||
5d259562 | 299 | COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
300 | RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, |
301 | RK2928_CLKGATE_CON(3), 3, GFLAGS), | |
302 | ||
5d259562 | 303 | COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
304 | RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS, |
305 | RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
306 | ||
307 | /* PD_VIO */ | |
5d259562 | 308 | COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
309 | RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS, |
310 | RK2928_CLKGATE_CON(3), 0, GFLAGS), | |
5d259562 | 311 | DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0, |
307a2e9a JC |
312 | RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), |
313 | ||
5d259562 | 314 | COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
315 | RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS, |
316 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
317 | ||
318 | MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, | |
319 | RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), | |
5d259562 | 320 | COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0, |
307a2e9a JC |
321 | RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, |
322 | RK2928_CLKGATE_CON(1), 2, GFLAGS), | |
5d259562 | 323 | COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0, |
307a2e9a JC |
324 | RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS, |
325 | RK2928_CLKGATE_CON(3), 6, GFLAGS), | |
326 | ||
5d259562 | 327 | COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
328 | RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS, |
329 | RK2928_CLKGATE_CON(1), 1, GFLAGS), | |
330 | ||
5d259562 | 331 | COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0, |
307a2e9a JC |
332 | RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS, |
333 | RK2928_CLKGATE_CON(3), 5, GFLAGS), | |
334 | ||
bdc7deec | 335 | GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, |
307a2e9a JC |
336 | RK2928_CLKGATE_CON(3), 7, GFLAGS), |
337 | ||
5d259562 | 338 | COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, |
307a2e9a JC |
339 | RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS, |
340 | RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
341 | ||
342 | /* PD_PERI */ | |
343 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, | |
344 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
345 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, | |
346 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
347 | GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, | |
348 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
349 | COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, | |
350 | RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), | |
351 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, | |
352 | RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, | |
353 | RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
354 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, | |
355 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS, | |
356 | RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
357 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, | |
358 | RK2928_CLKGATE_CON(5), 0, GFLAGS), | |
359 | ||
360 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, | |
361 | RK2928_CLKGATE_CON(6), 5, GFLAGS), | |
362 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, | |
363 | RK2928_CLKGATE_CON(6), 6, GFLAGS), | |
364 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, | |
365 | RK2928_CLKGATE_CON(6), 7, GFLAGS), | |
366 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, | |
367 | RK2928_CLKGATE_CON(6), 8, GFLAGS), | |
368 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, | |
369 | RK2928_CLKGATE_CON(6), 9, GFLAGS), | |
370 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, | |
371 | RK2928_CLKGATE_CON(6), 10, GFLAGS), | |
372 | ||
5d259562 | 373 | COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
374 | RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS, |
375 | RK2928_CLKGATE_CON(2), 7, GFLAGS), | |
376 | ||
5d259562 | 377 | COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
378 | RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS, |
379 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
380 | ||
5d259562 | 381 | GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0, |
67de7901 | 382 | RK2928_CLKGATE_CON(10), 12, GFLAGS), |
307a2e9a | 383 | |
5d259562 | 384 | COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, |
307a2e9a JC |
385 | RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, |
386 | RK2928_CLKGATE_CON(2), 15, GFLAGS), | |
387 | ||
a225a3ba | 388 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, |
307a2e9a JC |
389 | RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, |
390 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
391 | ||
fe53230c | 392 | COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0, |
307a2e9a JC |
393 | RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, |
394 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
395 | DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, | |
396 | RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), | |
397 | ||
398 | COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, | |
399 | RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, | |
400 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
401 | DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, | |
402 | RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), | |
403 | ||
404 | /* | |
405 | * Clock-Architecture Diagram 2 | |
406 | */ | |
407 | ||
408 | GATE(0, "gpll_vop", "gpll", 0, | |
409 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
410 | GATE(0, "cpll_vop", "cpll", 0, | |
411 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
412 | MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, | |
413 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), | |
bdc7deec | 414 | DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, |
307a2e9a JC |
415 | RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), |
416 | DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, | |
417 | RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), | |
0a9d4ac0 | 418 | MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, |
307a2e9a JC |
419 | RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), |
420 | ||
36714529 HS |
421 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), |
422 | ||
307a2e9a JC |
423 | COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, |
424 | RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
425 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
cb87df58 | 426 | COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, |
67de7901 | 427 | RK2928_CLKSEL_CON(8), 0, |
cb87df58 XZ |
428 | RK2928_CLKGATE_CON(0), 4, GFLAGS, |
429 | &rk3228_i2s0_fracmux), | |
430 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
431 | RK2928_CLKGATE_CON(0), 5, GFLAGS), |
432 | ||
433 | COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, | |
434 | RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
435 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
cb87df58 | 436 | COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, |
67de7901 | 437 | RK2928_CLKSEL_CON(7), 0, |
cb87df58 XZ |
438 | RK2928_CLKGATE_CON(0), 11, GFLAGS, |
439 | &rk3228_i2s1_fracmux), | |
440 | GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
441 | RK2928_CLKGATE_CON(0), 14, GFLAGS), |
442 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, | |
443 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, | |
444 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
445 | ||
446 | COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, | |
447 | RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
448 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
cb87df58 | 449 | COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, |
67de7901 | 450 | RK2928_CLKSEL_CON(30), 0, |
cb87df58 XZ |
451 | RK2928_CLKGATE_CON(0), 8, GFLAGS, |
452 | &rk3228_i2s2_fracmux), | |
453 | GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
454 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
455 | ||
456 | COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, | |
457 | RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
458 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
cb87df58 | 459 | COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, |
67de7901 | 460 | RK2928_CLKSEL_CON(20), 0, |
cb87df58 XZ |
461 | RK2928_CLKGATE_CON(2), 12, GFLAGS, |
462 | &rk3228_spdif_fracmux), | |
307a2e9a | 463 | |
f18c0994 | 464 | GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, |
307a2e9a JC |
465 | RK2928_CLKGATE_CON(1), 3, GFLAGS), |
466 | ||
5d259562 | 467 | GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0, |
307a2e9a | 468 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
5d259562 | 469 | GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0, |
307a2e9a JC |
470 | RK2928_CLKGATE_CON(1), 6, GFLAGS), |
471 | ||
a3cb9aa4 | 472 | COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, |
307a2e9a JC |
473 | RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, |
474 | RK2928_CLKGATE_CON(2), 8, GFLAGS), | |
475 | ||
22721881 JS |
476 | COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0, |
477 | RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS, | |
307a2e9a | 478 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
307a2e9a JC |
479 | |
480 | COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, | |
481 | RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
482 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
483 | ||
484 | /* PD_UART */ | |
485 | COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
486 | RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
487 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
488 | COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
489 | RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
490 | RK2928_CLKGATE_CON(1), 10, GFLAGS), | |
491 | COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, | |
492 | 0, RK2928_CLKSEL_CON(15), 12, 2, | |
493 | MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), | |
cb87df58 | 494 | COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, |
307a2e9a | 495 | RK2928_CLKSEL_CON(17), 0, |
cb87df58 XZ |
496 | RK2928_CLKGATE_CON(1), 9, GFLAGS, |
497 | &rk3228_uart0_fracmux), | |
498 | COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, | |
307a2e9a | 499 | RK2928_CLKSEL_CON(18), 0, |
cb87df58 XZ |
500 | RK2928_CLKGATE_CON(1), 11, GFLAGS, |
501 | &rk3228_uart1_fracmux), | |
502 | COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, | |
307a2e9a | 503 | RK2928_CLKSEL_CON(19), 0, |
cb87df58 XZ |
504 | RK2928_CLKGATE_CON(1), 13, GFLAGS, |
505 | &rk3228_uart2_fracmux), | |
307a2e9a JC |
506 | |
507 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, | |
508 | RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, | |
509 | RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
510 | ||
6e3732a2 | 511 | COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
512 | RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, |
513 | RK2928_CLKGATE_CON(1), 7, GFLAGS), | |
6e3732a2 | 514 | MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0, |
307a2e9a | 515 | RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), |
6e3732a2 | 516 | MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, |
307a2e9a | 517 | RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), |
6e3732a2 | 518 | GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0, |
307a2e9a | 519 | RK2928_CLKGATE_CON(5), 4, GFLAGS), |
6e3732a2 | 520 | GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0, |
307a2e9a | 521 | RK2928_CLKGATE_CON(5), 3, GFLAGS), |
6e3732a2 | 522 | GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0, |
307a2e9a | 523 | RK2928_CLKGATE_CON(5), 5, GFLAGS), |
6e3732a2 | 524 | GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0, |
307a2e9a | 525 | RK2928_CLKGATE_CON(5), 6, GFLAGS), |
6e3732a2 | 526 | COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0, |
307a2e9a JC |
527 | RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, |
528 | RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
6e3732a2 | 529 | COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
530 | RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, |
531 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
532 | ||
533 | /* | |
534 | * Clock-Architecture Diagram 3 | |
535 | */ | |
536 | ||
537 | /* PD_VOP */ | |
5d259562 | 538 | GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS), |
307a2e9a | 539 | GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS), |
5d259562 | 540 | GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS), |
307a2e9a JC |
541 | GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS), |
542 | ||
0a9d4ac0 | 543 | GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS), |
307a2e9a JC |
544 | GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS), |
545 | ||
5d259562 | 546 | GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS), |
307a2e9a JC |
547 | GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS), |
548 | ||
5d259562 EZ |
549 | GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS), |
550 | GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS), | |
0a9d4ac0 | 551 | GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS), |
307a2e9a JC |
552 | GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS), |
553 | GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS), | |
554 | GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS), | |
5d259562 EZ |
555 | GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS), |
556 | GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS), | |
bdc7deec | 557 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), |
5d259562 EZ |
558 | GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS), |
559 | GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS), | |
307a2e9a JC |
560 | |
561 | /* PD_PERI */ | |
562 | GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), | |
6e3732a2 | 563 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), |
307a2e9a JC |
564 | |
565 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), | |
566 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), | |
567 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS), | |
568 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS), | |
5d259562 | 569 | GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS), |
307a2e9a | 570 | GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS), |
5d259562 | 571 | GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS), |
307a2e9a | 572 | GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS), |
5d259562 EZ |
573 | GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS), |
574 | GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS), | |
307a2e9a JC |
575 | GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS), |
576 | GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), | |
577 | GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), | |
578 | ||
6e3732a2 | 579 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), |
307a2e9a JC |
580 | GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), |
581 | ||
582 | /* PD_GPU */ | |
22721881 JS |
583 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), |
584 | GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), | |
307a2e9a JC |
585 | |
586 | /* PD_BUS */ | |
587 | GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
588 | GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
589 | GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
590 | GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
591 | ||
592 | GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), | |
a45c072b XZ |
593 | GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), |
594 | GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), | |
595 | GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
596 | GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
5d259562 EZ |
597 | GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), |
598 | GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
599 | GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), | |
307a2e9a JC |
600 | |
601 | GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
602 | GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
603 | GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
604 | ||
5d259562 EZ |
605 | GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), |
606 | GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS), | |
307a2e9a JC |
607 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), |
608 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), | |
609 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), | |
610 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), | |
611 | GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS), | |
612 | GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
613 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), | |
614 | GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), | |
615 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), | |
616 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), | |
617 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS), | |
618 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS), | |
619 | GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), | |
620 | GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS), | |
621 | GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS), | |
a3cb9aa4 | 622 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), |
307a2e9a JC |
623 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS), |
624 | GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
625 | GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
626 | GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
627 | ||
628 | GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
629 | GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS), | |
bdc7deec | 630 | GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), |
307a2e9a JC |
631 | GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), |
632 | GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), | |
633 | ||
5d259562 | 634 | GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS), |
307a2e9a | 635 | GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS), |
5d259562 | 636 | GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS), |
307a2e9a | 637 | GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS), |
5d259562 | 638 | GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS), |
307a2e9a | 639 | GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS), |
5d259562 | 640 | GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS), |
307a2e9a JC |
641 | GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS), |
642 | ||
643 | /* PD_MMC */ | |
644 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), | |
bb07698f | 645 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), |
307a2e9a JC |
646 | |
647 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), | |
bb07698f | 648 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), |
307a2e9a JC |
649 | |
650 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), | |
bb07698f | 651 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), |
307a2e9a JC |
652 | }; |
653 | ||
654 | static const char *const rk3228_critical_clocks[] __initconst = { | |
655 | "aclk_cpu", | |
f18c0994 EZ |
656 | "pclk_cpu", |
657 | "hclk_cpu", | |
307a2e9a JC |
658 | "aclk_peri", |
659 | "hclk_peri", | |
660 | "pclk_peri", | |
f18c0994 EZ |
661 | "aclk_rga_noc", |
662 | "aclk_iep_noc", | |
663 | "aclk_vop_noc", | |
664 | "aclk_hdcp_noc", | |
665 | "hclk_vio_ahb_arbi", | |
666 | "hclk_vio_noc", | |
667 | "hclk_vop_noc", | |
668 | "hclk_host0_arb", | |
669 | "hclk_host1_arb", | |
670 | "hclk_host2_arb", | |
671 | "hclk_otg_pmu", | |
672 | "aclk_gpu_noc", | |
673 | "sclk_initmem_mbist", | |
674 | "aclk_initmem", | |
675 | "hclk_rom", | |
676 | "pclk_ddrupctl", | |
677 | "pclk_ddrmon", | |
678 | "pclk_msch_noc", | |
679 | "pclk_stimer", | |
680 | "pclk_ddrphy", | |
681 | "pclk_acodecphy", | |
682 | "pclk_phy_noc", | |
683 | "aclk_vpu_noc", | |
684 | "aclk_rkvdec_noc", | |
685 | "hclk_vpu_noc", | |
686 | "hclk_rkvdec_noc", | |
307a2e9a JC |
687 | }; |
688 | ||
689 | static void __init rk3228_clk_init(struct device_node *np) | |
690 | { | |
ef1d9fee | 691 | struct rockchip_clk_provider *ctx; |
307a2e9a | 692 | void __iomem *reg_base; |
307a2e9a JC |
693 | |
694 | reg_base = of_iomap(np, 0); | |
695 | if (!reg_base) { | |
696 | pr_err("%s: could not map cru region\n", __func__); | |
697 | return; | |
698 | } | |
699 | ||
ef1d9fee XZ |
700 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
701 | if (IS_ERR(ctx)) { | |
702 | pr_err("%s: rockchip clk init failed\n", __func__); | |
1d003eb0 | 703 | iounmap(reg_base); |
ef1d9fee XZ |
704 | return; |
705 | } | |
307a2e9a | 706 | |
ef1d9fee | 707 | rockchip_clk_register_plls(ctx, rk3228_pll_clks, |
307a2e9a JC |
708 | ARRAY_SIZE(rk3228_pll_clks), |
709 | RK3228_GRF_SOC_STATUS0); | |
ef1d9fee | 710 | rockchip_clk_register_branches(ctx, rk3228_clk_branches, |
307a2e9a JC |
711 | ARRAY_SIZE(rk3228_clk_branches)); |
712 | rockchip_clk_protect_critical(rk3228_critical_clocks, | |
713 | ARRAY_SIZE(rk3228_critical_clocks)); | |
714 | ||
ef1d9fee | 715 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", |
307a2e9a JC |
716 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
717 | &rk3228_cpuclk_data, rk3228_cpuclk_rates, | |
718 | ARRAY_SIZE(rk3228_cpuclk_rates)); | |
719 | ||
720 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
721 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
722 | ||
ef1d9fee XZ |
723 | rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL); |
724 | ||
725 | rockchip_clk_of_add_provider(np, ctx); | |
307a2e9a JC |
726 | } |
727 | CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); |