[people/arne_f/kernel.git] / drivers / edac / i82443bxgx_edac.c

/*
 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
 * module (C) 2006 Tim Small
 *
 * This file may be distributed under the terms of the GNU General
 * Public License.
 *
 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
 * others.
 *
 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
 *
 * Written with reference to 82443BX Host Bridge Datasheet:
 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
 * references to this document given in [].
 *
 * This module doesn't support the 440LX, but it may be possible to
 * make it do so (the 440LX's register definitions are different, but
 * not completely so - I haven't studied them in enough detail to know
 * how easy this would be).
 */

#include <linux/module.h>
#include <linux/init.h>

#include <linux/pci.h>
#include <linux/pci_ids.h>


#include <linux/edac.h>
#include "edac_module.h"

#define EDAC_MOD_STR    "i82443bxgx_edac"

/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
 * rows" "The 82443BX supports multiple-bit error detection and
 * single-bit error correction when ECC mode is enabled and
 * single/multi-bit error detection when correction is disabled.
 * During writes to the DRAM, the 82443BX generates ECC for the data
 * on a QWord basis. Partial QWord writes require a read-modify-write
 * cycle when ECC is enabled."
*/

/* "Additionally, the 82443BX ensures that the data is corrected in
 * main memory so that accumulation of errors is prevented. Another
 * error within the same QWord would result in a double-bit error
 * which is unrecoverable. This is known as hardware scrubbing since
 * it requires no software intervention to correct the data in memory."
 */

/* [Also see page 100 (section 4.3), "DRAM Interface"]
 * [Also see page 112 (section 4.6.1.4), ECC]
 */

#define I82443BXGX_NR_CSROWS 8
#define I82443BXGX_NR_CHANS  1
#define I82443BXGX_NR_DIMMS  4

/* 82443 PCI Device 0 */
#define I82443BXGX_NBXCFG 0x50	/* 32bit register starting at this PCI
				 * config space offset */
#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24	/* Array of bits, zero if
						 * row is non-ECC */
#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12	/* 2 bits,00=100MHz,10=66 MHz */

#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7	/* 2 bits:       */
#define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0	/* 00 = Non-ECC */
#define I82443BXGX_NBXCFG_INTEGRITY_EC     0x1	/* 01 = EC (only) */
#define I82443BXGX_NBXCFG_INTEGRITY_ECC    0x2	/* 10 = ECC */
#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB  0x3	/* 11 = ECC + HW Scrub */

#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE  6

/* 82443 PCI Device 0 */
#define I82443BXGX_EAP   0x80	/* 32bit register starting at this PCI
				 * config space offset, Error Address
				 * Pointer Register */
#define I82443BXGX_EAP_OFFSET_EAP  12	/* High 20 bits of error address */
#define I82443BXGX_EAP_OFFSET_MBE  BIT(1)	/* Err at EAP was multi-bit (W1TC) */
#define I82443BXGX_EAP_OFFSET_SBE  BIT(0)	/* Err at EAP was single-bit (W1TC) */

#define I82443BXGX_ERRCMD  0x90	/* 8bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1)	/* 1 = enable */
#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0)	/* 1 = enable */

#define I82443BXGX_ERRSTS  0x91	/* 16bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5	/* 3 bits - first err row multibit */
#define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4)	/* 1 = MBE occurred */
#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1	/* 3 bits - first err row singlebit */
#define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0)	/* 1 = SBE occurred */

#define I82443BXGX_DRAMC 0x57	/* 8bit register starting at this PCI
				 * config space offset. */
#define I82443BXGX_DRAMC_OFFSET_DT 3	/* 2 bits, DRAM Type */
#define I82443BXGX_DRAMC_DRAM_IS_EDO 0	/* 00 = EDO */
#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1	/* 01 = SDRAM */
#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2	/* 10 = Registered SDRAM */

#define I82443BXGX_DRB 0x60	/* 8x 8bit registers starting at this PCI
				 * config space offset. */

/* FIXME - don't poll when ECC disabled? */

struct i82443bxgx_edacmc_error_info {
	u32 eap;
};

static struct edac_pci_ctl_info *i82443bxgx_pci;

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
					 * already registered driver
					 */

static int i82443bxgx_registered = 1;

static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
				struct i82443bxgx_edacmc_error_info
				*info)
{
	struct pci_dev *pdev;
	pdev = to_pci_dev(mci->pdev);
	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
		/* Clear error to allow next error to be reported [p.61] */
		pci_write_bits32(pdev, I82443BXGX_EAP,
				 I82443BXGX_EAP_OFFSET_SBE,
				 I82443BXGX_EAP_OFFSET_SBE);

	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
		/* Clear error to allow next error to be reported [p.61] */
		pci_write_bits32(pdev, I82443BXGX_EAP,
				 I82443BXGX_EAP_OFFSET_MBE,
				 I82443BXGX_EAP_OFFSET_MBE);
}

static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
						struct
						i82443bxgx_edacmc_error_info
						*info, int handle_errors)
{
	int error_found = 0;
	u32 eapaddr, page, pageoffset;

	/* bits 30:12 hold the 4kb block in which the error occurred
	 * [p.61] */
	eapaddr = (info->eap & 0xfffff000);
	page = eapaddr >> PAGE_SHIFT;
	pageoffset = eapaddr - (page << PAGE_SHIFT);

	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
		error_found = 1;
		if (handle_errors)
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     page, pageoffset, 0,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1, mci->ctl_name, "");
	}

	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
		error_found = 1;
		if (handle_errors)
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     page, pageoffset, 0,
					     edac_mc_find_csrow_by_page(mci, page),
					     0, -1, mci->ctl_name, "");
	}

	return error_found;
}

static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
{
	struct i82443bxgx_edacmc_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i82443bxgx_edacmc_get_error_info(mci, &info);
	i82443bxgx_edacmc_process_error_info(mci, &info, 1);
}

static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
				struct pci_dev *pdev,
				enum edac_type edac_mode,
				enum mem_type mtype)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	int index;
	u8 drbar, dramc;
	u32 row_base, row_high_limit, row_high_limit_last;

	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	row_high_limit_last = 0;
	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
		edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
			 mci->mc_idx, index, drbar);
		row_high_limit = ((u32) drbar << 23);
		/* find the DRAM Chip Select Base address and mask */
		edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
			 mci->mc_idx, index, row_high_limit,
			 row_high_limit_last);

		/* 440GX goes to 2GB, represented with a DRB of 0. */
		if (row_high_limit_last && !row_high_limit)
			row_high_limit = 1UL << 31;

		/* This row is empty [p.49] */
		if (row_high_limit == row_high_limit_last)
			continue;
		row_base = row_high_limit_last;
		csrow->first_page = row_base >> PAGE_SHIFT;
		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
		dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
		/* EAP reports in 4kilobyte granularity [61] */
		dimm->grain = 1 << 12;
		dimm->mtype = mtype;
		/* I don't think 440BX can tell you device type? FIXME? */
		dimm->dtype = DEV_UNKNOWN;
		/* Mode is global to all rows on 440BX */
		dimm->edac_mode = edac_mode;
		row_high_limit_last = row_high_limit;
	}
}

static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	u8 dramc;
	u32 nbxcfg, ecc_mode;
	enum mem_type mtype;
	enum edac_type edac_mode;

	edac_dbg(0, "MC:\n");

	/* Something is really hosed if PCI config space reads from
	 * the MC aren't working.
	 */
	if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
		return -EIO;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I82443BXGX_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = I82443BXGX_NR_CHANS;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(0, "MC: mci = %p\n", mci);
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
	case I82443BXGX_DRAMC_DRAM_IS_EDO:
		mtype = MEM_EDO;
		break;
	case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
		mtype = MEM_SDR;
		break;
	case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
		mtype = MEM_RDR;
		break;
	default:
		edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
		mtype = -MEM_UNKNOWN;
	}

	if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
		mci->edac_cap = mci->edac_ctl_cap;
	else
		mci->edac_cap = EDAC_FLAG_NONE;

	mci->scrub_cap = SCRUB_FLAG_HW_SRC;
	pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
	ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
		(BIT(0) | BIT(1)));

	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
		? SCRUB_HW_SRC : SCRUB_NONE;

	switch (ecc_mode) {
	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
		edac_mode = EDAC_NONE;
		break;
	case I82443BXGX_NBXCFG_INTEGRITY_EC:
		edac_mode = EDAC_EC;
		break;
	case I82443BXGX_NBXCFG_INTEGRITY_ECC:
	case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
		edac_mode = EDAC_SECDED;
		break;
	default:
		edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
		edac_mode = EDAC_UNKNOWN;
		break;
	}

	i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);

	/* Many BIOSes don't clear error flags on boot, so do this
	 * here, or we get "phantom" errors occurring at module-load
	 * time. */
	pci_write_bits32(pdev, I82443BXGX_EAP,
			(I82443BXGX_EAP_OFFSET_SBE |
				I82443BXGX_EAP_OFFSET_MBE),
			(I82443BXGX_EAP_OFFSET_SBE |
				I82443BXGX_EAP_OFFSET_MBE));

	mci->mod_name = EDAC_MOD_STR;
	mci->ctl_name = "I82443BXGX";
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82443bxgx_edacmc_check;
	mci->ctl_page_to_phys = NULL;

	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82443bxgx_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
				      const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	/* don't need to call pci_enable_device() */
	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);

	if (mci_pdev == NULL)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (i82443bxgx_pci)
		edac_pci_release_generic_ctl(i82443bxgx_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i82443bxgx_pci_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);

static struct pci_driver i82443bxgx_edacmc_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82443bxgx_edacmc_init_one,
	.remove = i82443bxgx_edacmc_remove_one,
	.id_table = i82443bxgx_pci_tbl,
};

static int __init i82443bxgx_edacmc_init(void)
{
	int pci_rc;
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
	if (pci_rc < 0)
		goto fail0;

	if (mci_pdev == NULL) {
		const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
		int i = 0;
		i82443bxgx_registered = 0;

		while (mci_pdev == NULL && id->vendor != 0) {
			mci_pdev = pci_get_device(id->vendor,
					id->device, NULL);
			i++;
			id = &i82443bxgx_pci_tbl[i];
		}
		if (!mci_pdev) {
			edac_dbg(0, "i82443bxgx pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);

		if (pci_rc < 0) {
			edac_dbg(0, "i82443bxgx init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82443bxgx_edacmc_driver);

fail0:
	pci_dev_put(mci_pdev);
	return pci_rc;
}

static void __exit i82443bxgx_edacmc_exit(void)
{
	pci_unregister_driver(&i82443bxgx_edacmc_driver);

	if (!i82443bxgx_registered)
		i82443bxgx_edacmc_remove_one(mci_pdev);

	pci_dev_put(mci_pdev);
}

module_init(i82443bxgx_edacmc_init);
module_exit(i82443bxgx_edacmc_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
5a2c675c TS	1	/*
	2	* Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
	3	* module (C) 2006 Tim Small
	4	*
	5	* This file may be distributed under the terms of the GNU General
	6	* Public License.
	7	*
	8	* Written by Tim Small <tim@buttersideup.com>, based on work by Linux
	9	* Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
	10	* others.
	11	*
	12	* 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
	13	*
	14	* Written with reference to 82443BX Host Bridge Datasheet:
084a4fcc	15	* http://download.intel.com/design/chipsets/datashts/29063301.pdf
5a2c675c TS	16	* references to this document given in [].
	17	*
	18	* This module doesn't support the 440LX, but it may be possible to
	19	* make it do so (the 440LX's register definitions are different, but
	20	* not completely so - I haven't studied them in enough detail to know
	21	* how easy this would be).
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/init.h>
	26
	27	#include <linux/pci.h>
	28	#include <linux/pci_ids.h>
	29
5a2c675c	30
c3c52bce	31	#include <linux/edac.h>
78d88e8a	32	#include "edac_module.h"
5a2c675c	33
5a2c675c TS	34	#define EDAC_MOD_STR "i82443bxgx_edac"
5a2c675c TS	35
5a2c675c TS	36	/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
	37	* Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
	38	* rows" "The 82443BX supports multiple-bit error detection and
	39	* single-bit error correction when ECC mode is enabled and
	40	* single/multi-bit error detection when correction is disabled.
	41	* During writes to the DRAM, the 82443BX generates ECC for the data
	42	* on a QWord basis. Partial QWord writes require a read-modify-write
	43	* cycle when ECC is enabled."
	44	*/
	45
	46	/* "Additionally, the 82443BX ensures that the data is corrected in
	47	* main memory so that accumulation of errors is prevented. Another
	48	* error within the same QWord would result in a double-bit error
	49	* which is unrecoverable. This is known as hardware scrubbing since
	50	* it requires no software intervention to correct the data in memory."
	51	*/
	52
	53	/* [Also see page 100 (section 4.3), "DRAM Interface"]
	54	* [Also see page 112 (section 4.6.1.4), ECC]
	55	*/
	56
	57	#define I82443BXGX_NR_CSROWS 8
	58	#define I82443BXGX_NR_CHANS 1
	59	#define I82443BXGX_NR_DIMMS 4
	60
5a2c675c	61	/* 82443 PCI Device 0 */
11116601 DT	62	#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
	63	* config space offset */
	64	#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
	65	* row is non-ECC */
	66	#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
	67
	68	#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
	69	#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
	70	#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
	71	#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
	72	#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
5a2c675c TS	73
	74	#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
	75
5a2c675c	76	/* 82443 PCI Device 0 */
11116601 DT	77	#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
	78	* config space offset, Error Address
	79	* Pointer Register */
	80	#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
	81	#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
	82	#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
	83
	84	#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
5a2c675c	85	* config space offset. */
11116601 DT	86	#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
11116601 DT	87	#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
5a2c675c	88
11116601	89	#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
5a2c675c	90	* config space offset. */
11116601 DT	91	#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
	92	#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
	93	#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
	94	#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
5a2c675c	95
11116601 DT	96	#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
	97	* config space offset. */
	98	#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
	99	#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
5a2c675c	100	#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
11116601	101	#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
5a2c675c	102
11116601 DT	103	#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
11116601 DT	104	* config space offset. */
5a2c675c TS	105
	106	/* FIXME - don't poll when ECC disabled? */
	107
5a2c675c TS	108	struct i82443bxgx_edacmc_error_info {
	109	u32 eap;
	110	};
	111
456a2f95 DJ	112	static struct edac_pci_ctl_info *i82443bxgx_pci;
456a2f95 DJ	113
53a2fe58 VB	114	static struct pci_dev mci_pdev; / init dev: in case that AGP code has
	115	* already registered driver
	116	*/
	117
	118	static int i82443bxgx_registered = 1;
	119
11116601	120	static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
052dfb45 DT	121	struct i82443bxgx_edacmc_error_info
052dfb45 DT	122	*info)
5a2c675c TS	123	{
5a2c675c TS	124	struct pci_dev *pdev;
fd687502	125	pdev = to_pci_dev(mci->pdev);
5a2c675c TS	126	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
	127	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
	128	/* Clear error to allow next error to be reported [p.61] */
	129	pci_write_bits32(pdev, I82443BXGX_EAP,
	130	I82443BXGX_EAP_OFFSET_SBE,
	131	I82443BXGX_EAP_OFFSET_SBE);
	132
	133	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
	134	/* Clear error to allow next error to be reported [p.61] */
	135	pci_write_bits32(pdev, I82443BXGX_EAP,
	136	I82443BXGX_EAP_OFFSET_MBE,
	137	I82443BXGX_EAP_OFFSET_MBE);
	138	}
	139
11116601 DT	140	static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
	141	struct
	142	i82443bxgx_edacmc_error_info
	143	*info, int handle_errors)
5a2c675c TS	144	{
	145	int error_found = 0;
	146	u32 eapaddr, page, pageoffset;
	147
	148	/* bits 30:12 hold the 4kb block in which the error occurred
	149	* [p.61] */
	150	eapaddr = (info->eap & 0xfffff000);
	151	page = eapaddr >> PAGE_SHIFT;
	152	pageoffset = eapaddr - (page << PAGE_SHIFT);
	153
11116601	154	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
5a2c675c TS	155	error_found = 1;
5a2c675c TS	156	if (handle_errors)
9eb07a7f	157	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
40f562b1 MCC	158	page, pageoffset, 0,
40f562b1 MCC	159	edac_mc_find_csrow_by_page(mci, page),
03f7eae8	160	0, -1, mci->ctl_name, "");
5a2c675c TS	161	}
5a2c675c TS	162
11116601	163	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
5a2c675c TS	164	error_found = 1;
5a2c675c TS	165	if (handle_errors)
9eb07a7f	166	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
40f562b1 MCC	167	page, pageoffset, 0,
40f562b1 MCC	168	edac_mc_find_csrow_by_page(mci, page),
03f7eae8	169	0, -1, mci->ctl_name, "");
5a2c675c TS	170	}
	171
	172	return error_found;
	173	}
	174
5a2c675c TS	175	static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
	176	{
	177	struct i82443bxgx_edacmc_error_info info;
	178
956b9ba1	179	edac_dbg(1, "MC%d\n", mci->mc_idx);
5a2c675c TS	180	i82443bxgx_edacmc_get_error_info(mci, &info);
	181	i82443bxgx_edacmc_process_error_info(mci, &info, 1);
	182	}
	183
5a2c675c	184	static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
052dfb45 DT	185	struct pci_dev *pdev,
	186	enum edac_type edac_mode,
	187	enum mem_type mtype)
5a2c675c TS	188	{
5a2c675c TS	189	struct csrow_info *csrow;
084a4fcc	190	struct dimm_info *dimm;
5a2c675c TS	191	int index;
	192	u8 drbar, dramc;
	193	u32 row_base, row_high_limit, row_high_limit_last;
	194
	195	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	196	row_high_limit_last = 0;
	197	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	198	csrow = mci->csrows[index];
de3910eb MCC	199	dimm = csrow->channels[0]->dimm;
084a4fcc	200
5a2c675c	201	pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
956b9ba1 JP	202	edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
956b9ba1 JP	203	mci->mc_idx, index, drbar);
5a2c675c TS	204	row_high_limit = ((u32) drbar << 23);
5a2c675c TS	205	/* find the DRAM Chip Select Base address and mask */
956b9ba1 JP	206	edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
	207	mci->mc_idx, index, row_high_limit,
	208	row_high_limit_last);
5a2c675c TS	209
	210	/* 440GX goes to 2GB, represented with a DRB of 0. */
	211	if (row_high_limit_last && !row_high_limit)
	212	row_high_limit = 1UL << 31;
	213
	214	/* This row is empty [p.49] */
	215	if (row_high_limit == row_high_limit_last)
	216	continue;
	217	row_base = row_high_limit_last;
	218	csrow->first_page = row_base >> PAGE_SHIFT;
	219	csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
a895bf8b	220	dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
5a2c675c	221	/* EAP reports in 4kilobyte granularity [61] */
084a4fcc MCC	222	dimm->grain = 1 << 12;
084a4fcc MCC	223	dimm->mtype = mtype;
5a2c675c	224	/* I don't think 440BX can tell you device type? FIXME? */
084a4fcc	225	dimm->dtype = DEV_UNKNOWN;
5a2c675c	226	/* Mode is global to all rows on 440BX */
084a4fcc	227	dimm->edac_mode = edac_mode;
5a2c675c TS	228	row_high_limit_last = row_high_limit;
	229	}
	230	}
	231
11116601	232	static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
5a2c675c TS	233	{
5a2c675c TS	234	struct mem_ctl_info *mci;
40f562b1	235	struct edac_mc_layer layers[2];
5a2c675c TS	236	u8 dramc;
	237	u32 nbxcfg, ecc_mode;
	238	enum mem_type mtype;
	239	enum edac_type edac_mode;
	240
956b9ba1	241	edac_dbg(0, "MC:\n");
5a2c675c TS	242
5a2c675c TS	243	/* Something is really hosed if PCI config space reads from
052dfb45 DT	244	* the MC aren't working.
052dfb45 DT	245	*/
5a2c675c TS	246	if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
	247	return -EIO;
	248
40f562b1 MCC	249	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	250	layers[0].size = I82443BXGX_NR_CSROWS;
	251	layers[0].is_virt_csrow = true;
	252	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	253	layers[1].size = I82443BXGX_NR_CHANS;
	254	layers[1].is_virt_csrow = false;
ca0907b9	255	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
5a2c675c TS	256	if (mci == NULL)
	257	return -ENOMEM;
	258
956b9ba1	259	edac_dbg(0, "MC: mci = %p\n", mci);
fd687502	260	mci->pdev = &pdev->dev;
5a2c675c TS	261	mci->mtype_cap = MEM_FLAG_EDO \| MEM_FLAG_SDR \| MEM_FLAG_RDR;
	262	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
	263	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
	264	switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) \| BIT(1))) {
11116601	265	case I82443BXGX_DRAMC_DRAM_IS_EDO:
5a2c675c TS	266	mtype = MEM_EDO;
	267	break;
	268	case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
	269	mtype = MEM_SDR;
	270	break;
	271	case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
	272	mtype = MEM_RDR;
	273	break;
	274	default:
956b9ba1	275	edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
5a2c675c TS	276	mtype = -MEM_UNKNOWN;
	277	}
	278
	279	if ((mtype == MEM_SDR) \|\| (mtype == MEM_RDR))
	280	mci->edac_cap = mci->edac_ctl_cap;
	281	else
	282	mci->edac_cap = EDAC_FLAG_NONE;
	283
	284	mci->scrub_cap = SCRUB_FLAG_HW_SRC;
	285	pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
	286	ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
052dfb45	287	(BIT(0) \| BIT(1)));
5a2c675c TS	288
5a2c675c TS	289	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
052dfb45	290	? SCRUB_HW_SRC : SCRUB_NONE;
5a2c675c	291
11116601	292	switch (ecc_mode) {
5a2c675c TS	293	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
	294	edac_mode = EDAC_NONE;
	295	break;
	296	case I82443BXGX_NBXCFG_INTEGRITY_EC:
	297	edac_mode = EDAC_EC;
	298	break;
	299	case I82443BXGX_NBXCFG_INTEGRITY_ECC:
	300	case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
	301	edac_mode = EDAC_SECDED;
	302	break;
	303	default:
956b9ba1	304	edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
5a2c675c TS	305	edac_mode = EDAC_UNKNOWN;
	306	break;
	307	}
	308
	309	i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
	310
	311	/* Many BIOSes don't clear error flags on boot, so do this
25985edc	312	* here, or we get "phantom" errors occurring at module-load
5a2c675c TS	313	* time. */
5a2c675c TS	314	pci_write_bits32(pdev, I82443BXGX_EAP,
052dfb45 DT	315	(I82443BXGX_EAP_OFFSET_SBE \|
	316	I82443BXGX_EAP_OFFSET_MBE),
	317	(I82443BXGX_EAP_OFFSET_SBE \|
	318	I82443BXGX_EAP_OFFSET_MBE));
5a2c675c TS	319
5a2c675c TS	320	mci->mod_name = EDAC_MOD_STR;
5a2c675c	321	mci->ctl_name = "I82443BXGX";
c4192705	322	mci->dev_name = pci_name(pdev);
5a2c675c TS	323	mci->edac_check = i82443bxgx_edacmc_check;
	324	mci->ctl_page_to_phys = NULL;
	325
b8f6f975	326	if (edac_mc_add_mc(mci)) {
956b9ba1	327	edac_dbg(3, "failed edac_mc_add_mc()\n");
5a2c675c TS	328	goto fail;
	329	}
	330
456a2f95 DJ	331	/* allocating generic PCI control info */
	332	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	333	if (!i82443bxgx_pci) {
	334	printk(KERN_WARNING
	335	"%s(): Unable to create PCI control\n",
	336	__func__);
	337	printk(KERN_WARNING
	338	"%s(): PCI error report via EDAC not setup\n",
	339	__func__);
	340	}
	341
956b9ba1	342	edac_dbg(3, "MC: success\n");
5a2c675c TS	343	return 0;
5a2c675c TS	344
052dfb45	345	fail:
5a2c675c TS	346	edac_mc_free(mci);
	347	return -ENODEV;
	348	}
11116601	349
5a2c675c	350	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	351	static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	352	const struct pci_device_id *ent)
5a2c675c	353	{
53a2fe58 VB	354	int rc;
53a2fe58 VB	355
956b9ba1	356	edac_dbg(0, "MC:\n");
5a2c675c	357
ee6583f6	358	/* don't need to call pci_enable_device() */
53a2fe58 VB	359	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
	360
	361	if (mci_pdev == NULL)
	362	mci_pdev = pci_dev_get(pdev);
	363
	364	return rc;
5a2c675c TS	365	}
5a2c675c TS	366
9b3c6e85	367	static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
5a2c675c TS	368	{
	369	struct mem_ctl_info *mci;
	370
956b9ba1	371	edac_dbg(0, "\n");
5a2c675c	372
456a2f95 DJ	373	if (i82443bxgx_pci)
	374	edac_pci_release_generic_ctl(i82443bxgx_pci);
	375
11116601	376	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
5a2c675c TS	377	return;
	378
	379	edac_mc_free(mci);
	380	}
5a2c675c	381
ba935f40	382	static const struct pci_device_id i82443bxgx_pci_tbl[] = {
5a2c675c TS	383	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
	384	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
	385	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
	386	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
	387	{0,} /* 0 terminated list. */
	388	};
	389
	390	MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
	391
5a2c675c TS	392	static struct pci_driver i82443bxgx_edacmc_driver = {
	393	.name = EDAC_MOD_STR,
	394	.probe = i82443bxgx_edacmc_init_one,
9b3c6e85	395	.remove = i82443bxgx_edacmc_remove_one,
5a2c675c TS	396	.id_table = i82443bxgx_pci_tbl,
	397	};
	398
5a2c675c TS	399	static int __init i82443bxgx_edacmc_init(void)
5a2c675c TS	400	{
53a2fe58	401	int pci_rc;
c3c52bce HM	402	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	403	opstate_init();
	404
53a2fe58 VB	405	pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
	406	if (pci_rc < 0)
	407	goto fail0;
	408
	409	if (mci_pdev == NULL) {
	410	const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
	411	int i = 0;
	412	i82443bxgx_registered = 0;
	413
	414	while (mci_pdev == NULL && id->vendor != 0) {
	415	mci_pdev = pci_get_device(id->vendor,
	416	id->device, NULL);
	417	i++;
	418	id = &i82443bxgx_pci_tbl[i];
	419	}
	420	if (!mci_pdev) {
956b9ba1	421	edac_dbg(0, "i82443bxgx pci_get_device fail\n");
53a2fe58 VB	422	pci_rc = -ENODEV;
	423	goto fail1;
	424	}
	425
	426	pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
	427
	428	if (pci_rc < 0) {
956b9ba1	429	edac_dbg(0, "i82443bxgx init fail\n");
53a2fe58 VB	430	pci_rc = -ENODEV;
	431	goto fail1;
	432	}
	433	}
	434
	435	return 0;
	436
	437	fail1:
	438	pci_unregister_driver(&i82443bxgx_edacmc_driver);
	439
	440	fail0:
72601945	441	pci_dev_put(mci_pdev);
53a2fe58	442	return pci_rc;
5a2c675c TS	443	}
5a2c675c TS	444
5a2c675c TS	445	static void __exit i82443bxgx_edacmc_exit(void)
	446	{
	447	pci_unregister_driver(&i82443bxgx_edacmc_driver);
53a2fe58 VB	448
	449	if (!i82443bxgx_registered)
	450	i82443bxgx_edacmc_remove_one(mci_pdev);
	451
0a98babd	452	pci_dev_put(mci_pdev);
5a2c675c TS	453	}
5a2c675c TS	454
5a2c675c TS	455	module_init(i82443bxgx_edacmc_init);
	456	module_exit(i82443bxgx_edacmc_exit);
	457
5a2c675c TS	458	MODULE_LICENSE("GPL");
	459	MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
	460	MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
c3c52bce HM	461
	462	module_param(edac_op_state, int, 0444);
	463	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");