]>
Commit | Line | Data |
---|---|---|
94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
c5fd936e | 26 | #include <linux/delay.h> |
94580299 BS |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> | |
5addcf0a DA |
29 | #include <linux/pm_runtime.h> |
30 | #include <linux/vga_switcheroo.h> | |
fdb751ef | 31 | |
ae95621b MY |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
fdb751ef | 34 | |
ebb945a9 | 35 | #include <core/gpuobj.h> |
c33e05a1 | 36 | #include <core/option.h> |
7974dd1b BS |
37 | #include <core/pci.h> |
38 | #include <core/tegra.h> | |
94580299 | 39 | |
04b88677 | 40 | #include <nvif/driver.h> |
a7cf0180 | 41 | #include <nvif/fifo.h> |
37e1c45a | 42 | #include <nvif/user.h> |
04b88677 | 43 | |
923bc416 | 44 | #include <nvif/class.h> |
845f2725 | 45 | #include <nvif/cl0002.h> |
8ed1730c | 46 | #include <nvif/cla06f.h> |
538b269b BS |
47 | #include <nvif/if0004.h> |
48 | ||
4dc28134 | 49 | #include "nouveau_drv.h" |
ebb945a9 | 50 | #include "nouveau_dma.h" |
77145f1c BS |
51 | #include "nouveau_ttm.h" |
52 | #include "nouveau_gem.h" | |
77145f1c | 53 | #include "nouveau_vga.h" |
8d021d71 | 54 | #include "nouveau_led.h" |
b9ed919f | 55 | #include "nouveau_hwmon.h" |
77145f1c BS |
56 | #include "nouveau_acpi.h" |
57 | #include "nouveau_bios.h" | |
58 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
59 | #include "nouveau_abi16.h" |
60 | #include "nouveau_fbcon.h" | |
61 | #include "nouveau_fence.h" | |
33b903e8 | 62 | #include "nouveau_debugfs.h" |
27111a23 | 63 | #include "nouveau_usif.h" |
703fa264 | 64 | #include "nouveau_connector.h" |
055a65d5 | 65 | #include "nouveau_platform.h" |
ebb945a9 | 66 | |
94580299 BS |
67 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
68 | static char *nouveau_config; | |
69 | module_param_named(config, nouveau_config, charp, 0400); | |
70 | ||
71 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
72 | static char *nouveau_debug; | |
73 | module_param_named(debug, nouveau_debug, charp, 0400); | |
74 | ||
ebb945a9 BS |
75 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
76 | static int nouveau_noaccel = 0; | |
77 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
78 | ||
9430738d BS |
79 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
80 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
81 | int nouveau_modeset = -1; | |
77145f1c BS |
82 | module_param_named(modeset, nouveau_modeset, int, 0400); |
83 | ||
eb493fbc LP |
84 | MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); |
85 | static int nouveau_atomic = 0; | |
86 | module_param_named(atomic, nouveau_atomic, int, 0400); | |
87 | ||
5addcf0a | 88 | MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); |
321f5c5f | 89 | static int nouveau_runtime_pm = -1; |
5addcf0a DA |
90 | module_param_named(runpm, nouveau_runtime_pm, int, 0400); |
91 | ||
915b4d11 DH |
92 | static struct drm_driver driver_stub; |
93 | static struct drm_driver driver_pci; | |
94 | static struct drm_driver driver_platform; | |
77145f1c | 95 | |
94580299 | 96 | static u64 |
420b9469 | 97 | nouveau_pci_name(struct pci_dev *pdev) |
94580299 BS |
98 | { |
99 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
100 | name |= pdev->bus->number << 16; | |
101 | name |= PCI_SLOT(pdev->devfn) << 8; | |
102 | return name | PCI_FUNC(pdev->devfn); | |
103 | } | |
104 | ||
420b9469 AC |
105 | static u64 |
106 | nouveau_platform_name(struct platform_device *platformdev) | |
107 | { | |
108 | return platformdev->id; | |
109 | } | |
110 | ||
111 | static u64 | |
112 | nouveau_name(struct drm_device *dev) | |
113 | { | |
114 | if (dev->pdev) | |
115 | return nouveau_pci_name(dev->pdev); | |
116 | else | |
76adb460 | 117 | return nouveau_platform_name(to_platform_device(dev->dev)); |
420b9469 AC |
118 | } |
119 | ||
814a2324 | 120 | static inline bool |
11e451e7 | 121 | nouveau_cli_work_ready(struct dma_fence *fence) |
814a2324 | 122 | { |
11e451e7 BS |
123 | if (!dma_fence_is_signaled(fence)) |
124 | return false; | |
814a2324 BS |
125 | dma_fence_put(fence); |
126 | return true; | |
127 | } | |
128 | ||
129 | static void | |
11e451e7 | 130 | nouveau_cli_work(struct work_struct *w) |
814a2324 | 131 | { |
11e451e7 | 132 | struct nouveau_cli *cli = container_of(w, typeof(*cli), work); |
814a2324 BS |
133 | struct nouveau_cli_work *work, *wtmp; |
134 | mutex_lock(&cli->lock); | |
135 | list_for_each_entry_safe(work, wtmp, &cli->worker, head) { | |
11e451e7 | 136 | if (!work->fence || nouveau_cli_work_ready(work->fence)) { |
814a2324 BS |
137 | list_del(&work->head); |
138 | work->func(work); | |
139 | } | |
140 | } | |
141 | mutex_unlock(&cli->lock); | |
142 | } | |
143 | ||
144 | static void | |
145 | nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) | |
146 | { | |
147 | struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); | |
148 | schedule_work(&work->cli->work); | |
149 | } | |
150 | ||
151 | void | |
152 | nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, | |
153 | struct nouveau_cli_work *work) | |
154 | { | |
155 | work->fence = dma_fence_get(fence); | |
156 | work->cli = cli; | |
157 | mutex_lock(&cli->lock); | |
158 | list_add_tail(&work->head, &cli->worker); | |
814a2324 BS |
159 | if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) |
160 | nouveau_cli_work_fence(fence, &work->cb); | |
b26a2319 | 161 | mutex_unlock(&cli->lock); |
814a2324 BS |
162 | } |
163 | ||
20d8a88e BS |
164 | static void |
165 | nouveau_cli_fini(struct nouveau_cli *cli) | |
166 | { | |
11e451e7 BS |
167 | /* All our channels are dead now, which means all the fences they |
168 | * own are signalled, and all callback functions have been called. | |
169 | * | |
170 | * So, after flushing the workqueue, there should be nothing left. | |
171 | */ | |
172 | flush_work(&cli->work); | |
173 | WARN_ON(!list_empty(&cli->worker)); | |
174 | ||
20d8a88e | 175 | usif_client_fini(cli); |
24e8375b | 176 | nouveau_vmm_fini(&cli->vmm); |
01670a79 | 177 | nvif_mmu_fini(&cli->mmu); |
1167c6bc | 178 | nvif_device_fini(&cli->device); |
cb7e88e7 | 179 | mutex_lock(&cli->drm->master.lock); |
20d8a88e | 180 | nvif_client_fini(&cli->base); |
cb7e88e7 | 181 | mutex_unlock(&cli->drm->master.lock); |
20d8a88e BS |
182 | } |
183 | ||
94580299 | 184 | static int |
20d8a88e BS |
185 | nouveau_cli_init(struct nouveau_drm *drm, const char *sname, |
186 | struct nouveau_cli *cli) | |
94580299 | 187 | { |
7f507624 BS |
188 | static const struct nvif_mclass |
189 | mems[] = { | |
190 | { NVIF_CLASS_MEM_GF100, -1 }, | |
191 | { NVIF_CLASS_MEM_NV50 , -1 }, | |
192 | { NVIF_CLASS_MEM_NV04 , -1 }, | |
193 | {} | |
194 | }; | |
01670a79 BS |
195 | static const struct nvif_mclass |
196 | mmus[] = { | |
197 | { NVIF_CLASS_MMU_GF100, -1 }, | |
198 | { NVIF_CLASS_MMU_NV50 , -1 }, | |
199 | { NVIF_CLASS_MMU_NV04 , -1 }, | |
200 | {} | |
201 | }; | |
96da0bcd BS |
202 | static const struct nvif_mclass |
203 | vmms[] = { | |
204 | { NVIF_CLASS_VMM_GP100, -1 }, | |
205 | { NVIF_CLASS_VMM_GM200, -1 }, | |
206 | { NVIF_CLASS_VMM_GF100, -1 }, | |
207 | { NVIF_CLASS_VMM_NV50 , -1 }, | |
208 | { NVIF_CLASS_VMM_NV04 , -1 }, | |
209 | {} | |
210 | }; | |
20d8a88e | 211 | u64 device = nouveau_name(drm->dev); |
9ad97ede | 212 | int ret; |
9ad97ede | 213 | |
20d8a88e | 214 | snprintf(cli->name, sizeof(cli->name), "%s", sname); |
e75c091b | 215 | cli->drm = drm; |
20d8a88e BS |
216 | mutex_init(&cli->mutex); |
217 | usif_client_init(cli); | |
218 | ||
814a2324 BS |
219 | INIT_WORK(&cli->work, nouveau_cli_work); |
220 | INIT_LIST_HEAD(&cli->worker); | |
cb7e88e7 BS |
221 | mutex_init(&cli->lock); |
222 | ||
223 | if (cli == &drm->master) { | |
80e60973 BS |
224 | ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, |
225 | cli->name, device, &cli->base); | |
226 | } else { | |
cb7e88e7 BS |
227 | mutex_lock(&drm->master.lock); |
228 | ret = nvif_client_init(&drm->master.base, cli->name, device, | |
9ad97ede | 229 | &cli->base); |
cb7e88e7 | 230 | mutex_unlock(&drm->master.lock); |
dd5700ea | 231 | } |
20d8a88e | 232 | if (ret) { |
a43b16dd | 233 | NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); |
20d8a88e | 234 | goto done; |
dd5700ea | 235 | } |
94580299 | 236 | |
1167c6bc BS |
237 | ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, |
238 | &(struct nv_device_v0) { | |
239 | .device = ~0, | |
240 | }, sizeof(struct nv_device_v0), | |
241 | &cli->device); | |
242 | if (ret) { | |
a43b16dd | 243 | NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); |
1167c6bc BS |
244 | goto done; |
245 | } | |
246 | ||
01670a79 BS |
247 | ret = nvif_mclass(&cli->device.object, mmus); |
248 | if (ret < 0) { | |
a43b16dd | 249 | NV_PRINTK(err, cli, "No supported MMU class\n"); |
01670a79 BS |
250 | goto done; |
251 | } | |
252 | ||
253 | ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); | |
254 | if (ret) { | |
a43b16dd | 255 | NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); |
01670a79 BS |
256 | goto done; |
257 | } | |
258 | ||
96da0bcd BS |
259 | ret = nvif_mclass(&cli->mmu.object, vmms); |
260 | if (ret < 0) { | |
a43b16dd | 261 | NV_PRINTK(err, cli, "No supported VMM class\n"); |
96da0bcd BS |
262 | goto done; |
263 | } | |
264 | ||
265 | ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); | |
266 | if (ret) { | |
a43b16dd | 267 | NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); |
96da0bcd BS |
268 | goto done; |
269 | } | |
270 | ||
7f507624 BS |
271 | ret = nvif_mclass(&cli->mmu.object, mems); |
272 | if (ret < 0) { | |
a43b16dd | 273 | NV_PRINTK(err, cli, "No supported MEM class\n"); |
7f507624 BS |
274 | goto done; |
275 | } | |
276 | ||
277 | cli->mem = &mems[ret]; | |
7f507624 | 278 | return 0; |
20d8a88e BS |
279 | done: |
280 | if (ret) | |
281 | nouveau_cli_fini(cli); | |
282 | return ret; | |
94580299 BS |
283 | } |
284 | ||
ebb945a9 BS |
285 | static void |
286 | nouveau_accel_fini(struct nouveau_drm *drm) | |
287 | { | |
fbd58ebd | 288 | nouveau_channel_idle(drm->channel); |
0ad72863 | 289 | nvif_object_fini(&drm->ntfy); |
f027f491 | 290 | nvkm_gpuobj_del(&drm->notify); |
fbd58ebd | 291 | nvif_notify_fini(&drm->flip); |
0ad72863 | 292 | nvif_object_fini(&drm->nvsw); |
fbd58ebd BS |
293 | nouveau_channel_del(&drm->channel); |
294 | ||
295 | nouveau_channel_idle(drm->cechan); | |
0ad72863 | 296 | nvif_object_fini(&drm->ttm.copy); |
fbd58ebd BS |
297 | nouveau_channel_del(&drm->cechan); |
298 | ||
ebb945a9 BS |
299 | if (drm->fence) |
300 | nouveau_fence(drm)->dtor(drm); | |
301 | } | |
302 | ||
303 | static void | |
304 | nouveau_accel_init(struct nouveau_drm *drm) | |
305 | { | |
1167c6bc | 306 | struct nvif_device *device = &drm->client.device; |
41a63406 | 307 | struct nvif_sclass *sclass; |
49981046 | 308 | u32 arg0, arg1; |
41a63406 | 309 | int ret, i, n; |
ebb945a9 | 310 | |
967e7bde | 311 | if (nouveau_noaccel) |
ebb945a9 BS |
312 | return; |
313 | ||
eb47db4f BS |
314 | ret = nouveau_channels_init(drm); |
315 | if (ret) | |
316 | return; | |
317 | ||
37e1c45a BS |
318 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { |
319 | ret = nvif_user_init(device); | |
320 | if (ret) | |
321 | return; | |
322 | } | |
323 | ||
ebb945a9 | 324 | /* initialise synchronisation routines */ |
967e7bde BS |
325 | /*XXX: this is crap, but the fence/channel stuff is a little |
326 | * backwards in some places. this will be fixed. | |
327 | */ | |
41a63406 | 328 | ret = n = nvif_object_sclass_get(&device->object, &sclass); |
967e7bde BS |
329 | if (ret < 0) |
330 | return; | |
331 | ||
41a63406 BS |
332 | for (ret = -ENOSYS, i = 0; i < n; i++) { |
333 | switch (sclass[i].oclass) { | |
bbf8906b | 334 | case NV03_CHANNEL_DMA: |
967e7bde BS |
335 | ret = nv04_fence_create(drm); |
336 | break; | |
bbf8906b | 337 | case NV10_CHANNEL_DMA: |
967e7bde BS |
338 | ret = nv10_fence_create(drm); |
339 | break; | |
bbf8906b BS |
340 | case NV17_CHANNEL_DMA: |
341 | case NV40_CHANNEL_DMA: | |
967e7bde BS |
342 | ret = nv17_fence_create(drm); |
343 | break; | |
bbf8906b | 344 | case NV50_CHANNEL_GPFIFO: |
967e7bde BS |
345 | ret = nv50_fence_create(drm); |
346 | break; | |
bbf8906b | 347 | case G82_CHANNEL_GPFIFO: |
967e7bde BS |
348 | ret = nv84_fence_create(drm); |
349 | break; | |
bbf8906b BS |
350 | case FERMI_CHANNEL_GPFIFO: |
351 | case KEPLER_CHANNEL_GPFIFO_A: | |
63f8c9b7 | 352 | case KEPLER_CHANNEL_GPFIFO_B: |
a1020afe | 353 | case MAXWELL_CHANNEL_GPFIFO_A: |
e8ff9794 | 354 | case PASCAL_CHANNEL_GPFIFO_A: |
37e1c45a | 355 | case VOLTA_CHANNEL_GPFIFO_A: |
967e7bde BS |
356 | ret = nvc0_fence_create(drm); |
357 | break; | |
358 | default: | |
359 | break; | |
360 | } | |
361 | } | |
362 | ||
41a63406 | 363 | nvif_object_sclass_put(&sclass); |
ebb945a9 BS |
364 | if (ret) { |
365 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
366 | nouveau_accel_fini(drm); | |
367 | return; | |
368 | } | |
369 | ||
967e7bde | 370 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { |
1167c6bc | 371 | ret = nouveau_channel_new(drm, &drm->client.device, |
a7cf0180 BS |
372 | nvif_fifo_runlist_ce(device), 0, |
373 | &drm->cechan); | |
49981046 BS |
374 | if (ret) |
375 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
376 | ||
a7cf0180 | 377 | arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR); |
49469800 | 378 | arg1 = 1; |
00fc6f6f | 379 | } else |
967e7bde BS |
380 | if (device->info.chipset >= 0xa3 && |
381 | device->info.chipset != 0xaa && | |
382 | device->info.chipset != 0xac) { | |
1167c6bc | 383 | ret = nouveau_channel_new(drm, &drm->client.device, |
0ad72863 | 384 | NvDmaFB, NvDmaTT, &drm->cechan); |
00fc6f6f BS |
385 | if (ret) |
386 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
387 | ||
388 | arg0 = NvDmaFB; | |
389 | arg1 = NvDmaTT; | |
49981046 BS |
390 | } else { |
391 | arg0 = NvDmaFB; | |
392 | arg1 = NvDmaTT; | |
393 | } | |
394 | ||
1167c6bc BS |
395 | ret = nouveau_channel_new(drm, &drm->client.device, |
396 | arg0, arg1, &drm->channel); | |
ebb945a9 BS |
397 | if (ret) { |
398 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
399 | nouveau_accel_fini(drm); | |
400 | return; | |
401 | } | |
402 | ||
512fa0b8 BS |
403 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { |
404 | ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, | |
405 | nouveau_abi16_swclass(drm), NULL, 0, | |
406 | &drm->nvsw); | |
69a6146d | 407 | if (ret == 0) { |
512fa0b8 BS |
408 | ret = RING_SPACE(drm->channel, 2); |
409 | if (ret == 0) { | |
69a6146d | 410 | BEGIN_NV04(drm->channel, NvSubSw, 0, 1); |
512fa0b8 BS |
411 | OUT_RING (drm->channel, drm->nvsw.handle); |
412 | } | |
413 | ||
414 | ret = nvif_notify_init(&drm->nvsw, | |
415 | nouveau_flip_complete, | |
416 | false, NV04_NVSW_NTFY_UEVENT, | |
417 | NULL, 0, 0, &drm->flip); | |
418 | if (ret == 0) | |
419 | ret = nvif_notify_get(&drm->flip); | |
420 | if (ret) { | |
421 | nouveau_accel_fini(drm); | |
422 | return; | |
69a6146d BS |
423 | } |
424 | } | |
898a2b32 | 425 | |
898a2b32 | 426 | if (ret) { |
512fa0b8 | 427 | NV_ERROR(drm, "failed to allocate sw class, %d\n", ret); |
898a2b32 BS |
428 | nouveau_accel_fini(drm); |
429 | return; | |
430 | } | |
69a6146d BS |
431 | } |
432 | ||
967e7bde | 433 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
1167c6bc BS |
434 | ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0, |
435 | false, NULL, &drm->notify); | |
ebb945a9 BS |
436 | if (ret) { |
437 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
438 | nouveau_accel_fini(drm); | |
439 | return; | |
440 | } | |
441 | ||
a01ca78c | 442 | ret = nvif_object_init(&drm->channel->user, NvNotify0, |
4acfd707 BS |
443 | NV_DMA_IN_MEMORY, |
444 | &(struct nv_dma_v0) { | |
445 | .target = NV_DMA_V0_TARGET_VRAM, | |
446 | .access = NV_DMA_V0_ACCESS_RDWR, | |
ebb945a9 BS |
447 | .start = drm->notify->addr, |
448 | .limit = drm->notify->addr + 31 | |
4acfd707 | 449 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 450 | &drm->ntfy); |
ebb945a9 BS |
451 | if (ret) { |
452 | nouveau_accel_fini(drm); | |
453 | return; | |
454 | } | |
455 | } | |
456 | ||
457 | ||
49981046 | 458 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
459 | } |
460 | ||
56550d94 GKH |
461 | static int nouveau_drm_probe(struct pci_dev *pdev, |
462 | const struct pci_device_id *pent) | |
94580299 | 463 | { |
be83cd4e | 464 | struct nvkm_device *device; |
ebb945a9 BS |
465 | struct apertures_struct *aper; |
466 | bool boot = false; | |
94580299 BS |
467 | int ret; |
468 | ||
b00e5334 | 469 | if (vga_switcheroo_client_probe_defer(pdev)) |
98b3a340 LW |
470 | return -EPROBE_DEFER; |
471 | ||
0e67bed2 BS |
472 | /* We need to check that the chipset is supported before booting |
473 | * fbdev off the hardware, as there's no way to put it back. | |
474 | */ | |
475 | ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device); | |
476 | if (ret) | |
477 | return ret; | |
478 | ||
479 | nvkm_device_del(&device); | |
480 | ||
481 | /* Remove conflicting drivers (vesafb, efifb etc). */ | |
ebb945a9 BS |
482 | aper = alloc_apertures(3); |
483 | if (!aper) | |
484 | return -ENOMEM; | |
485 | ||
486 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
487 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
488 | aper->count = 1; | |
489 | ||
490 | if (pci_resource_len(pdev, 2)) { | |
491 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
492 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
493 | aper->count++; | |
494 | } | |
495 | ||
496 | if (pci_resource_len(pdev, 3)) { | |
497 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
498 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
499 | aper->count++; | |
500 | } | |
501 | ||
502 | #ifdef CONFIG_X86 | |
503 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
504 | #endif | |
771fa0e4 | 505 | if (nouveau_modeset != 2) |
44adece5 | 506 | drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot); |
83ef7777 | 507 | kfree(aper); |
ebb945a9 | 508 | |
7974dd1b BS |
509 | ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, |
510 | true, true, ~0ULL, &device); | |
94580299 BS |
511 | if (ret) |
512 | return ret; | |
513 | ||
514 | pci_set_master(pdev); | |
515 | ||
eb493fbc LP |
516 | if (nouveau_atomic) |
517 | driver_pci.driver_features |= DRIVER_ATOMIC; | |
518 | ||
915b4d11 | 519 | ret = drm_get_pci_dev(pdev, pent, &driver_pci); |
94580299 | 520 | if (ret) { |
e781dc8f | 521 | nvkm_device_del(&device); |
94580299 BS |
522 | return ret; |
523 | } | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
5b8a43ae | 528 | static int |
94580299 BS |
529 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
530 | { | |
94580299 BS |
531 | struct nouveau_drm *drm; |
532 | int ret; | |
533 | ||
20d8a88e BS |
534 | if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) |
535 | return -ENOMEM; | |
536 | dev->dev_private = drm; | |
537 | drm->dev = dev; | |
538 | ||
cb7e88e7 BS |
539 | ret = nouveau_cli_init(drm, "DRM-master", &drm->master); |
540 | if (ret) | |
541 | return ret; | |
542 | ||
20d8a88e | 543 | ret = nouveau_cli_init(drm, "DRM", &drm->client); |
94580299 BS |
544 | if (ret) |
545 | return ret; | |
546 | ||
1167c6bc BS |
547 | dev->irq_enabled = true; |
548 | ||
989aa5b7 | 549 | nvxx_client(&drm->client.base)->debug = |
be83cd4e | 550 | nvkm_dbgopt(nouveau_debug, "DRM"); |
77145f1c | 551 | |
94580299 | 552 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 553 | spin_lock_init(&drm->tile.lock); |
94580299 | 554 | |
77145f1c BS |
555 | /* workaround an odd issue on nvc1 by disabling the device's |
556 | * nosnoop capability. hopefully won't cause issues until a | |
557 | * better fix is found - assuming there is one... | |
558 | */ | |
1167c6bc BS |
559 | if (drm->client.device.info.chipset == 0xc1) |
560 | nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 561 | |
77145f1c | 562 | nouveau_vga_init(drm); |
cb75d97e | 563 | |
ebb945a9 | 564 | ret = nouveau_ttm_init(drm); |
94580299 | 565 | if (ret) |
77145f1c BS |
566 | goto fail_ttm; |
567 | ||
568 | ret = nouveau_bios_init(dev); | |
569 | if (ret) | |
570 | goto fail_bios; | |
571 | ||
77145f1c | 572 | ret = nouveau_display_create(dev); |
ebb945a9 | 573 | if (ret) |
77145f1c BS |
574 | goto fail_dispctor; |
575 | ||
576 | if (dev->mode_config.num_crtc) { | |
577 | ret = nouveau_display_init(dev); | |
578 | if (ret) | |
579 | goto fail_dispinit; | |
580 | } | |
581 | ||
b126a200 | 582 | nouveau_debugfs_init(drm); |
b9ed919f | 583 | nouveau_hwmon_init(dev); |
ebb945a9 BS |
584 | nouveau_accel_init(drm); |
585 | nouveau_fbcon_init(dev); | |
8d021d71 | 586 | nouveau_led_init(dev); |
5addcf0a | 587 | |
8fa4338a | 588 | if (nouveau_pmops_runtime()) { |
5addcf0a DA |
589 | pm_runtime_use_autosuspend(dev->dev); |
590 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
591 | pm_runtime_set_active(dev->dev); | |
592 | pm_runtime_allow(dev->dev); | |
593 | pm_runtime_mark_last_busy(dev->dev); | |
594 | pm_runtime_put(dev->dev); | |
595 | } | |
7326ead9 | 596 | |
94580299 BS |
597 | return 0; |
598 | ||
77145f1c BS |
599 | fail_dispinit: |
600 | nouveau_display_destroy(dev); | |
601 | fail_dispctor: | |
77145f1c BS |
602 | nouveau_bios_takedown(dev); |
603 | fail_bios: | |
ebb945a9 | 604 | nouveau_ttm_fini(drm); |
77145f1c | 605 | fail_ttm: |
77145f1c | 606 | nouveau_vga_fini(drm); |
20d8a88e | 607 | nouveau_cli_fini(&drm->client); |
cb7e88e7 | 608 | nouveau_cli_fini(&drm->master); |
20d8a88e | 609 | kfree(drm); |
94580299 BS |
610 | return ret; |
611 | } | |
612 | ||
11b3c20b | 613 | static void |
94580299 BS |
614 | nouveau_drm_unload(struct drm_device *dev) |
615 | { | |
77145f1c | 616 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 617 | |
8fa4338a | 618 | if (nouveau_pmops_runtime()) { |
c1b16b45 | 619 | pm_runtime_get_sync(dev->dev); |
55c868a3 | 620 | pm_runtime_forbid(dev->dev); |
c1b16b45 LW |
621 | } |
622 | ||
8d021d71 | 623 | nouveau_led_fini(dev); |
ebb945a9 BS |
624 | nouveau_fbcon_fini(dev); |
625 | nouveau_accel_fini(drm); | |
b9ed919f | 626 | nouveau_hwmon_fini(dev); |
b126a200 | 627 | nouveau_debugfs_fini(drm); |
77145f1c | 628 | |
9430738d | 629 | if (dev->mode_config.num_crtc) |
2f7ca781 | 630 | nouveau_display_fini(dev, false, false); |
77145f1c BS |
631 | nouveau_display_destroy(dev); |
632 | ||
77145f1c | 633 | nouveau_bios_takedown(dev); |
94580299 | 634 | |
ebb945a9 | 635 | nouveau_ttm_fini(drm); |
77145f1c | 636 | nouveau_vga_fini(drm); |
cb75d97e | 637 | |
20d8a88e | 638 | nouveau_cli_fini(&drm->client); |
cb7e88e7 | 639 | nouveau_cli_fini(&drm->master); |
20d8a88e | 640 | kfree(drm); |
94580299 BS |
641 | } |
642 | ||
8ba9ff11 AC |
643 | void |
644 | nouveau_drm_device_remove(struct drm_device *dev) | |
94580299 | 645 | { |
77145f1c | 646 | struct nouveau_drm *drm = nouveau_drm(dev); |
be83cd4e | 647 | struct nvkm_client *client; |
76ecea5b | 648 | struct nvkm_device *device; |
77145f1c | 649 | |
7d3428cd | 650 | dev->irq_enabled = false; |
989aa5b7 | 651 | client = nvxx_client(&drm->client.base); |
4e7e62d6 | 652 | device = nvkm_device_find(client->device); |
77145f1c BS |
653 | drm_put_dev(dev); |
654 | ||
e781dc8f | 655 | nvkm_device_del(&device); |
94580299 | 656 | } |
8ba9ff11 AC |
657 | |
658 | static void | |
659 | nouveau_drm_remove(struct pci_dev *pdev) | |
660 | { | |
661 | struct drm_device *dev = pci_get_drvdata(pdev); | |
662 | ||
663 | nouveau_drm_device_remove(dev); | |
664 | } | |
94580299 | 665 | |
cd897837 | 666 | static int |
05c63c2f | 667 | nouveau_do_suspend(struct drm_device *dev, bool runtime) |
94580299 | 668 | { |
77145f1c | 669 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
670 | int ret; |
671 | ||
8d021d71 MP |
672 | nouveau_led_suspend(dev); |
673 | ||
6fbb702e | 674 | if (dev->mode_config.num_crtc) { |
2d38a535 | 675 | NV_DEBUG(drm, "suspending console...\n"); |
6fbb702e | 676 | nouveau_fbcon_set_suspend(dev, 1); |
2d38a535 | 677 | NV_DEBUG(drm, "suspending display...\n"); |
6fbb702e | 678 | ret = nouveau_display_suspend(dev, runtime); |
9430738d BS |
679 | if (ret) |
680 | return ret; | |
681 | } | |
94580299 | 682 | |
2d38a535 | 683 | NV_DEBUG(drm, "evicting buffers...\n"); |
ebb945a9 BS |
684 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); |
685 | ||
2d38a535 | 686 | NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); |
81dff21b BS |
687 | if (drm->cechan) { |
688 | ret = nouveau_channel_idle(drm->cechan); | |
689 | if (ret) | |
f3980dc5 | 690 | goto fail_display; |
81dff21b BS |
691 | } |
692 | ||
693 | if (drm->channel) { | |
694 | ret = nouveau_channel_idle(drm->channel); | |
695 | if (ret) | |
f3980dc5 | 696 | goto fail_display; |
81dff21b BS |
697 | } |
698 | ||
2d38a535 | 699 | NV_DEBUG(drm, "suspending fence...\n"); |
ebb945a9 | 700 | if (drm->fence && nouveau_fence(drm)->suspend) { |
f3980dc5 IM |
701 | if (!nouveau_fence(drm)->suspend(drm)) { |
702 | ret = -ENOMEM; | |
703 | goto fail_display; | |
704 | } | |
ebb945a9 BS |
705 | } |
706 | ||
2d38a535 | 707 | NV_DEBUG(drm, "suspending object tree...\n"); |
cb7e88e7 | 708 | ret = nvif_client_suspend(&drm->master.base); |
94580299 BS |
709 | if (ret) |
710 | goto fail_client; | |
711 | ||
94580299 BS |
712 | return 0; |
713 | ||
714 | fail_client: | |
f3980dc5 IM |
715 | if (drm->fence && nouveau_fence(drm)->resume) |
716 | nouveau_fence(drm)->resume(drm); | |
717 | ||
718 | fail_display: | |
9430738d | 719 | if (dev->mode_config.num_crtc) { |
2d38a535 | 720 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 721 | nouveau_display_resume(dev, runtime); |
9430738d | 722 | } |
94580299 BS |
723 | return ret; |
724 | } | |
725 | ||
cd897837 | 726 | static int |
6fbb702e | 727 | nouveau_do_resume(struct drm_device *dev, bool runtime) |
2d8b9ccb DA |
728 | { |
729 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2d8b9ccb | 730 | |
2d38a535 | 731 | NV_DEBUG(drm, "resuming object tree...\n"); |
cb7e88e7 | 732 | nvif_client_resume(&drm->master.base); |
94580299 | 733 | |
2d38a535 | 734 | NV_DEBUG(drm, "resuming fence...\n"); |
81dff21b BS |
735 | if (drm->fence && nouveau_fence(drm)->resume) |
736 | nouveau_fence(drm)->resume(drm); | |
737 | ||
77145f1c | 738 | nouveau_run_vbios_init(dev); |
77145f1c | 739 | |
9430738d | 740 | if (dev->mode_config.num_crtc) { |
2d38a535 | 741 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 742 | nouveau_display_resume(dev, runtime); |
2d38a535 | 743 | NV_DEBUG(drm, "resuming console...\n"); |
6fbb702e | 744 | nouveau_fbcon_set_suspend(dev, 0); |
9430738d | 745 | } |
5addcf0a | 746 | |
8d021d71 MP |
747 | nouveau_led_resume(dev); |
748 | ||
77145f1c | 749 | return 0; |
94580299 BS |
750 | } |
751 | ||
7bb6d442 BS |
752 | int |
753 | nouveau_pmops_suspend(struct device *dev) | |
754 | { | |
755 | struct pci_dev *pdev = to_pci_dev(dev); | |
756 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
757 | int ret; | |
758 | ||
759 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || | |
760 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
761 | return 0; | |
762 | ||
763 | ret = nouveau_do_suspend(drm_dev, false); | |
764 | if (ret) | |
765 | return ret; | |
766 | ||
767 | pci_save_state(pdev); | |
768 | pci_disable_device(pdev); | |
7bb6d442 | 769 | pci_set_power_state(pdev, PCI_D3hot); |
c5fd936e | 770 | udelay(200); |
7bb6d442 BS |
771 | return 0; |
772 | } | |
773 | ||
774 | int | |
775 | nouveau_pmops_resume(struct device *dev) | |
2d8b9ccb DA |
776 | { |
777 | struct pci_dev *pdev = to_pci_dev(dev); | |
778 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
779 | int ret; | |
780 | ||
5addcf0a DA |
781 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
782 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
2d8b9ccb DA |
783 | return 0; |
784 | ||
785 | pci_set_power_state(pdev, PCI_D0); | |
786 | pci_restore_state(pdev); | |
787 | ret = pci_enable_device(pdev); | |
788 | if (ret) | |
789 | return ret; | |
790 | pci_set_master(pdev); | |
791 | ||
0b2fe659 HG |
792 | ret = nouveau_do_resume(drm_dev, false); |
793 | ||
794 | /* Monitors may have been connected / disconnected during suspend */ | |
795 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
796 | ||
797 | return ret; | |
2d8b9ccb DA |
798 | } |
799 | ||
7bb6d442 BS |
800 | static int |
801 | nouveau_pmops_freeze(struct device *dev) | |
2d8b9ccb DA |
802 | { |
803 | struct pci_dev *pdev = to_pci_dev(dev); | |
804 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 805 | return nouveau_do_suspend(drm_dev, false); |
2d8b9ccb DA |
806 | } |
807 | ||
7bb6d442 BS |
808 | static int |
809 | nouveau_pmops_thaw(struct device *dev) | |
2d8b9ccb DA |
810 | { |
811 | struct pci_dev *pdev = to_pci_dev(dev); | |
812 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 813 | return nouveau_do_resume(drm_dev, false); |
2d8b9ccb DA |
814 | } |
815 | ||
321f5c5f | 816 | bool |
5499473c | 817 | nouveau_pmops_runtime(void) |
321f5c5f BS |
818 | { |
819 | if (nouveau_runtime_pm == -1) | |
820 | return nouveau_is_optimus() || nouveau_is_v1_dsm(); | |
821 | return nouveau_runtime_pm == 1; | |
822 | } | |
823 | ||
7bb6d442 BS |
824 | static int |
825 | nouveau_pmops_runtime_suspend(struct device *dev) | |
826 | { | |
827 | struct pci_dev *pdev = to_pci_dev(dev); | |
828 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
829 | int ret; | |
830 | ||
321f5c5f | 831 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
832 | pm_runtime_forbid(dev); |
833 | return -EBUSY; | |
834 | } | |
835 | ||
7bb6d442 BS |
836 | nouveau_switcheroo_optimus_dsm(); |
837 | ret = nouveau_do_suspend(drm_dev, true); | |
838 | pci_save_state(pdev); | |
839 | pci_disable_device(pdev); | |
8c863944 | 840 | pci_ignore_hotplug(pdev); |
7bb6d442 BS |
841 | pci_set_power_state(pdev, PCI_D3cold); |
842 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
843 | return ret; | |
844 | } | |
845 | ||
846 | static int | |
847 | nouveau_pmops_runtime_resume(struct device *dev) | |
848 | { | |
849 | struct pci_dev *pdev = to_pci_dev(dev); | |
850 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1167c6bc | 851 | struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; |
7bb6d442 BS |
852 | int ret; |
853 | ||
321f5c5f BS |
854 | if (!nouveau_pmops_runtime()) { |
855 | pm_runtime_forbid(dev); | |
856 | return -EBUSY; | |
857 | } | |
7bb6d442 BS |
858 | |
859 | pci_set_power_state(pdev, PCI_D0); | |
860 | pci_restore_state(pdev); | |
861 | ret = pci_enable_device(pdev); | |
862 | if (ret) | |
863 | return ret; | |
864 | pci_set_master(pdev); | |
865 | ||
866 | ret = nouveau_do_resume(drm_dev, true); | |
cae9ff03 | 867 | |
7bb6d442 | 868 | /* do magic */ |
a01ca78c | 869 | nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); |
7bb6d442 | 870 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
0b2fe659 HG |
871 | |
872 | /* Monitors may have been connected / disconnected during suspend */ | |
873 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
874 | ||
7bb6d442 BS |
875 | return ret; |
876 | } | |
877 | ||
878 | static int | |
879 | nouveau_pmops_runtime_idle(struct device *dev) | |
880 | { | |
321f5c5f | 881 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
882 | pm_runtime_forbid(dev); |
883 | return -EBUSY; | |
884 | } | |
885 | ||
7bb6d442 BS |
886 | pm_runtime_mark_last_busy(dev); |
887 | pm_runtime_autosuspend(dev); | |
888 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
889 | return 1; | |
890 | } | |
2d8b9ccb | 891 | |
5b8a43ae | 892 | static int |
ebb945a9 BS |
893 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
894 | { | |
ebb945a9 BS |
895 | struct nouveau_drm *drm = nouveau_drm(dev); |
896 | struct nouveau_cli *cli; | |
a2896ced | 897 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
898 | int ret; |
899 | ||
5addcf0a DA |
900 | /* need to bring up power immediately if opening device */ |
901 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 902 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
903 | return ret; |
904 | ||
a2896ced MS |
905 | get_task_comm(tmpname, current); |
906 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 | 907 | |
922a8c82 LP |
908 | if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { |
909 | ret = -ENOMEM; | |
910 | goto done; | |
911 | } | |
420b9469 | 912 | |
20d8a88e | 913 | ret = nouveau_cli_init(drm, name, cli); |
ebb945a9 | 914 | if (ret) |
20d8a88e | 915 | goto done; |
ebb945a9 | 916 | |
0ad72863 BS |
917 | cli->base.super = false; |
918 | ||
ebb945a9 BS |
919 | fpriv->driver_priv = cli; |
920 | ||
921 | mutex_lock(&drm->client.mutex); | |
922 | list_add(&cli->head, &drm->clients); | |
923 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 924 | |
20d8a88e BS |
925 | done: |
926 | if (ret && cli) { | |
927 | nouveau_cli_fini(cli); | |
928 | kfree(cli); | |
929 | } | |
930 | ||
5addcf0a DA |
931 | pm_runtime_mark_last_busy(dev->dev); |
932 | pm_runtime_put_autosuspend(dev->dev); | |
5addcf0a | 933 | return ret; |
ebb945a9 BS |
934 | } |
935 | ||
5b8a43ae | 936 | static void |
f0e73ff3 | 937 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
ebb945a9 BS |
938 | { |
939 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
940 | struct nouveau_drm *drm = nouveau_drm(dev); | |
941 | ||
5addcf0a DA |
942 | pm_runtime_get_sync(dev->dev); |
943 | ||
ac8c7930 | 944 | mutex_lock(&cli->mutex); |
ebb945a9 BS |
945 | if (cli->abi16) |
946 | nouveau_abi16_fini(cli->abi16); | |
ac8c7930 | 947 | mutex_unlock(&cli->mutex); |
ebb945a9 BS |
948 | |
949 | mutex_lock(&drm->client.mutex); | |
950 | list_del(&cli->head); | |
951 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 952 | |
20d8a88e BS |
953 | nouveau_cli_fini(cli); |
954 | kfree(cli); | |
5addcf0a DA |
955 | pm_runtime_mark_last_busy(dev->dev); |
956 | pm_runtime_put_autosuspend(dev->dev); | |
ebb945a9 BS |
957 | } |
958 | ||
baa70943 | 959 | static const struct drm_ioctl_desc |
77145f1c | 960 | nouveau_ioctls[] = { |
f8c47144 DV |
961 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
962 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
963 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
964 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
965 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
966 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
967 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
968 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
969 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW), | |
970 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
971 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
972 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
77145f1c BS |
973 | }; |
974 | ||
27111a23 BS |
975 | long |
976 | nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
5addcf0a | 977 | { |
27111a23 BS |
978 | struct drm_file *filp = file->private_data; |
979 | struct drm_device *dev = filp->minor->dev; | |
5addcf0a | 980 | long ret; |
5addcf0a DA |
981 | |
982 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 983 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
984 | return ret; |
985 | ||
27111a23 BS |
986 | switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { |
987 | case DRM_NOUVEAU_NVIF: | |
988 | ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); | |
989 | break; | |
990 | default: | |
991 | ret = drm_ioctl(file, cmd, arg); | |
992 | break; | |
993 | } | |
5addcf0a DA |
994 | |
995 | pm_runtime_mark_last_busy(dev->dev); | |
996 | pm_runtime_put_autosuspend(dev->dev); | |
997 | return ret; | |
998 | } | |
27111a23 | 999 | |
77145f1c BS |
1000 | static const struct file_operations |
1001 | nouveau_driver_fops = { | |
1002 | .owner = THIS_MODULE, | |
1003 | .open = drm_open, | |
1004 | .release = drm_release, | |
5addcf0a | 1005 | .unlocked_ioctl = nouveau_drm_ioctl, |
77145f1c BS |
1006 | .mmap = nouveau_ttm_mmap, |
1007 | .poll = drm_poll, | |
77145f1c BS |
1008 | .read = drm_read, |
1009 | #if defined(CONFIG_COMPAT) | |
1010 | .compat_ioctl = nouveau_compat_ioctl, | |
1011 | #endif | |
1012 | .llseek = noop_llseek, | |
1013 | }; | |
1014 | ||
1015 | static struct drm_driver | |
915b4d11 | 1016 | driver_stub = { |
77145f1c | 1017 | .driver_features = |
d54e1b84 DA |
1018 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
1019 | #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT) | |
1020 | | DRIVER_KMS_LEGACY_CONTEXT | |
1021 | #endif | |
1022 | , | |
77145f1c BS |
1023 | |
1024 | .load = nouveau_drm_load, | |
1025 | .unload = nouveau_drm_unload, | |
1026 | .open = nouveau_drm_open, | |
77145f1c BS |
1027 | .postclose = nouveau_drm_postclose, |
1028 | .lastclose = nouveau_vga_lastclose, | |
1029 | ||
33b903e8 | 1030 | #if defined(CONFIG_DEBUG_FS) |
56c101af | 1031 | .debugfs_init = nouveau_drm_debugfs_init, |
33b903e8 MS |
1032 | #endif |
1033 | ||
51cb4b39 BS |
1034 | .enable_vblank = nouveau_display_vblank_enable, |
1035 | .disable_vblank = nouveau_display_vblank_disable, | |
d83ef853 | 1036 | .get_scanout_position = nouveau_display_scanoutpos, |
1bf6ad62 | 1037 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
77145f1c BS |
1038 | |
1039 | .ioctls = nouveau_ioctls, | |
baa70943 | 1040 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
1041 | .fops = &nouveau_driver_fops, |
1042 | ||
1043 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1044 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
1045 | .gem_prime_export = drm_gem_prime_export, |
1046 | .gem_prime_import = drm_gem_prime_import, | |
1047 | .gem_prime_pin = nouveau_gem_prime_pin, | |
3aac4502 | 1048 | .gem_prime_res_obj = nouveau_gem_prime_res_obj, |
1af7c7dd | 1049 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
1050 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
1051 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
1052 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
1053 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c | 1054 | |
a51e6ac4 | 1055 | .gem_free_object_unlocked = nouveau_gem_object_del, |
77145f1c BS |
1056 | .gem_open_object = nouveau_gem_object_open, |
1057 | .gem_close_object = nouveau_gem_object_close, | |
1058 | ||
1059 | .dumb_create = nouveau_display_dumb_create, | |
1060 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
77145f1c BS |
1061 | |
1062 | .name = DRIVER_NAME, | |
1063 | .desc = DRIVER_DESC, | |
1064 | #ifdef GIT_REVISION | |
1065 | .date = GIT_REVISION, | |
1066 | #else | |
1067 | .date = DRIVER_DATE, | |
1068 | #endif | |
1069 | .major = DRIVER_MAJOR, | |
1070 | .minor = DRIVER_MINOR, | |
1071 | .patchlevel = DRIVER_PATCHLEVEL, | |
1072 | }; | |
1073 | ||
94580299 BS |
1074 | static struct pci_device_id |
1075 | nouveau_drm_pci_table[] = { | |
1076 | { | |
1077 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
1078 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1079 | .class_mask = 0xff << 16, | |
1080 | }, | |
1081 | { | |
1082 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
1083 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1084 | .class_mask = 0xff << 16, | |
1085 | }, | |
1086 | {} | |
1087 | }; | |
1088 | ||
703fa264 PM |
1089 | static void nouveau_display_options(void) |
1090 | { | |
1091 | DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); | |
1092 | ||
1093 | DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); | |
1094 | DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); | |
1095 | DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); | |
1096 | DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); | |
1097 | DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); | |
1098 | DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); | |
1099 | DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); | |
1100 | DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); | |
1101 | DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); | |
1102 | DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); | |
f3a8b664 | 1103 | DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); |
703fa264 PM |
1104 | } |
1105 | ||
2d8b9ccb DA |
1106 | static const struct dev_pm_ops nouveau_pm_ops = { |
1107 | .suspend = nouveau_pmops_suspend, | |
1108 | .resume = nouveau_pmops_resume, | |
1109 | .freeze = nouveau_pmops_freeze, | |
1110 | .thaw = nouveau_pmops_thaw, | |
1111 | .poweroff = nouveau_pmops_freeze, | |
1112 | .restore = nouveau_pmops_resume, | |
5addcf0a DA |
1113 | .runtime_suspend = nouveau_pmops_runtime_suspend, |
1114 | .runtime_resume = nouveau_pmops_runtime_resume, | |
1115 | .runtime_idle = nouveau_pmops_runtime_idle, | |
2d8b9ccb DA |
1116 | }; |
1117 | ||
94580299 BS |
1118 | static struct pci_driver |
1119 | nouveau_drm_pci_driver = { | |
1120 | .name = "nouveau", | |
1121 | .id_table = nouveau_drm_pci_table, | |
1122 | .probe = nouveau_drm_probe, | |
1123 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 1124 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
1125 | }; |
1126 | ||
8ba9ff11 | 1127 | struct drm_device * |
e396ecd1 AC |
1128 | nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, |
1129 | struct platform_device *pdev, | |
47b2505e | 1130 | struct nvkm_device **pdevice) |
420b9469 | 1131 | { |
8ba9ff11 AC |
1132 | struct drm_device *drm; |
1133 | int err; | |
420b9469 | 1134 | |
e396ecd1 | 1135 | err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, |
7974dd1b | 1136 | true, true, ~0ULL, pdevice); |
8ba9ff11 | 1137 | if (err) |
e781dc8f | 1138 | goto err_free; |
8ba9ff11 | 1139 | |
915b4d11 | 1140 | drm = drm_dev_alloc(&driver_platform, &pdev->dev); |
0f288605 TG |
1141 | if (IS_ERR(drm)) { |
1142 | err = PTR_ERR(drm); | |
8ba9ff11 | 1143 | goto err_free; |
420b9469 AC |
1144 | } |
1145 | ||
8ba9ff11 AC |
1146 | platform_set_drvdata(pdev, drm); |
1147 | ||
1148 | return drm; | |
1149 | ||
1150 | err_free: | |
e781dc8f | 1151 | nvkm_device_del(pdevice); |
8ba9ff11 AC |
1152 | |
1153 | return ERR_PTR(err); | |
420b9469 AC |
1154 | } |
1155 | ||
94580299 BS |
1156 | static int __init |
1157 | nouveau_drm_init(void) | |
1158 | { | |
915b4d11 | 1159 | driver_pci = driver_stub; |
915b4d11 | 1160 | driver_platform = driver_stub; |
915b4d11 | 1161 | |
703fa264 PM |
1162 | nouveau_display_options(); |
1163 | ||
77145f1c | 1164 | if (nouveau_modeset == -1) { |
77145f1c BS |
1165 | if (vgacon_text_force()) |
1166 | nouveau_modeset = 0; | |
77145f1c BS |
1167 | } |
1168 | ||
1169 | if (!nouveau_modeset) | |
1170 | return 0; | |
1171 | ||
055a65d5 AC |
1172 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER |
1173 | platform_driver_register(&nouveau_platform_driver); | |
1174 | #endif | |
1175 | ||
77145f1c | 1176 | nouveau_register_dsm_handler(); |
db1a0ae2 | 1177 | nouveau_backlight_ctor(); |
10631d72 DV |
1178 | |
1179 | #ifdef CONFIG_PCI | |
1180 | return pci_register_driver(&nouveau_drm_pci_driver); | |
1181 | #else | |
1182 | return 0; | |
1183 | #endif | |
94580299 BS |
1184 | } |
1185 | ||
1186 | static void __exit | |
1187 | nouveau_drm_exit(void) | |
1188 | { | |
77145f1c BS |
1189 | if (!nouveau_modeset) |
1190 | return; | |
1191 | ||
10631d72 DV |
1192 | #ifdef CONFIG_PCI |
1193 | pci_unregister_driver(&nouveau_drm_pci_driver); | |
1194 | #endif | |
db1a0ae2 | 1195 | nouveau_backlight_dtor(); |
77145f1c | 1196 | nouveau_unregister_dsm_handler(); |
055a65d5 AC |
1197 | |
1198 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER | |
1199 | platform_driver_unregister(&nouveau_platform_driver); | |
1200 | #endif | |
94580299 BS |
1201 | } |
1202 | ||
1203 | module_init(nouveau_drm_init); | |
1204 | module_exit(nouveau_drm_exit); | |
1205 | ||
1206 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
1207 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1208 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 1209 | MODULE_LICENSE("GPL and additional rights"); |