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ebc326be NC |
1 | /* |
2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef SOC_NPS_COMMON_H | |
34 | #define SOC_NPS_COMMON_H | |
35 | ||
36 | #ifdef CONFIG_SMP | |
37 | #define NPS_IPI_IRQ 5 | |
38 | #endif | |
39 | ||
40 | #define NPS_HOST_REG_BASE 0xF6000000 | |
41 | ||
42 | #define NPS_MSU_BLKID 0x018 | |
43 | ||
44 | #define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E | |
45 | #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60 | |
46 | #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422 | |
47 | ||
60486724 VG |
48 | #ifndef AUX_IENABLE |
49 | #define AUX_IENABLE 0x40c | |
50 | #endif | |
51 | ||
52 | #define CTOP_AUX_IACK (0xFFFFF800 + 0x088) | |
53 | ||
ebc326be NC |
54 | #ifndef __ASSEMBLY__ |
55 | ||
56 | /* In order to increase compilation test coverage */ | |
57 | #ifdef CONFIG_ARC | |
58 | static inline void nps_ack_gic(void) | |
59 | { | |
60 | __asm__ __volatile__ ( | |
61 | " .word %0\n" | |
62 | : | |
63 | : "i"(CTOP_INST_RSPI_GIC_0_R12) | |
64 | : "memory"); | |
65 | } | |
66 | #else | |
67 | static inline void nps_ack_gic(void) { } | |
68 | #define write_aux_reg(r, v) | |
69 | #define read_aux_reg(r) 0 | |
70 | #endif | |
71 | ||
72 | /* CPU global ID */ | |
73 | struct global_id { | |
74 | union { | |
75 | struct { | |
76 | #ifdef CONFIG_EZNPS_MTM_EXT | |
77 | u32 __reserved:20, cluster:4, core:4, thread:4; | |
78 | #else | |
79 | u32 __reserved:24, cluster:4, core:4; | |
80 | #endif | |
81 | }; | |
82 | u32 value; | |
83 | }; | |
84 | }; | |
85 | ||
86 | /* | |
87 | * Convert logical to physical CPU IDs | |
88 | * | |
89 | * The conversion swap bits 1 and 2 of cluster id (out of 4 bits) | |
90 | * Now quad of logical clusters id's are adjacent physically, | |
91 | * and not like the id's physically came with each cluster. | |
92 | * Below table is 4x4 mesh of core clusters as it layout on chip. | |
93 | * Cluster ids are in format: logical (physical) | |
94 | * | |
95 | * ----------------- ------------------ | |
96 | * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)| | |
97 | * | |
98 | * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)| | |
99 | * ----------------- ------------------ | |
100 | * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)| | |
101 | * | |
102 | * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)| | |
103 | * ----------------- ------------------ | |
104 | * 0 1 2 3 | |
105 | */ | |
106 | static inline int nps_cluster_logic_to_phys(int cluster) | |
107 | { | |
108 | #ifdef __arc__ | |
109 | __asm__ __volatile__( | |
110 | " mov r3,%0\n" | |
111 | " .short %1\n" | |
112 | " .word %2\n" | |
113 | " mov %0,r3\n" | |
114 | : "+r"(cluster) | |
115 | : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST), | |
116 | "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM) | |
117 | : "r3"); | |
118 | #endif | |
119 | ||
120 | return cluster; | |
121 | } | |
122 | ||
123 | #define NPS_CPU_TO_CLUSTER_NUM(cpu) \ | |
124 | ({ struct global_id gid; gid.value = cpu; \ | |
125 | nps_cluster_logic_to_phys(gid.cluster); }) | |
126 | ||
127 | struct nps_host_reg_address { | |
128 | union { | |
129 | struct { | |
130 | u32 base:8, cl_x:4, cl_y:4, | |
131 | blkid:6, reg:8, __reserved:2; | |
132 | }; | |
133 | u32 value; | |
134 | }; | |
135 | }; | |
136 | ||
137 | struct nps_host_reg_address_non_cl { | |
138 | union { | |
139 | struct { | |
140 | u32 base:7, blkid:11, reg:12, __reserved:2; | |
141 | }; | |
142 | u32 value; | |
143 | }; | |
144 | }; | |
145 | ||
146 | static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg) | |
147 | { | |
148 | struct nps_host_reg_address_non_cl reg_address; | |
149 | ||
150 | reg_address.value = NPS_HOST_REG_BASE; | |
151 | reg_address.blkid = blkid; | |
152 | reg_address.reg = reg; | |
153 | ||
154 | return (void *)reg_address.value; | |
155 | } | |
156 | ||
157 | static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg) | |
158 | { | |
159 | struct nps_host_reg_address reg_address; | |
160 | u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu); | |
161 | ||
162 | reg_address.value = NPS_HOST_REG_BASE; | |
163 | reg_address.cl_x = (cl >> 2) & 0x3; | |
164 | reg_address.cl_y = cl & 0x3; | |
165 | reg_address.blkid = blkid; | |
166 | reg_address.reg = reg; | |
167 | ||
168 | return (void *)reg_address.value; | |
169 | } | |
170 | #endif /* __ASSEMBLY__ */ | |
171 | ||
172 | #endif /* SOC_NPS_COMMON_H */ |