sun7i: dts: add bananapro.

[people/arne_f/kernel.git] / arch / arm / boot / dts / sun5i-a10s.dtsi

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 64961595e8d63cafaaaf2373ce6e5a580a7e6879..0e79c4ee0afc3ec4099145f5ef6cfade9c4a1fbc 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -47,44 +47,48 @@
                        clock-frequency = <0>;
                };
 
-               osc24M: osc24M@01c20050 {
+               osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                       clock-output-names = "osc24M";
                };
 
-               osc32k: osc32k {
+               osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                       clock-output-names = "osc32k";
                };
 
-               pll1: pll1@01c20000 {
+               pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll1";
                };
 
-               pll4: pll4@01c20018 {
+               pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll4";
                };
 
-               pll5: pll5@01c20020 {
+               pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
 
-               pll6: pll6@01c20028 {
+               pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +97,23 @@
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                       clock-output-names = "cpu";
                };
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                       clock-output-names = "axi";
                };
 
-               axi_gates: axi_gates@01c2005c {
+               axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
@@ -115,12 +121,13 @@
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                       clock-output-names = "ahb";
                };
 
-               ahb_gates: ahb_gates@01c20060 {
+               ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -136,12 +143,13 @@
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                       clock-output-names = "apb0";
                };
 
-               apb0_gates: apb0_gates@01c20068 {
+               apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -152,19 +160,21 @@
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
                };
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                       clock-output-names = "apb1";
                };
 
-               apb1_gates: apb1_gates@01c2006c {
+               apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -176,7 +186,7 @@
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -184,7 +194,7 @@
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -192,7 +202,7 @@
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -200,7 +210,7 @@
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -208,7 +218,7 @@
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -216,7 +226,7 @@
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -224,7 +234,7 @@
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -232,7 +242,7 @@
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -240,7 +250,7 @@
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -248,7 +258,7 @@
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -256,15 +266,24 @@
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
 
+               usb_clk: clk@01c200cc {
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       compatible = "allwinner,sun5i-a13-usb-clk";
+                       reg = <0x01c200cc 0x4>;
+                       clocks = <&pll6 1>;
+                       clock-output-names = "usb_ohci0", "usb_phy";
+               };
+
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
@@ -373,7 +392,7 @@
                };
 
                wdt: watchdog@01c20c90 {
-                       compatible = "allwinner,sun4i-wdt";
+                       compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
 
@@ -383,7 +402,7 @@
                };
 
                rtp: rtp@01c25000 {
-                       compatible = "allwinner,sun4i-ts";
+                       compatible = "allwinner,sun4i-a10-ts";
                        reg = <0x01c25000 0x100>;
                        interrupts = <29>;
                };