clk: rockchip: Fix initialization of mux_pll_src_4plls_p

[people/arne_f/kernel.git] / drivers / clk / rockchip / clk-rk3228.c

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 04f4f3739e3bed0f0e90d77b77279a50837e03ee..8d11d76e1db7c62219791e5af6e0b19dbd655590 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -144,7 +144,7 @@ PNAME(mux_usb480m_p)                = { "usb480m_phy", "xin24m" };
 PNAME(mux_hdmiphy_p)           = { "hdmiphy_phy", "xin24m" };
 PNAME(mux_aclk_cpu_src_p)      = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
 
-PNAME(mux_pll_src_4plls_p)     = { "cpll", "gpll", "hdmiphy" "usb480m" };
+PNAME(mux_pll_src_4plls_p)     = { "cpll", "gpll", "hdmiphy", "usb480m" };
 PNAME(mux_pll_src_3plls_p)     = { "cpll", "gpll", "hdmiphy" };
 PNAME(mux_pll_src_2plls_p)     = { "cpll", "gpll" };
 PNAME(mux_sclk_hdmi_cec_p)     = { "cpll", "gpll", "xin24m" };